International Journal of Engineering Trends and Technology (IJETT) - Volume4 Issue7- July 2013
Impact of Voltage Scaled Repeaters on VLSI Based
CNT Interconnects
Sandeep Saini*1, Karamjit Singh Sandha#2
#
*M.E. E.C.E, Thapar University, Patiala, India
Asst. Professor, ECE Department, Thapar University, Patiala, India
Abstract— Carbon nanotubes (CNTs) have provided an
attractive solution over Copper at deep sub-micron level very
large scale integration (VLSI) technologies. Delay is one of the
major design constraints in very large scale integration (VLSI)
circuits. This paper presents an analysis of propagation delay
and effect of repeater insertion on propagation delay for both
CNT and Cu interconnects. It has been observed that CNT
interconnects have lower propagation delay than the Copper
interconnects. Also, propagation delay reduces as we increase the
number of repeaters. The above trends are studied with
technology node. In addition this paper deals with effect of
voltage scaling in repeaters loaded long interconnect in VLSI
circuits on propagation delay. It has been observed that
propagation delay reduces with the voltage.
used in this paper for modelling the Copper interconnects into
R, L and C parameters as shown in Fig.1 [3].
The Winbond TSM model Fig.2 [4], is for global layer
interconnect lines with coupling above one ground. Here
thickness of the interconnect is t, width of CNT bundle is w,
height of the interconnect above the ground is h.
Keywords— Interconnect, CNT, propagation delay, power
dissipation, repeater, voltage scaling.
I. INTRODUCTION
As VLSI technology advances over the years chip
complexity increases and the feature size decreases [1]. Thus,
both die size and device density of the VLSI circuits increase.
The use of long interconnect lines (global interconnects)
becomes essential due to the increased die size in VLSI chips.
For these global interconnects, conventional interconnect
technologies used by copper or aluminium fare badly because
of their increasing resistively with length which causes some
serious problems like electro migration and voids formation in
the successive levels of interconnect paths [2]. For this reason,
researchers introduced new materials such as carbon
nanotubes (CNTs) which seem to be a possible solution for
VLSI technologies of global interconnects.
II. COPPER INTERCONNECTS:
A lot of work has been done in the field of copper
interconnects regarding its circuit modelling and design
methodologies.
Fig.2 Geometry of Global Interconnects
Spacing between the interconnect S is assumed to be equal to
the interconnect width, i.e. S=W.
III. CARBON NANOTUBES INTERCONNECTS:
CNTs were discovered by Sumio Iijima of the NEC
Laboratory in Tsukuba in 1991. CNTs are made up by rolling
the graphene sheets at some angle thus producing hollow
cylindrical structures made up of carbon atoms as shown in
Fig.3 [5]. Graphene is a sheet of graphite having carbon atoms
at arranged in a hexagonal shape resembling a honeycomb
lattice. Carbon atoms here have sp2 bonding which is stronger
than sp3 bonding in diamond thus making graphene the
strongest material [6]. Also, CNTs have some other
favourable properties like high thermal conductivity and
mechanical strength [7],[8], long ballistic transport length[9],
and high current carrying capability[10]. These remarkable
properties make CNTs one of the most promising research
materials for future VLSI technology.
Fig.3 single-walled carbon nanotubes (SWCNT)
Fig.1 RLC Π-model representation of an interconnect line
Performance analysis is done by circuit modelling the
interconnects into R, L and C parameters. Π-circuit has been
ISSN: 2231-5381
CNTs are of two types, single-walled carbon nanotubes
(SWCNT) having single rolled sheet of graphene and multi-
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International Journal of Engineering Trends and Technology (IJETT) - Volume4 Issue7- July 2013
walled carbon nanotubes (MWCNT) [5] as in Fig. 4 which
have various concentric tubes of graphene.
Fig.6 Basic Nano interconnect circuit with one repeater
significantly by insertion of the repeaters at optimally spaced
points along the line[14].
Fig.4 Multi-walled carbon nanotubes (MWCNT)
Here, Π-circuit has been used for circuit modelling of
CNT interconnects. Instead of single CNT, bundled CNTs are
used for better electrical properties and mechanical strength.
The distance between adjacent SWNTs in bundle can be
found
Fig.7 m number of repeaters driving an interconnect divided into subsections
Fig.7 [13] above shows m number of repeaters inserted in
an interconnect divided into subsections. As the interconnect
is divided into subsections, the cumulative RC constant is
reduced. However, the additional delay due to repeaters has to
be taken into account.
A lot of work has been done regarding CMOS inverters.
These are the simplest buffers or repeaters in VLSI
interconnect. Figure.8 [13] shows a CMOS buffer driving a
interconnect load and its equivalent symbolic representation.
In this paper the effect of number of repeaters on the
propagation
delay
Fig.5 Cross-section of a SWNT bundle interconnects
from cross-section of a bundle, db=δ+d as shown in Fig. 5
[11].
Here, 𝜹 = 0.34 nm is the spacing between SWNTs in the
bundle and d is diameter of SWNT.
IV. REPEATERS IN INTERCONNECTS:
The long interconnect lines give high propagation delays
due to capacitive nodes thus degrading the performance of the
device. To drive these high capacitive nodes buffers are
needed. These buffers are also called repeaters. A basic
interconnect circuit with one repeater is shown in Fig. 6 [12].
A repeater reduces the propagation delay by mitigating the
charging-discharging effect of the capacitor [13].
But a single repeater offers a large RC (ResistiveCapacitive) load at the gate terminals connected to it. For
driving long interconnects a number of repeaters have to be
inserted at equal distances between the interconnect ends.
Therefore, in long interconnects,the propagation delay reduces
ISSN: 2231-5381
Fig.8 CMOS buffer driving an interconnect load and its equivalent
representation
for both CNT and Copper interconnects over the different
technology nodes have been analysed.
V. VOLTAGE SCALED REPEATERS FOR GLOBAL
INTERCONNECTS:
Several methodologies for designing the repeater driven
interconnect have been given in the literature. Broadly these
methodologies can be classified as: delay centric and
throughput (bits per second) centric. The primary objective of
the delay-centric design is optimization of number and size of
the repeaters to achieve minimum propagation delay. In the
other method, these optimizations are carried out to achieve
maximum possible throughput. Voltage-scaling is one of the
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International Journal of Engineering Trends and Technology (IJETT) - Volume4 Issue7- July 2013
most effective methods of containing power dissipation and
propagation delay. Deodhar and Davis [15] considered
voltage-scaled repeater system design. With the help of
SPICE simulation results, they demonstrated that voltagescaling could control power dissipation in a repeater system.
However, their approach being throughput-centric provides a
limited picture of how voltage-scaling would affect a delaycentric design. This paper deals primarily with the influence
of voltage-scaling on the optimum number of repeaters in a
delay-centric repeater-chain design for long interconnects.
The insertion of voltage-scaled repeaters in long
interconnections have shown new and encouraging results in
deep submicron technologies, it leads to a decrease in
optimum number of repeaters required to be inserted in a long
interconnect for delay minimization. Thus voltage scaled
repeaters can enhance the performance of the interconnects
largely. The performance of the voltage scaled repeaters is
analysed using Spice simulated results. All interconnect
parameters used in simulations are obtained from ITRS 2005
[16] as summarized in Table 1.
between
CNT
and
Copper
for
Fig.9 Comparison of delay between CNT and Copper (32nm)
respectively with various number of repeaters, these results
we observe that as we keep on increasing the number of
repeaters in the interconnect, the difference between the
propagation delay for CNT and Copper keep on narrowing.
The repeater Aspect Ratio has a fixed ratio of 40.
Table 1
ITRS 2005 based simulation parameters
Fig.10 Comparison of delay between CNT and Copper (22nm)
viz.1,3,5,7,9,11with various voltages for varying number of
repeaters. From Tables 2 and 3 below give the SPICE
simulated propagation delay for Copper and CNT
Interconnects respectively for 32nm technology. These values
are shown graphically in fig. 11 and 12. Here n is number of
repeaters inserted in the interconnect.
Table 2
Variation of propagation delay with „n‟ for different VDD values for 32nm
CNT
The aspect ratio (A/R) for global level interconnects in ITRS
is in the range of 2.5-2.8. For convenience, we have used
aspect ratio (A/R) =3.
n
VDD(V)
1
3
5
7
9
11
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
3.281
2.525
2.395
2.305
2.242
2.225
2.241
2.292
2.385
2.055
1.835
1.675
1.661
1.641
1.612
1.615
1.630
1.645
1.745
1.532
1.455
1.383
1.381
1.355
1.325
1.365
1.382
1.711
1.391
1.272
1.245
1.232
1.231
1.205
1.237
1.245
1.463
1.272
1.215
1.133
1.113
1.124
1.112
1.140
1.143
1.34
1.23
1.132
1.103
1.056
1.078
1.085
1.081
1.105
VI. RESULTS AND DISCUSSIONS:
The values of R, L and C for Copper and CNT have been
calculated through MATLAB. Propagation Delay in Copper
and CNT interconnects for 32nm, 22nm technologies is
calculated using SPICE simulation. Simulation is done here
for different no. of repeaters „n‟ viz. 1,3,5,7,9,11. Aspect ratio
of the inverters used here in the buffer is 40.
Fig. 9 and
1032nm and 22nm technologies gives the comparison of delay
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) - Volume4 Issue7- July 2013
Fig.11 Variation of delay with voltage for CNT(32nm)
Fig.13 Variation of delay with voltage for CNT (22nm)
Table 3
Variation of propagation delay with n for different VDD values for 32nm Cu
Table 5
Variation of propagation delay with n for different VDD values for 22nm Cu
n
VDD(V)
1
3
5
7
9
11
n
VDD(V)
1
3
5
7
9
11
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.635
2.815
2.781
2.575
2.565
2.751
2.532
2.461
2.605
1.935
2.125
2.171
1.845
1.821
1.803
1.812
1.825
1.871
1.665
1.660
1.795
1.631
1.630
1.465
1.505
1.495
1.505
1.612
1.515
1.445
1.315
1.310
1.300
1.331
1.325
1.345
1.519
1.408
1.315
1.255
1.213
1.185
1.242
1.241
1.260
1.425
1.245
1.213
1.165
1.125
1.151
1.115
1.156
1.172
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
4.851
4.855
4.842
4.821
4.830
4.811
4.825
4.945
4.855
3.465
3.304
3.425
3.360
3.411
3.375
3.483
3.565
3.695
2.554
2.715
2.635
2.725
2.771
2.705
2.455
2.681
2.795
2.255
2.201
2.163
2.141
2.245
2.246
2.245
2.245
2.281
2.095
2.026
1.975
1.915
1.865
1.941
1.970
1.975
1.991
1.967
1.905
1.825
1.775
1.713
1.710
1.755
1.805
1.793
Fig.12 Variation of delay with voltage for Copper(32nm)
Fig.14 Variation of delay with voltage for Copper (22nm)
Tables 4 and 5 give the SPICE simulated propagation delay
for Copper and CNT Interconnects respectively for 22nm
technology which is shown graphically in fig. 13 and 14.
Table 4
Variation of propagation delay with n for different VDD values for 22nm CNT
n
VDD(V)
1
3
5
7
9
11
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.616
2.451
2.347
2.252
2.231
2.275
2.215
2.295
2.355
1.765
1.655
1.565
1.501
1.512
1.465
1.501
1.540
1.552
1.485
1.285
1.265
1.245
1.225
1.215
1.215
1.223
1.251
1.285
1.176
1.132
1.075
1.069
1.084
1.061
1.086
1.111
1.205
1.094
1.015
1.023
1.014
1.006
1.007
1.002
1.029
1.175
1.035
0.969
0.964
0.947
0.939
0.929
0.953
0.971
ISSN: 2231-5381
VII. CONCLUSION:
The delay performance of CNT and Copper interconnects
have been compared for various number of repeaters. CNT
interconnects show significant improvement in performance
as compared to copper interconnects due to low resistivity.
Optimum delay can be achieved with the use of voltage scaled
repeaters. It has been observed from results that propagation
delay reduces with voltage scaling for same number of
repeaters. It has also been observed that lower delay can be
achieved with less number of repeaters at high voltage as
compared to more number of repeaters at less voltage.
REFERENCES
[1] Y. Leblebici et al., “CMOS Digital Integrated Circuits – Analysis and
Design”, TMH, New York, 2003.
[2] A. K. Goel, High-speed VLSI Interconnections, Willey-IEEE Press, Sep.
2007.
http://www.ijettjournal.org
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International Journal of Engineering Trends and Technology (IJETT) - Volume4 Issue7- July 2013
[3] Andrew B. Kahng et al., “Efficient Gate Delay Modeling for Large
Interconnect Loads” Proc. IEEE MultiChip Module Conf
[4] JD Meindel et al., “Interconnect opportunities for gigascale integration”,
International business Machine corporation, vol. 46, no. 2/3, pp. 256,
March/May 2002.
[5] Navin Srivastava et al., “Performance analysis of carbon nanotube
interconnects for VLSI applications,” Proc. IEEE/ACM Int.
Conf. ICCAD, pp. 383–390, 2005
[6] N Srivastava et al., “Carbon Nanomaterials for Next-Generation
Interconnects and Passives: Physics, Status and Prospects”. IEEE Trans.
Electron Devices. Res. 56, No. 9 pp-1799-1821. Sep 2009
[7] P. G. Collins, et al., “Current saturation and electrical breakdown in
multiwalled carbon nanotubes,” Phys. Rev. Lett., vol. 86, no. 14, pp. 3128–
3131, Apr. 2001.
[8] S. Berber, et al., “Unusually high thermal
conductivity of carbon nanotubes,” Phys. Rev. Lett., vol. 84, no. 20, pp. 4613–
4616, 2000.
[9] A. Javey, et al., Carbon Nanotube Electronics, Springer, 2009.
[10] B. Q. Wei, et al., “Reliability and current carrying capacity of carbon
nanotubes,” Appl. Phys. Lett., vol. 79, no. 8, pp. 1172–1174, Aug. 2001.
[11] A. Srivastava, et al., “A Carbon nanotubes for next generation very large
scale integration interconnects”. J. Nanophotonics. Res. 4, No. 041690, pp-126, May 2010
[12] H.B. Bakoglu et al., “Optimal interconnection circuits for VLSI”, IEEE
Transactions on Electron Devices, Vol. ED-32 No. 5, pp. 903-9, 1985
[13] Rajeevan Chandel, et al., Repeater insertion in global interconnects in
VLSI circuits, Emerald Group Publishing Limited, Microelectronics
International 2005.
[14] H.B. Bakoglu et al., Circuits, Interconnections and Packaging for VLSI,
Addison Wesley VLSI Systems Series, Reading, MA, 1990
[15] V.V. Deodhar, et al., “Voltage-scaling and repeater insertion for highthroughput low-power interconnects”, Proc. ISCAS’03 5, pp. v-349–352,
2003
[16] International Technology Roadmap for Semiconductors, 2005.
http://public.itrs.net/
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