International Journal of Engineering Trends and Technology- Volume3Issue5- 2012
Efficient RC low-power bus encoding
methods for crosstalk reduction
Gopaldas Sunil kumar, Patnam Samulu
Department of Electronics and Communication, RGMCET Nandyal, Kurnool, A.P.
Abstact: In on-chip buses, the RC
crosstalk effect leads to serious problems, such as
wire propagation delay and dynamic power
dissipation. Crosstalk noise is dominated by the
coupling
capacitance,
resulting
in
wire
propagation delay, logical malfunction and power
dissipation on on-chip buses. Therefore,
eliminating crosstalk effects have become a very
important consideration in the development of the
bus encoding design. This project presents two
efficient bus-coding methods. The proposed
methods simultaneously reduce more dynamic
power dissipation and wire propagation delay than
existing bus encoding methods. Our methods also
reduce more total power consumption than other
encoding methods. The proposed methods
transform the bus signal to reduce and eliminate
the worst crosstalk types, i.e. Type-4, Type-3, and
Type-2. They reduce power and wire propagation
delay by decreasing the switching and coupling
activities.
1. Introduction:
Crosstalk noise is dominated by the coupling
capacitance, resulting in wire propogation delay,
logical malfunction and power dissipation on onchip buses.capacitive couplings result in crosstalk
noise, power supply noise, and leakage noise in
deep submicron (DSM) technology. Coupling
capacitance results from parallel wires and adjacent
wire switching in opposite transition directions.
Data transmission reliability on bus lines is also
debased by wire propagation delay. In other words,
wire propagation delay degrades overall system
performance. Thus, the practical design process
must consider crosstalk effects.Inorder to decrease
dynamic power dissipation and wire propagation
delay on buses, system engineers present several
kinds of options to solve these problems. The first
option is that a shielding line (VDD/Ground) can
be inserted between two adjacent signal lines. This
method is separated into the passive shielding and
ISSN: 2231-5381
the active shielding. Although this method results
in a larger chip area, it eliminates the worst
crosstalk effects. The second option is that we can
use placeand route tools to avoid routing bus lines
side by side. Inorder to reduce switching activty the
previous well knownare INC-XOR,T0,T0-XOR
coding schemes are desined for instruction buses.
Bus-invert (BI), and partial bus-invert (PBI)
coding schemes are designed for data buses, which
are generally random. The number of transmitting
transitions does not exceed half of the bus width.
To limit transmitting transitions, it uses an extra
control line.When the number of transmitting
transitions is more than half of the bus width, the
original data are inverted and the control line is set
to ‘‘High’’; otherwise, the original data are
transmitted and the control line is set to ‘‘Low’’. In
other words, the original data bus width is changed
from 8-bit to 9-bit, from 16-bit to 17-bit, or from
32-bit to 33-bit. The PBI method, i.e. an extension
of the BI method, partitions bus lines into two
parts, and then encodes each part with the BI
method. Thus, the PBImethod offers greater
advantages than the BI method, but it requires
additional control lines. For instance, the PBI
method increases two extra control lines on an 8-bit
bus. In other words, the original data bus width is
changed from8-bit to 10-bit, from 16-bit to 20-bit,
and from 32-bit to 40-bit after the PBI method is
applied. The proposed bus encoding design can
reduce dynamic power dissipation and wire
propagation delay simultaneously on on-chip buses.
The proposed methods transform the bus signal to
reduce and eliminate the three worst crosstalk
types, i.e. Type-4, Type-3, and Type-2.They reduce
power and wire propagation delay by decreasing
the switching and coupling activities. Simulation
results show that by simulating various random
data streams, they decrease more dynamic power
dissipation and wire propagation delay than othe
rmethods presently used in the bus encoding
design.Both they fully eliminate the Type-4
coupling, and greatly decrease the Type-3 coupling.
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International Journal of Engineering Trends and Technology- Volume3Issue5- 2012
2. Power Expressions in RC Buses:
There are two majorfor crosstalk nmoises
areavailalable they are load capacitances (CL), and
coupling capacitances (CC), and the total
capacitances are increased by operating the
coupling and load capacitances inparallel. A load
capacitance indicates the wire-to- ground
capacitance. A coupling capacitance is located
between the wire and its adjacent wires. Coupling
capaci- tances in SoC systems are several times
largerthan load capacitances.Crosstalk effects apply
Eq.(1) as follows as:
Ceff Cc*|(V2 V1)/ E| Cc*|(V2 V3)/ E|
PD,coded = (α CL *C L +α Cc *Cc )*V
= (α CL +λ*α Cc )*C L *V
DD
2
DD
*f
*f
Where f is the clock frequency and λ is the
capacitance ratio and defined as,
λ = Cc /CL
3. Crosstalk on RC buses:
As explained earlier different crosstalk are
available.they are catogirised as five different
types.
Table 1 shows the five-crosstalk effects. For a 3bitbus, a Type-0 coupling occurs if the 3-bit data on
the bus is transited with the same transitional
direction. For example ,at ransition from 000to111
ISSN: 2231-5381
Table 1: Crosstalk types
Type0
Type1
Type2
Type3
Type4
−−−
−−↑
↑↓↓
−↑↓
↑↑↓
↓↓↓
−↑↑
↓↑↑
−↓↑
↓↓↑
↑↑↑
↑−−
↑↓−
↑↓↑
↑↑−
↓↑−
↓↑↓
(1)
Where ∆V2,∆V1,∆V3 are the voltage variations of
the centerwire and adjacent wires,E is the power
supply voltage which equals rail-to-rail signal
voltage in cmos circuits,Ceff is the coupling
capacitancevariation.
The crosstalk effects of interconnect bus
characteristics to be a simple case of three adjacent
wires. Dynamic power dissipation, which is
generated by load capacitances, is proportional to
the number of signal transitions on buses. On the
other hand, power dissipation is also generated by
coupling capacitances, and they result from relative
signal transitions between coupled bus lines. The
Dynamic power consumption on a coding bus is
calculated as follows:
2
(i.e.↑↑↑) causes a Type-0 coupling.Three
conditions cause a Type-0 coupling. For a Type-0
coupling, the coupling capacitance is zero. A Type1 coupling occurs when1-bit or 2-bit data is
changed between the(B(t), Inv(t)) data value and
the (B(t_1), Inv(t_1)) data value. For example, a
transition from 001 to 101 (i.e↑−−) causes a Type-1
coupling. Eight conditions cause a Type-1
coupling. For a Type-1 coupling, the coupling
capacitance is CC.
−−↓
−↓↓
↓−−
↓↓−
Switching from “0’ to “1” : ↑,switching from
“1”to “0 ” : ↓
The occurrences of Type-2 coupling are shown as
follows. For example, the data is changed from 100
to 011 (i.e.↓↑↑) or from 010 to 000 (i.e.−↓−), which
causes a Type-2 coupling. Ten conditions cause a
Type-2 coupling. For a Type-2 coupling, the
coupling capacitance is 2. CC. A Type-3 coupling
occurs when the center wire under goes the
opposite state transition with one of the two wires
while the other wires are quiet. For example, the
data is changed from 010 to 001(i.e. −↑↓), which
causesaType-3 coupling and the coupling
capacitance of 3. CC. Four conditions cause a
Type-3 coupling. For a Type-4 coupling, all threewire transitions act in the opposite states with
respect to eachother and their previous bus state.
For example, the data is changed from 010 to
101(i.e. ↑↓↑), which causes a Type-4 coupling with
the coupling capacitance of 4. CC. Two conditions
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International Journal of Engineering Trends and Technology- Volume3Issue5- 2012
causeaType-4 coupling. The worstcrosstalke ffects
indicate theType-2,Type-3and Type-4 couplings.
We define the symbol swhich are used throughout
the paper as follows:
b (t): The multiple-bit bus value is sent presently on
the bus at time t (source wordattime t).
b (t_1): The multiple-bit bus value is sent
previously on the bus at time t_1 (source word at
time t_1).
B (t): The encoded multiple-bit bus value is sent
presently on the bus lines at time t (encoding code
word at time t)
.
B (t_1) the encoded multiple-bit bus value is sent
previously on bus lines at time t_1 (encoding code
word at time t_1).
Inv (t):
A bus line for acting the bus is
invertedornot at time t.
Inv (t_1): A bus line for acting the bus is
invertedornot at time t_1.
4. Bus Invert Methods:
In method 1 there are N4 count_0 and N4 count_1
are there they are used for detecting type 4
crosstalk.If any such type of crosstalk exists this
N4 block will find and the output will be the
inverted forn of input.N3 count_0 and N3 count_1
are there for finding existance of type 3 crosstalk
which was explained in the table.If any such kind
crosstalk exists this module will detect and the
output will be the inverted form of input.in method
1 we are unable to find the typr crosstalkl even
though it exists we are unable to find.the outputs of
N4 count and N3 count are one and two bits these
outputs are fed to multiplexer where thes are
considered to be the selection lines and the inputs
are present inputs and inverted inputs,with the help
of those selection lines the mux is going to select
one of the inputs as output. And that output fed to
an register where this will used for next as an
previous input.In method 1 we are only able to
reduce type 4 and type 3 completely.
To treduce the crosstalk effects two methods were
proposed and are specially applied to three adjacent
wires.they treduce not only not only dynamic
power consumptionbut also wire propogation
delay. Therefore they improve overall system
reliability. To reduce the coupling activites from
crosstalk effects, we present two bus invert
methods to reduce dynamic power consumption
and wire propogation delay.
4.2 Metod 2
In method 1 we are only able to find the type 4 and
type 3 only which wii be considered as an
limitation. Moreover type 2 crosstalk was also had
worse effects. Hence type 2 should be reduced.
Inorder to reduce type 2 one more module has to be
added for the existing method 1.Hence N2 count_0
and N2 count_1 has to added to the existing
method 1.
4.1 Metod 1
The proposed methodI divides the bus width into
several clusters. Each cluster has a 4-bit width and
an extra control bit. After the bus encoding is
applied,the n-bit bus extends to n+n/4 bits. The bus
encoder outputs the inverts of the input data when
the original input data and the previous bus state,
i.e.((b(t), 0) and (B(t_1), Inv(t_1))) cause the Type2,3 ,or 4 crosstalk effect.
Block diagram of method 1
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Block diagram of method 2
The block diagram of method 2 was shown
above.this was modified version of method1 where
some extension was made i.e N2 count was
included to it. The outputs of N4 count, N3 count
and N2 count are one, twoand one bit. These fed to
the multiplexer as selection lines.Depending up on
the above modules if crosstalk occurs in any
module its output was considered as 1, otherwise as
0.To the mux present input and inverted inputs are
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International Journal of Engineering Trends and Technology- Volume3Issue5- 2012
fed based upon the selection lines the
corresponding input is going to be selected as
output.If crosstalk ocuurs in any of the module the
output is the inverted form of input otherwise same
was received as output.
if(A1 == 1)
B(t) = b(t)
Inv(t) = 1
else if(D1 == 1)
B(t) = b(t)
Inv(t) = 0
else if(B1 > C1)
Table 2:
Bus
Method 1(n.s)
Method 2(n.s)
width
4
2.585
3.330
8
2.585
3.316
16
2.637
3.316
32
2.637
3.316
Delays associated with two methods
6. Conclusion:
B(t) = b(t)
The two methods 1&2 are two novel bus encoding
methods to reduce efficiently dynamic power
dissipation and wire propagationdelay on
buses.Both the proposed methods reduce more
dynamic
power
dissipation,total
power
consumption, and wire propagation delay than
existing bus encoding methods. Mean while, our
methods also reduces total power consumption 8bit to 32-bit data buses.
Inv(t) = 1
else if(B1 < C1)
B(t) = b(t)
Inv(t) = 0
else if(E1 == 1)
B(t) = b(t)
Inv(t) = 1
else
B(t) = b(t)
References:
Inv(t) = 0
The above algorithm was implemented for method
2 where it finds all the three worst crosstalks.
Method 2 helps us in detecting the type4, type3 and
type2 and also in eliminating them.
5. Results after simulation:
After trying so many combinations of various
inputs for 4bit, 8bit, 16bit, 32bit method1
eliminates type4 and type3,where as method 2
eliminates type4, type3 and type2 as well.These
two methods reduce switching transitions therefore
coupling capacitances were reduced to some extent.
Therefore dynamic power dissipation was also
reduced,the propogation delay was also reduced
and was tabulated as fallows.
[1] W.-W. Hsieh, P.-Y. Chen, C.-Y. Wang, T.T.
Hwang, A bus-encoding scheme for crosstalk
elimination in high-performance processor design,
IEEE Transac- tions on Computer-Aided Design of
Integrated Circuits and Systems 26 (12) (2007)
2222–2227.
[2] K.-H. Baek, K.-W. Kim, S.-M. Kang, A low
energy encoding technique for reduction of
coupling effects in SoC interconnects, in:
Proceedings of the 43rd IEEE Midwest Symposium
on Circuits and Systems, vol. 1, 8–11 August 2000,
pp. 80–83.
[3] B. Victor, K. Keutzer, Bus encoding to prevent
crosstalk delay, n: Proceedings of the IEEE/ACM
International Conference on Computer Aided
Design, 4–8 November 2001, pp. 57–63.
[4] K. Hirose, H. Yasuura, A bus delay reduction
technique considering crosstalk, in: Proceeding
Design, Automation and Test in Europe
Conference and Exhibition, 27–30 March 2000, pp.
441–445.
[5] R. Ayoub, A. Orailoglu, A unified
transformational approach for reductions in fault
vulnerability, power, and crosstalk noise and delay
on processor buses, in: Proceedings of the ASP-
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology- Volume3Issue5- 2012
DAC Design Automation Conference, vol. 2, 18–
21 January 2005, pp. 729–734.
[6] S. Ramprasad, N.R. Shanbhag, I.N. Hajj, A
coding framework for low-power address and data
busses, IEEE Transactions VLSI Systems 7 (2)
(1999) 212–221.
[7] L. Benini, G. De Micheli, E. Macii, D. Sciuto,
C. Silvano, Asymptotic zero- transition activity
encoding for address busses in low-power
microprocessor- based systems, in: Proceedings of
the Seventh Great Lakes Symposium on VLSI, 13–
15 March 1997, pp. 77–82.
[8] W. Fornaciari, M. Polentarutti, D. Sciuto, C.
Silvano, Power optimization of system-level
address buses based on software profiling, in:
Proceedings of the Eighth International Workshop
on Hardware/Software Codesign, 2000, pp. 29–33.
[9] M.A.Elgamel, M.A.Bayoumi, Interconnect
noise analysis and optimizationin deep submicron
technology, IEEE Circuits and Systems Magazine
3(4)(2003) 6–17.
[16] T. Lindkvist, J. Lofvenberg, O. Gustafsson,
Deep sub-micron bus invert coding, in:
Proceedings of the Sixth Nordic Signal Processing
Symposium, June 2004, pp. 133–136.
[17 ]Chih-Peng Fan,Chia-Hao Fang Efficient RC
low power bus encoding methodsfor crosstalk
reduction.
Gopaldas Sunil Kumar pursuing M.Tech second
year at RGMCET Nandyal.He received B.Tech
from VITS Proddatur in 2009..He was currently
working as an Assistant Professor in Department of
Electronics and Communication Engineering,
GITAMW ,Proddatur.
.
Patnam Samulu currently working as an Assistant
Professor in Department of Electronics and
Communication Engineering at RGMCET,
Nandyal since 2006..He recived his M.Techfrom
SV University, Thirupathi in 2006 and recived
B.tech from RGMCET Nandyal.
[10] C.-G.Lyuh, T.Kim, Low-power bus encoding
with
crosstalk
delay
elimination,
IEE
Proceedings—Computers and Digital Techniques
153(2)(2006)93–100.
[11] Z.Khan, T.Arslan, A.T.Erdogan, Low power
system on chip bus encoding scheme with crosstalk
noise reduction capability, IEE Proceedings —
Compu-ters and Digital Techniques 153 (2)
(2006)101–108.
[12] Y.Zhang, J.Lach, K.Skadron, M.R.Stan,
Odd/even bus invertwith two-phase transfer for
buse swithcoupling ,in: Proceedings of the 2002
International Symposium on Low Power
Electronics and Design ,2002,pp.80–83.
[13] X.Lin, P.Qiu, Q.Qiu, Partitioned bus coding
for energy reduction, in: Proceedings of the ASPDAC, vol.2,18–21 January 2005, pp.1280–1283.
[14] S.W.Tu, Y.W.Chang, J.Y.Jou, RLCcouplingaware simulation and on-chipbus encoding for
delay reduction, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
25 (10) (2006)2258–2264.
[15]
K.Takeuchi,
K.Yanagisawa,
T.Sato,
K.Sakamoto, S.Hojo, Probabilistic crosstalk delay
estimation for ASICs, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and
Systems 23(9)(2004)1377–1383
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