International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
Development of Transponder Simulator for SSR
B. Sindhuja, N. Naga swathi
M.tech student, Assistant Professor,
Department of ECE, Bapatla Engineering College,
A.P,India
Abstract- In this project, a generic of the radar transponder
response was designed on FPGA. The design on the
transmitting pulse p1,p2 and p3,Pulse detection and mode
generation and Transponder with delays are user configurable
through a graphical user interface(GUI).The radar
transponder response based on the secondary surveillance
radar. It is designed for real time application using vector
signal transceiver (VST).
RTR are an essential requirement in the defense
industry for Electronic Counter Measure (ECM) and
performance evaluation of radars without the need of
expensive trips and interference from commercial wireless
devices. The current design is capable of Transmission of
pulse P1,P2 and P3, and delay calculation and mode
selection, Range detection in real time and operates based on
the principle of Digital Radio Frequency Memory (DRFM),
which presents a reliable method for storing the Radio
Frequency (RF) signal in digital format. Before regenerating
the stored waveform for transmission, of the pulse P1,P2 and
P3and mode selection & Range of the target being presented
to RUT are incorporated into the waveform through vector
data modifications & corresponding delay respectively.
Multiple targets are simulated through cascading the
hardware with synchronization of their local oscillators. The
algorithm to perform the required signal processing is
designed specifically for VST using the FPGA module of
National Instrument’s LabVIEW software, and tested on the
same.
1. Introduction
This chapter serves as an introduction to the report. It
starts with presenting an overview of the project. Later
on, the principle idea behind initiating the project is
described. Then we move on to the approach used to
address the problem and describe the expected outcomes
of the work. The chapter concludes by providing the
necessary support from various literatures that lead to
opting for the current approach.
1.1 Overview:
Radar (acronym for Radio Detection and
Ranging) is an object-detection system that uses radio
waves to determine the range, altitude, direction, or
speed of objects. It can be used to detect aircraft, ships,
spacecraft, guided missiles, motor vehicles, weather
formations, and terrain. The cost, time and effort that
goes in testing the Radars, on the fields are immense.
So, it is of considerable importance in developing a
Radar Transponder (RTR) for testing these systems in
laboratory before opting for field evaluation. Thus, the
current project revolves around designing and
ISSN: 2231-5381
developing a Radar Transponder which is capable of
providing required stimulus to the Radar Under Test
(RUT) in a laboratory/ controlled conditions, enabling to
carry out the performance evaluation and measure
system‟s response. Apart from testing the Radar, it can
also be used to measure the Radar‟s performance and
delay calculation, time spacing, range of the target.
The secondary surveillance radar using the
transmitting pulse p1,p2 and p3 by ground antenna we
are using the interrogate by the particular target by using
transponder to transmitting and reception. By
transmitting the pulse at p1 and p2,p3 pulse the main
beam p1 and p3 is high, p2 is low, the side beam p2 act
like control beam. in this way we are generating
multiple target .the spacing of p1 and pe3 we are
generating the mode selection. Capturing the Radar‟s
signal and retransmitting them is an old technique used
in Electronic Counter Measure (ECM) techniques, to
create false targets on enemies Radars. This is an active
jamming method used to avoid being hit by enemies
.The RTS works on similar grounds; it captures the
Radar‟s Transmitted signal (Tx) and retransmits it back.
RUT detects/assumes the presence of targets from the
Received signal (Rx) , thus facilitating the performance
evaluation of RUT without requirement for field
testing. The captured signal can be modified to present
the RUT with targets of different ranges, velocities,
Radar Cross Section (RCS) areas, directions by varying
various aspects of the signal. Traditional methods use
analog memory loops to store the RF signal, which
creates lot of signal degradation. With the advent of
high-speed electronics like Field Programmable Gate
Array (FPGA), this problem has been resolved using
„Digital Radio Frequency Memory (DRFM)‟ mode of
operation.
1.2 Objective:
The objective of the thesis is to develop a RTR
that can present multiple moving targets to RUT. The
features that are to be incorporated currently include
simulation of multiple targets with the Mode Selection
and delay generation, range of the target. These
parameters should be user configurable via a Graphical
user interface (GUI).
As mentioned in the previous chapter the problem has
been solved using a technique called „DRFM‟.
http://www.ijettjournal.org
Page 41
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
Therefore, the prime focus is laid in developing a
DRFM circuit in FPGA, which enables the storing &
modifying of a signal via a signal-processing algorithm
to include the presence of targets and their Spacing of
pulse. The DRFM circuit has to be implemented on
National Instrument‟s (NI) proprietary device Vector
Signal Transceiver (VST) /NI -5644R.
To fulfil the objective of the project, the entire design
process has been divided into different parts:
 The initial step involves introducing
target‟s presence & Spacing of pulse
between p1 and p3.
 The second part introduces Mode
selection.
 The final step is to simulate multiple
targets and rang of the target.
In the subsequent section various methods to
achieve the goals were surveyed. It also discusses the
way the these methods achieved the objective .
1.3 Literature Survey:
This section discusses about various methods
implemented in designing RTR for different purposes.
In [1] a FPGA based design of multi level RTR was
developed. The RTR can simulate target echoes at
video, intermediate frequency (IF) and radio frequency
(RF) levels. It can be operated in two different modes ;
Synthesis and DRFM modes. In synthesis mode the
RTR generates the stored waveform codes of
transmitted radar‟s pulses, while in DRFM mode the
radar‟s transmitted signal is captured down converted to
an Intermediate frequency and required delay and other
parameters are added and then converted back to Radio
Frequency (RF) before retransmitting it back .
In [2] a RTR was developed based on the Direct
Digital Synthesis (DDS) technique . The idea was to
perform the radar‟s performance evaluation through a
feed –through signal method between the transmitter
and receiver antenna for pulse p1, p2 and p3 radar‟s,
conventional pulsed radar‟s (with pulse width at
0.8usce) and LFM pulse compression Radar‟s. In each
of the above modes the RTR generates the phase
coherent transmit signals to simulate the target echoes
with range , pulse spacing and Mode selection. This
stand Mode scelation are use in radar testing different
algoritams.
1.4 Approach:
The survey provided several options to choose from
for the design process. The current project has
incorporated the idea of including Range , Mode
seletion and Multiple targets dealys from [2] for a
Linear Frequency Modulation, paly back of the signal.
The DRFM mode of operation was chosen over
synthesising or Digital Direct Synthesis (DDS) method
ISSN: 2231-5381
as real time evaluation of the RUT was of priority over
testing the RUT with stored waveform codes using feedthrough signal method from [1,5,9]. Thus the system
down converts the received radar‟s signal to IF and
gives it to Analog to Digital Convertor (ADC) to add
the required changes and gives it back to DAC. It is
then up converted to RF. The design is based for Xilinx
Vertex-6 FPGA board present inside the Vector Signal
Transceiver (VST).
1.4.1 Expected Outcome:
The prime focus of the project is to design a
system that can used to test radars, thus the current RTR
design should be able to take the input from the radar
signal pulse generating p1,p2 and p3 and spacing of p1
and p3,Mode selection and process it to add the presence
of targets with range and velocity effects in real time
being use controllable through a Graphical User
Interface (GUI).
At hardware level National instrument's (NI)
latest proprietary technology Vector Signal Transceivers
(VST) were used .The VST has the functionality of both
Vector Signal Analyser (VSA) and Vector Signal
Generator (VSG) put together into single block. In
addition, it also provides the flexibility of performing
the required Digital Signal Processing (DSP) operations
using in-built FPGA Vertex-6 board, latest in its class.
VST ,the PXIe(PXI Express) module is a software
configurable device; the module can be fully configured
as per user's requirements using NI's ''LabVIEW '' &
''LabVIEW -FPGA module '' software.
By comparing the requirements the design demands
and specifications of VST , the design of RTR seems
practically possible by providing the receiver with the
radar pulse transimtting , doing the DSP on FPGA board
and then play back the RTR‟s output through
Transmitter. It also provides the facilities to give the
control parameters required for DSP operations through
the PXIe bus present in the back plane when integrated
with the PXIe-1085 chassis along with
suitable
controller ( say here - NI PXIe 8135 ).
2.1 NI’S Lab VIEW
Lab VIEW (stands for Laboratory Virtual
Instrument Engineering Workbench) is a system-design
platform and development environment for a visual
programming language from National Instruments (NI).
Its graphical nature makes it ideal for test and
measurement, automation, instrument control, data
acquisition, and data analysis applications. A Virtual
Instrument (VI) is a Lab VIEW programming element.
A VI consists of a front panel, block diagram, and an
icon that represents the program. The front panel is used
to display controls and indicators for the user, and the
block diagram contains the code for the VI. The icon,
which is a visual representation of the VI, has
connectors for program inputs and outputs. VIs are
http://www.ijettjournal.org
Page 42
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
similar to the functions and subroutine elements of C
and BASIC programming language. A VI may be used
as the user interface or as a subroutine in an application.
An elaborate front panel can be created without much
effort to serve as the user interface for an application.
class performance, which is the prime requirement in
designing the Radar Target simulator.
Lab VIEW is not an interpreted language; it is compiled
behind the scenes by Lab View‟s execution engine.
Similar to Java, the VIs are compiled into an executable
code that Lab View‟s execution engine processes during
runtime.
2.1.1 LABVIEW-FPGA Module:
The Lab VIEW-FPGA module is an extension
of the design software LabVIEW from National
Instruments. LabVIEW and the Lab VIEW FPGA
Module deliver graphical development for FPGA chips
on NI reconfigurable I/O (RIO) hardware targets. With
the LabVIEW FPGA Module, you can develop FPGA
VIs on a host computer running Windows, and
LabVIEW compiles and implements the code in
hardware. You can create embedded FPGA VIs that
combine direct access to I/O with user-defined
LabVIEW logic to define custom hardware for
applications such as digital protocol communication,
hardware-in-the-loop simulation, and rapid control
prototyping. In the current project the FPGA targets are
used for hardware-in-the-loop simulation
While the LabVIEW FPGA Module contains
many built-in signal-processing routines, you can also
integrate existing hardware description language (HDL)
code as well as third-party IP including Xilinx CORE
Generator functions. In addition, LabVIEW FPGA
integrates with both Mentor Graphics ModelSim and
included Xilinx ISim tools for cycle-accurate simulation
of logic. It also allows to define own control algorithms
with loop rates up to 300 MHz.
2.2 Hardware Tools:
This section deals with all the hardware tools
used directly or indirectly while developing RTS. It
starts with VST then moves to 16-bit ARB, RFSA,
PXIe-1085 chassis and concludes by FPGA –Xilinx
Vertex -6 board.
2.2.1 Vector Signal Transceiver:
The NI PXIe-5644R/5645R/5646R vector
signal transceivers (VSTs) are part of a new class of
instrumentation that combines a vector signal generator
and vector signal analyzer with FPGA-based real-time
signal processing and control. Because of this softwaredesigned approach, a VST features the flexibility of
software defined radio architecture with RF instrument
ISSN: 2231-5381
Figure 2.1 Vector Signal Transceiver
standards such as IEEE 802.11ac with an error vector
magnitude of better than -45 dB (0.5 percent) at 5.8
GHz. In addition, you can easily expand the VST's small
3-slot 3U PXI Express form factor to support multiple
input, multiple output (MIMO) configurations. The
software for the VST is built on NI LabVIEW FPGA.
2.2.2 16-Bit Arbitrary Waveform Generator
The NI PXIe-5451 is a 16-bit, 400 MS/s, dualchannel arbitrary waveform generator. It features both
single-ended and differential outputs with two analog
paths for maximum flexibility and performance. The NI
PXIe-5451 is the ideal instrument to test devices with
I/Q inputs, generate multiple wideband signals, or serve
as the baseband component of an RF vector signal
generator, which thus can be used to generate the radar‟s
baseband signal.
It also features onboard signal processing
(OSP) functions that include digital upconversion, pulse
shaping and interpolation filters, gain and offset control,
and a numerically controlled oscillator (NCO) for
frequency shifting. Common applications include
prototyping, validating, and testing of semiconductor
components and communications, radar, and electronic
warfare systems.
http://www.ijettjournal.org
Page 43
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
star trigger for PXI modules and a built-in 100
MHz reference clock, SYNC100, and PXI differential
star trigger for PXI Express modules. It is capable of 4
GB/s of per-slot bandwidth and 12 GB/s of system
bandwidth, enabled by PCIe x8 Gen 2 links to every
slot. Monitoring the chassis health information remotely
with the Ethernet connection on the rear of the chassis
via a web service portal is also possible.
Figure 2.2: Radio Frequency Spectrum
Analyser
2.2.3 Radio Frequency Spectrum Analyser:
2.2.5 PXIE –Embedded Controller (NI- 8135):
The NI PXIe-8135 is a high-performance Intel
Core i7-3610QE processor-based embedded controller
for use in PXI Express systems. With the 2.3 GHz base
frequency, 3.3 GHz (single-core, Turbo Boost mode)
quad-core processor, and dual-channel 1600 MHz
DDR3 memory, this controller is ideal for processorintensive modular instrumentation and data acquisition
applications.
The NI PXIe-5665 is a modular, three-stage
superheterodyne analyzer that you can use both as a
spectrum analyzer and a vector signal analyzer to
perform signal measurements over a frequency range
from 20 Hz to 14 GHz with options for 25 MHz and 50
MHz of instantaneous bandwidth. This new RF
instrument has exceptionally low phase noise of -129
dBc/Hz at a 10 kHz offset at 800 MHz, and an average
noise level of -165 dBm/Hz.
2.2.4 PXIe-1085 CHASSIS:
The NI PXIe-1085 18-slot chassis features a highbandwidth, all-hybrid backplane to meet a wide range of
high-performance test and measurement application
needs. The hybrid connector type in every peripheral
slot enables the most flexibility in terms of
instrumentation module placement. It also incorporates
all the features of the latest PXI specification including
support for both PXI and PXI Express modules with a
built-in 10 MHz reference clock, PXI trigger bus, and
PXI
Figure 2.3: PXIe 1085 chassis
ISSN: 2231-5381
Figure
2.4: Embedded controller/Host (NI-8135)
3.Implementation & Testing
The current chapter deals with the methodology &
implementation of the RTR using SSR. It begins with
discussion about choosing DRFM mode of operation
over synthesis or direct-feed through signal methods.
Then the discussion moves on to the implementation of
the DSP algorithm in LabVIEW for VST.
3.1 Methodology:
The RTR in SSR design should be able to meet the
basic requirements of Radar testing system to use for
performance evaluation of the RUT. Therefore, the RTS
design should focus on simulating more of realistic
environment rather being able to provide controlled
testing environment. It is this requirement that drives the
design process towards opting DRFM mode of operation
rather than DDS or synthesizing and feed –through
signal methods of operation.
In most of RTS In SSR using the DDS
method, i.e. Direct Digital Synthesis method the radar„s
waveform code is stored, changes to the code according
to the entered simulating parameters are made, and the
waveform is generated and transmitted. Those using
synthesis and feed-through method use one of the
http://www.ijettjournal.org
Page 44
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
various pre-stored waveform codes, which have in-built
effects of the simulating environment for generation.
While in DRFM mode, the Radar„s signal given out by
the RUT is captured, processed and retransmitted back
to RUT. Thus if the RUT changes the waveform code
for every pulse, the same will be reflected in the output
of the RTS also making it more dynamic and realistic in
nature.
3.1.1 Digital Radio Frequency Memory:
Digital Radio Frequency Memory (DRFM) is an
electronic method for digitally capturing and
retransmitting RF signal. DRFMs are typically used in
radar jamming, although applications in cellular
communications are becoming more common. A DRFM
system is designed to digitize an incoming RF input
signal at a frequency and bandwidth necessary to
adequately represent the signal, and then reconstruct that
RF signal when required. The digital "duplicate" of the
received signal is coherent with the source of the
received signal. There is no signal degradation, which
allows for greater range errors for reactive jamming and
allows for predictive jamming. It allows modification of
signal prior to retransmission adjusting its apparent
radar cross section, range, velocity, and angle altering
the signature of the false target.
Considering the peak power of both the components
to be equal then the resultant power is :
=
2∗|I|.............................. (4.3)
Thus, there is a resultant 3dB increase of power,
which is advantageous while both transmitting and
receiving the signal.
The third advantage is that the heading of the
target can also be obtained from I/Q processing. In
traditional processing the Doppler shift reflects moving
targets, but by using I/Q method the heading of the
target can be obtained as objects moving towards and
away creates opposite effects in I/Q components.
3.1.3 Range:
The range is the distance at which the detected target is
present. This distance, i.e. the distance to the target
relative to the radar„s location is given by the equation
given below:
=∁× /2.............................. (3.4)
Where
R= Range of the target relative to the radar„s position.
∁= velocity of light in vacuum/ Air.
T= time taken for the echo to reach the radar„s receiver.
Thus from the above equation it is vivid that
the range R„ of the target to be simulated is proportional
to the delay in receiving the echo of the transmitted
pulse T„ at the RUT. Therefore, by imparting a delay
corresponding to the range to be simulated using
DRFM, the concept of simulating the range of the target
can be achieved. It should be taken care that the delay
imparted falls under the unambiguous range of the RUT
and must be user configurable.
Figure 3.1: DRFM block diagram
This blind phase problem can be solved using the Inphase/Quadrature-Phase (I/Q) sampling. In this method,
the signal is down converted using two Local Oscillators
(LO) exactly 900 degrees out of phase. Thus when one
component become zero the other reaches its extreme
value enabling the detection of target as shown in lower
part fig.
Second advantage, I/Q processing also gives power
advantage.
=
............................ (3.2)
Where
P = Resultant power
|I | = Peak power of ‗I„component.
|Q| = Peak power of ‗Q„component.
ISSN: 2231-5381
The maximum range as per by specifications is
350Kms which corresponds to a delay of 2.3333ms and
the minimum delay that has to be created has for 5Kms
range is 38.889us.
3.1.5 Multiple Targets:
The RTR should have the capability to simulate
multiple targets simultaneously to test the Track while
scan„ and other advanced tracking capabilities of RUT.
This requires creating target echoes that replicate the
real time continuous echoes coming from different
targets. This is achieved by cascading the Hardware
component, which is actually replicating the targets i.e.
VST. The MIMO configuration is achieved by
synchronization all the cascaded VST„s Local
Oscillators (LO).
3.2 FPGA VI:
The FPGA VI contains the entire algorithm
required for DRFM mode of operation and Signal
http://www.ijettjournal.org
Page 45
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
processing that has to be implemented on FPGA board.
This VI is compiled by Lab VIEW FPGA to a bit-file
that can download on to the target (here VST) to
implement the algorithm in the hardware as seen in fig.
4.3. The VI is divided into three basic parts. They are:
Transmitting pulse p1,p2 and p3
Pulse detection and mode selection
Transponder reply with delay
Transmission of pulses p1,p2 and p3 at the signal
processing block is showed in below figure. The method
that is used for the transmission of pulses p1,p2 and p3
is as follows.
At the transmitting end we are using combination of
chirp signals and sampling blocks.
The uplink frequency or carrier frequency is used in this
transmission as 1.03GHz.Then the pulse width is taken
as 0.8 sec.The delay between p1 and p2 is constant and
it is taken as 2 secbut the delay between p1 and p3 is
varying and based on this variation we are selecting the
mode .
Figure 3.4: Transmitting the pulse loop of FPGA
VI
Figure 3.5 output loop of reply code
Figure 3.3: Transmission of pulses
The loop of FPGA that is used for transmission of pulse
is shown below. In this method
first we are selecting the source name, channel name and
method of generation, after that we are going to
calculate the pulse generation by using waveform
generation subVI.
Because of this generation the spacing and configuration
of pulses p1,p2 and p3 are defined. After that we are
going to design the script generation block with respect
top1, p2 and p3 configuration and defining the spacing
between them. After finally generation of pulse
transmission is completed.
ISSN: 2231-5381
The data of pulse transmitting p1,p2 and p3at
RF in it analyzes. Store in the data at DRFM FPGA and
the mode selection .
4. Results And Conclusion
This chapter discusses about Result and Conclusion
, short comes in the procedure , limitations of the
methods used for testing .It presents the results and
analysis of various scenarios designed compiled and
were loaded onto the target for verification.
4.1 Results :
In this project first we are transmitting the pulses
p1,p2 and p3. The pulse width of pulse is always fixed
and it is 0.8 sec and pulse spacing between p1 and p2
is 2 sec.the uplink frequency is 1.03GHz, The pulse
spacing between the p1 and p3 is varying based on this
http://www.ijettjournal.org
Page 46
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
we are selecting the mode. The pulse spacing between
p1 and p3 is 3 sec that is mode1that is show in Figure
5.3 and spacing is 5 sec that is mode 2 it is shown in
Figure 5.4. the pulse spacing is 8
Figure 4.3: Mode2 delay is 5 sec
Figure 4.1 : Radar Transponder Response GUI
The above fig. show the total radar transponder
response. In this we are generating the different target
delays and different mode selection. The different
Channel shows at the different delays and different
mode selections. In this modes are using the military
application and height.
Figure 4.4: Mode 3/A delay is 8 sec
Figure 4.2:Mode1 delay is 3 sec
Figure 4.5: Mode C delay is 21 sec
ISSN: 2231-5381
http://www.ijettjournal.org
Page 47
International Journal of Engineering Trends and Technology (IJETT) – Volume 25 Number 1- July 2015
4.2 Conclusion:
The project is the generation of pulse p1
and p2,p3 by the transponder , and the spacing of p1 and
p3 we generating the modes, we are play back the signal
by transponder
and calculated
multiple target
generating the delays and calculate the range of the
target.
5.References
[1].Zongbo Wang Meiguo Gao Yunjie Li Haiqing Jiang Sunguo Ying
“The Hardware Platform Design for DRFM System” ICSP2008
Proceedings IEEE
[2].M. I. Skolnik, Introduction to Radar Systems, Third Edition, The
McGraw-Hill Companies, Inc, 2001.
[3]."Digital RF Memories", Journal of Electronic Defense Supplement,
pp. 19-20, January 1994.
[4].Mark A.Richards, “Fundamentals of Radar Signal Processing “
McGraw-Hill Publications.
[5]. Michael C.Stevens. “Secondary Surveillance Radar”, Artech
House Publications
Figure 4.6: Mode D delay 25 sec
Figure 4.7: The delay generation of multiple targets
Figure 4.8: The comparing of transmitting
signal and receiving signal
ISSN: 2231-5381
http://www.ijettjournal.org
Page 48