International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 4 - June 2015
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PG Student [VLSI], Dept. of ECE, Sri Satya Sai College of Engineering
Bhopal, India
Abstract
— Low power design has become one of the primary focuses in digital VLSI circuits, especially in clocked devices like microprocessor and portable devices. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 4 transistors (4-T) XOR and XNOR gates. The other applies Gate- Diffusion-Input (GDI) technique to full adders.
Simulations are performed by using Cadence Virtuoso based on 65nm CMOS technology. In comparison with Static
Energy Recovery Full (SERF) adder cell module, the proposed four full adder cells demonstrate their advantages, including lower power consumption, smaller area, and higher speed. Compared to existing GDI technique with buffer restoration circuits, hybrid GDI implementation provides full swing output voltage in all digital circuits. Also it shows less power and less delay with about 60% area increase as compared to basic GDI.
Keywords — GDI, Full Adder, Pass transistor logic, tri-state inverters , Low power
I. Introduction
It is time we explore the well-engineered deep submicron
CMOS technologies to address the challenging criteria of these emerging low-power and high-speed communication digital signal processing chips. The performance of many applications as digital signal processing depends upon the performance of the arithmetic circuits to execute complex algorithms such as convolution, correlation, and digital filtering. Fast arithmetic computation cells including adders and multipliers are the most frequently and widely used circuits in very-large-scale integration (VLSI) systems. The semiconductor industry has witnessed an explosive growth of integration of sophisticated multimedia-based applications into mobile electronics gadgetry since the last decade.
However, the critical concern in this arena is to reduce the increase in power consumption beyond a certain range of operating frequency. Moreover, with the explosive growth, the demand, and the popularity of portable electronic products, the designers are driven to strive for smaller silicon area, higher speed, longer battery life, and enhanced reliability. The
XOR-XNOR circuits are basic building blocks in various circuits especially arithmetic circuits (adders & multipliers), compressors, comparators, parity checkers, code converters, error-detecting or error-correcting codes and phase detector.
To reduce the power consumption different logic design techniques like CMOS complementary logic, Pseudo nMOS,
Dynamic CMOS, Clocked CMOS logic (C2MOS), CMOS
Domino logic, Cascade voltage switch logic (CVSL),
Modified Domino logic, Pass Transistor Logic (PTL) have been proposed [2-4]. Although Static CMOS Logic has been the most popular design approach for the past three decades, many attempts have been made to propose a better alternative to achieve lower power dissipation, smaller area and better performance reported in [11-12]. Circuit designed with transmission gate (TG) solves the problem of low logic level swing by using PMOS as well as NMOS but this implementation needs true and complemented control signal and requires more area than pass transistor logic. Pseudo-
NMOS is simple and fast but reduces noise margins and increases power consumption. Pass-transistor logic is good for certain classes of circuits (MUX/adders). On the other hand,
PTL implementations of logic gates such as NANDs and
NORs were found to be slower and consume more power than
CMOS implementations mainly because of the reduced output swings due to the threshold drop across a single-channel pass transistor.
II. RELATED WORK
The main contribution of this paper presents the design of modified primitive cells and five different topologies for full adders at circuit level implemented based on the GDI technique. The modified GDI primitive cells are constructed and its significant variation between CMOS and conventional
GDI are compared. Though GDI technique offers low power, less transistor count and high speed, the major challenges occurs in the fabrication process. The GDI technique requires twin-well CMOS or Silicon on Insulator (SOI) process to realize a chip which increases the complexity as well as the cost of fabrication.
A. Conventional 28T CMOS Full Adder Circuit
The conventional CMOS adder cell using 28 transistors based on standard CMOS topology. Due to high number of transistors, its power consumption is high. Large PMOS transistor in pull up network result in high input capacitances, which cause high delay and dynamic power. One of the most
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 4 - June 2015 significant advantages of this full adder was ts high noise margins and thus reliable operation at low voltages.
B.Gate Diffusion Input (GDI)
The basic primitive of GDI cell consists of nMOS and pMOS as shown in Fig 2. A basic GDI cell contains four terminals – G (common gate input of nMOS and pMOS transistors), P (the outer diffusion node of pMOS transistor),
N (the outer diffusion node of nMOS transistor), and D
(common diffusion node of both transistors) [8]. Table 1 show how a simple change of the input configuration of the simple
GDI cell corresponds to different Boolean functions.
Referring to Table1 most of the functions are realized using the function F1 and F2 since they are possible to realize using
CMOS p-well process.
TABLE 1.
LOGIC FACTION IMPLEMENTATION WITH GDI
TECHNIQUE
N P G Out Function
0 B A F1
.B
B 1 A F2
1
B
C
0
B
0
B
1
A
A
A
A
+B
A+B
AB
B+AC
OR
AND
MUX
NOT
TABLE 2.
LOGIC FUNCTION IMPLEMENTED WITH MGDI
TECHNIQUE
N P G Out Function
A
B
B
A
B
A
A+B
AB
OR
AND
B
0
A
1
C
A
A+CB MUX
NOT
G
P
D
N
Fig 1. Symbol of GDI cell
The GDI approach allows implementation of a wide range of complex logic functions using only two transistors This method is suitable for design of fast, low power circuits, reduced number of transistors while allowing simple topdown design. Gate-Diffusion-Input (GDI) design technique is an efficient alternative for the logic design in standard CMOS and SOI technologies [9],[10]. A basic GDI cell contains four terminals – G node (the common gate input of the NMOS and
PMOS transistors), P node (the outer diffusion node of the
PMOS transistor), N node (the outer diffusion node of the
NMOS transistor), D node (the common diffusion of both transistors). P, N and D may be used as either input or output nodes, depending on the circuit structure shown in Fig.1 Bulks of both NMOS and PMOS are connected to N or P
(respectively), so it can be arbitrarily biased in contrast with
CMOS inverter. It must be remarked, that not all the functions are possible in standard p-well CMOS process, but can be successfully implemented in twin-well CMOS or SO1 technologies. Multiple-input gates can be implemented by combining several GDI cells [11]
C .
Modified Gate Diffusion Input (GDI)
In the basic structure of GDI cell the N diffusion node and
P diffusion node act as a source and sink. Thereby there in no direct impedance path between VDD and GND as in the case of CMOS logic. Therefore this structure will considerably reduce the effect of dynamic short circuit power dissipation.
The other advantage of this scheme, it requires lesser area to realize the logic functionality. While considering the basic structure of AND and OR gate of GDI the P diffusion (AND gate) is connected to GND and the N diffusion (OR gate) is connected to VDD (In Table 1). This type of logic structure produces a slight degradation at the output voltage. To obtain the full swing voltage the proposed primitive cells has a modification in existing GDI technique. In the proposed cells of AND gate the P diffusion and Gate terminal are connected to „A‟ input. Similarly for OR gate the N diffusion and gate terminal are connected to „B‟ input. This modification produces less power consumption and high VOH, while apparently maintaining the same reduced transistor count. Fig
3 shows the construction of modified basic gates of AND, OR,
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 4 - June 2015
NAND, NOR, XOR, XNOR and MUX. The modified GDI primitive logic function (MGDI) is shown in Table 2.
D. Static Energy Recovery Full Adder (SERF)
As an initial step toward designing low power arithmetic circuit modules, we designed a Static Energy Recovery Full adder (SERF) cell. The cell uses only 10 transistors and it does not need inverted inputs. The design was inspired by the
XNOR gate full adder design [10]. In non-energy recovery design the charge applied to the load capacitance during logic level high is drained to ground during the logic level low. It should be noted that the new SERF adder has no direct path to the ground. The elimination of a path to the ground reduces power consumption, removing the Psc variable (product of Isc and voltage) from the total power equation. The charge stored at the load capacitance is reapplied to the control gates [11].
The combination of not having a direct path to ground and the re-application of the load charge to the control gate makes the energy recovering full adder an energy efficient design. To the best of our knowledge this new design has the lowest transistor count for the complete realization of a full adder.
A
Cout
Cin
B
Sum
A
B
Cin
Cin
A
Carry
Sum
Fig.2. Schematic of SERF Full Adder
III. Proposed Methodology
In this section we introduce a novel Low-Power Full Adder, which has good characteristic in term of speed and power. The circuit of 11T adder is a one-bit full adder core has three inputs (A, B, C in
) and two outputs (Sum S and Carry C out
).
The adder is made of three CMOS inverter. Input A is directly connected to first inverter & Input B is connected to parallel
PMOS network. The output of the first inverter generate compliment of C out and SUM Compliment is generated with the help of C out
which is feed to the second inverter, C in
is feed to the third inverter so as to generate the SUM.
Fig.3.Schematic of Proposed 11T Full Adder
IV. Results and Simulation
The power consumption of proposed circuit is remarkably reduced than the other Approaches at 180nm technology with supply voltage ranging from 1v at 27
0
C. In order to prove that which design consume less power and have high performance,
Simulations are carried out for power, delay, power-delay product at varying supply voltages, temperature and operating frequency. To establish an impartial simulation circumstance, each circuit have been tested on the same input patterns which covers possible combination of input.
TABLE. III. Comparison of Power, Delay, PDP of 28T,
SERF, GDI, & 11T adder with proposed circuit
Parameters Average
Power(us)
Delay
(ns)
PDP
(fs)
28T
SERF
GDI
Proposed 11T
8 Bit full
Adder from 11T
16 Bit full
Adder from 11T
43.6
8.34
7.26
3.21
42.23
86.83
3.155
2.548
2.136
.03929
6.028
2.024
137.55
21.250
15.507
.12612
254.56
175.39
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 4 - June 2015
Fig 4: Layout diagram of Proposed 11T Adder
Application of Adder Circuit
Adder Circuit circuits are basically used to implement wide
Arithmetic circuits. Adder are used in Dynamic RAMs, Static
RAMs, high speed processors and other high speed circuits and GDI reduces the area of the Arithmetic circuits. Adder circuits are thus used which reduce sub threshold leakage current in standby mode and improve noise immunity for wide
OR gates.
V. Conclusion
A new family of self-reset logic (SRL) cells implemented with modified GDI technique has been presented. The performance of this proposed primitive cells presents 60-80% of power reduction when compare to other logic families with slight increase in transistor count. With this proposed primitive cell a new low-power, high-speed Delay element has been implemented. Area is reduces by GDI Technique to enhance the performance.
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