International Journal of Engineering Trends and Technology (IJETT) – Volume 27 Number 3 - September 2015
Design of a New Power Efficient Explicit-Pulsed Dual Edge
Triggered Sense-Amplifier Flip-Flop
P.Manikanta#1, R.Ramana Reddy*2,
1
Student, 2Professor, ECE Department, Jntuk, India
Abstract— In this paper a new dual-edge triggered
sense-amplifier
flip-flop
(NEWDET-SAFF)
is
proposed. The proposed flip-flop presets its storage
nodes to a medium voltage level between VDD and
VSS just before input capturing. By embedding dualedge triggering mechanism and conditional precharging in the new symmetric latch, the NEWDETSAFF is capable of achieving low power dissipation
and delay. The presetting operation allows the
proposed flip-flop to be faster and more clock-skew
tolerant than conventional flip-flops. Simulations are
carried out using a mentor graphics tools of 130-nm
CMOS process technology and results indicate that
NEWDET-SAFF results has 22% improvement on
clock-skew tolerance, 20% decrease of data-to-output
delay, 22.3% reduction of power-delay product, as
compared to DET-SAFF.
Keywords — Dual-edge triggering, clock-skew
tolerance, Conditional precharging.
I. INTRODUCTION
Speed, power consumption, robustness,
clock-skew tolerance, and layout area are the most
important parameters in the design of highperformance semiconductor devices. Since flip-flops
are essential elements for designing these devices,
they have a critical influence on determining these
parameters. As frequency increases, pulse-based flipflops are used popularly to compare with conventional
master-slave flip-flops [1]. The basic idea is to
construct a short pulse around the triggering edge of
the clock. This pulse acts as the clock input to a latch,
sampling the input data only in a short window.
Race conditions are thus avoided by keeping
the transparent period of the latch very short. This
sampling window is usually wide enough for the input
data to propagate to the output Q. So, the setup time
can be negative. Since input data can arrive at the flipflop even after the triggering edge of the clock, this
feature is attractive in that some timing can be
borrowed from the previous cycle [2]. Soft clock edge
property obtained by the pulse-based operation also
provides a large clock-skew tolerance while
maintaining low data-to-output latency. If the
variation on this latency is smaller than the variation
of the clock edge, clock skew is said to be absorbed
[3]. The highest clock-skew tolerance can be obtained
if data-to-output delay is flat in the region of expected
clock arrival. Conventional methods to absorb clock
skew usually have large synchronization overhead,
reduce design flexibility, and require the generation
and distribution of overlapped multiple clock phases.
ISSN: 2231-5381
Many dual edge triggered flip-flops have been
discussed [3]-[10].
II. REVIEW OF EXISTING DUAL- EDGE
TRIGGERED FLIP-FLOPS
A. Static Output-Controlled Discharge FlipFlop
By using static dual edge triggered flip-flop,
static output controlled discharge flip-flop
(SCDFF) is designed and the schematic diagram
is shown in Fig.1. The pulse generator and the
static latch can involve an explicit pulse
generator and a latch that captures the pulse
signal. And the static latch consists of two static
stages. In the first stage, input D is used to drive
the pre-charge transistor so that node X follows
D during the sampling period. The conditional
discharging technique is implemented by
inserting a QB controlled NMOS in the
discharge path.
(a)
(b)
Fig.1. Static output-controlled discharge flip-flop (SCDFF): (a)
dual pulse generator and (b) static latch.
This helps to reduce the power dissipation,
of the input activity. The major advantage of SCDFF
is low power consumption and soft edge property.
Drawback of SCDFF is delay.
B. Dual Edge-Triggered Static-Pulsed Flip-Flop
DSPFF consists of pulse generator and static latch
stages. The pulse generator and the static latch of dual
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International Journal of Engineering Trends and Technology (IJETT) – Volume 27 Number 3 - September 2015
edge static pulsed flip-flop is shown in Fig.2.The
pulse generator consists of four inverters which
generate delayed and inverted clock signals, CLK2
and CLK3, along with two NMOS transistors for
pulse generation. In latching stage, once the PULS
signal is generated, both pass transistors are turned
ON to capture the inputs data so that either SB or RB
will be discharged.
The adaptive clock inverter chain will disable some
internal clocked transistors when the data activity is
low. The signal derived from node NC of the sensing
stage is used to implement adaptive clocking. If input
D is derived from output Q node NC will be pulled up
and the transistors pass transistors in the inverter chain
will turn on. Consequently, the desired inverted and
delayed signals, CLK3 and CLK4 will be produced so
that an arrow transparent window is created on the
rising and falling edges of the clock. Either SB or RB
will be discharged during this transparent period,
changing the output state in the latching stage.
(a)
(a) Adaptive inverter chain
(b)
Fig.2. Dual edge-triggered static pulsed Flip-Flop (DSPFF): (a) dual
pulse generator, and (b) static latch
A smaller delay can be obtained since DB and D
are directly fed to the nodes, SB and RB, respectively.
The PMOS transistors, together with two weak NMOS
transistors, effectively avoid the floating of nodes SB
and RB when the flip-flop is opaque, thereby
providing a fully static operation. The explicit pulse
generator is simple and suitable for dual-edge
triggering.
The static feature of DSPFF eliminates
unnecessary transitions. Symmetrical output delays
can be obtained by carefully sizing the transistors
aspect ratios. On top of that, DSPFF suffers from high
leakage current. This is caused by a high-voltage drop
across either of the pass transistor in the pull down
path, when they are off.
C. Adaptive Clocking Dual Edge-Triggered SenseAmplifier Flip-Flop
ACSAFF is an implicit dual edge triggered sense
amplifier flip-flop. It consists of three stages: The
adaptive clock inverting stage, the front end sensing
stage and the Nikolic’s [11] stage is shown in Fig.3.
ISSN: 2231-5381
Front end sensing stage
Latch stage
(b) Sensing and latch stage
Fig.3. Adaptive clocking dual edge- triggered sense- amplifier FlipFlop (ACSAFF) ( a) Adaptive inverter chain (b) Sensing and latch
stage
Once the output is altered with reference to the
input then the node NC will be blocked through either
of the pull down transistors path. This flip-flop has
shown its superiority in terms of power consumption
at low switching activity.
D. Dual-Edge Triggered Sense-Amplifier Flip-Flop
The schematic diagram of the DET-SAFF is
shown in Fig.4 the dual edge triggered pulse generator
[12] produces a pulse signal synchronized at the rising
and falling clock edges. The pulse generator can be
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International Journal of Engineering Trends and Technology (IJETT) – Volume 27 Number 3 - September 2015
shared by multiple flip-flop circuits when a group of
flip-flops are located closely. For a sense amplifier
based flip- flop, in the evaluation phase, as soon as D
is low, SB will be set to high, and if D is high, RB will
be set to high.
III. PROPOSED DUAL EDGE TRIGGERED
SENSE AMPLIFIER FLIPFLOP
The schematic diagram of the NEWDETSAFF is shown in Fig.5 it consists of pulse generator
and sensing stages of DET-SAFF. In the latching stage
a new high speed and symmetrical latch is developed
to achieve low power and high speed.
(a) Dual pulse generator
Sensing
stage
node. This topology significantly speeds up the highto-low output transition because the output latch
immediately captures the input value once the PULS
signal is generated. On the other hand, the low-to-high
latency will also be improved. This is because the
output node will not only be charged by the pull-up
transistors, but also with the pull down pass transistors.
The advantage of DET-SAFF is high speed and low
power. But the unnecessary transitions especially at
low switching activities cause a lot of power to be
wasted.
Latch stage
(a) Dual pulse generator
(b) Sensing and latch stage
Fig.4. Dual edge-triggered sense-amplifier Flip-Flop (a)Dual
pulse generator (b) Sensing and latch stage
Therefore, the conditional pre-charging
technique is applied in the sensing stage of DETSAFF, to avoid redundant transitions at major
internal nodes. Two input controlled PMOS
transistors in the pull-up stage of sense amplifier are
embedded in the pre-charge paths of nodes SB and
RB, respectively. In this case, if D remains high for
n cycles, SB may only be discharged in the first
cycle. For the following cycles, SB will be floating
when PULS is low or fed to the low state DB when
PULS is high. As for RB, it only needs to be precharged in the first cycle and remains at its high
state for the remaining cycles.
Since the pre-charging activity is
conditionally controlled, the critical pull down path
of SB and RB is simplified, consisting of only one
signal transistor. This helps to reduce the
discharging time significantly. As such, the resulting
sensing stage possesses low-power and high-speed
features.
A fast symmetric latch is developed this new
latch [13] makes use of SB and RB to pull up the
output nodes. But the pull down path is modified. It
composes PULS -controlled NMOS pass transistor,
through which D (DB) is directly fed to the Q (QB)
ISSN: 2231-5381
(b) Latch stage
Fig.5. Proposed new Dual edge-triggered sense-amplifier FlipFlop (a) Dual pulse generator (b) Latch stage
Once the PULS is generated from pulse
generator then the sensing stage will generate the SB
and RB notice transistors Q1 and Q3 resemble the
series-connected complementary pair from the inverter
circuit. Both are controlled by the same input signal
(input SB), the upper transistor will turn OFF and the
lower transistor will turn ON when the input is “high”
(logic 1), and vice versa. The transistors Q2 and Q4 are
similarly controlled by the same input signal (input
RB), to the logic levels. The upper transistors of both
pairs (Q1 and Q2) have their source and drain terminals
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International Journal of Engineering Trends and Technology (IJETT) – Volume 27 Number 3 - September 2015
are parallel connected, while the lower transistors
(Q3 and Q4) are series-connected.
This arrangement results the output to go
“high” (logic 1) if either top transistor saturates, and
will go “low” (logic 0) only if both lower transistors
saturate. The design cross coupling results a latch
circuit as a result the data will be latched in the design.
IV.
SIMULATION
RESULTS
AND
PERFORMANCE COMPARISONS
All the flip-flops were designed using
Chartered Semiconductor Limited’s 0.13µm CMOS
process technology, at an operating temperature of
270C and a supply voltage of 1.8V, using MENTOR
GRAPHICS TOOLS. The performance of the
proposed flip-flop is evaluated and compared with
SCDFF, DSPFF, ACSAFF, and DETSAFF. The
design was optimized to 1.25 GHZ. Table I
summarize the performance metrics of the reviewed
flip-flops and proposed designs, at input switching
activity of α = 1. The proposed NEWDET-SAFF
achieved low CLK-to-Q delay among the flip-flops.
V. CONCLUSION
In this paper a new technique, conditional precharge,
is proposed. This technique is incorporated in the dual
edge triggered sense amplifier flip-flop and a new flipflop named NEW DET-SAFF is proposed to reduce
the delay and power dissipation in flip-flops. With a
data switching activity of 50%, the new flip-flop can
save upto 36% of the energy with the same speed as
that for the fastest pulsed flip-flops. While explicit
pulsed data close to output (ep-DCO) is suitable for
speed critical paths, NEWDET-SAFF is suitable for
both speed critical paths and speed-insensitive paths
for energy-efficiency. Moreover, the design has shown
its superiority in high switching activity with a
reduced delay of 73% respectively.
REFERENCES:
[1]
[2]
[3]
TABLE I COMPARISON RESULTS OF FLIPFLOPS
CLK-to-Q
delay(ps)
Min D-toQ delay
(ps)
Rise
time(ps)
Fall
time(ps)
MOCF(GH
Z)
# of
transistors
DSPFF
[9]
ACSAFF
[10]
DETSAFF
[12]
NEW
DETSAFF
619.80
886.7
598.5
192.36
37.877
620.40
572.9
803.1
197.36
178.19
746.7
218.89
111.02
30.720
800.7
111.02
50.452
49.751
1.43
0.83
1
1
24
39
22
22
103.33
97.981
1
29
*MOCF: Maximum operating clock frequency is the
highest frequency at which output can acquire 90% of
full swing
[4]
[5]
[6]
[7]
[8]
[9]
[10]
40
power(nw)
Designs
SCDFF
[8]
30
SCDFF
20
DSPFF
10
0
[11]
[12]
ACSAFF
DETSAFF
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NEWDET-SAFF
Fig. 5. Power dissipation of different flip-flops
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