International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 5 - Mar 2014
Synthesis of High Speed Full Adder
Ashwani Panjeta1
Abstract— Adders are the basic component in most of the
electronic devices used nowadays. An adder circuit is
characterized by various parameters such as power, delay and
area occupancy. This paper presents a adder which reduces
power consumption. All the adders are simulated by Mentor
Graphics. The technology used is 180 nm. Significant power
reduction is shown in the proposed adder as compared to other
adders being discussed.
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I. INTRODUCTION
In the past, the major concerns of the VLSI designers were
area, performance, cost and reliability. The recent trend shows
that power consumption is given extra weightage in
comparison to other parameters while designing any of the
digital circuit. Speed, power and utilization measure the
efficiency of the systems. Addition is one of the fundamental
arithmetic operations and is used extensively in many VLSI
systems. In addition to its main task, which is adding two
binary numbers, it is the core element of many useful complex
arithmetic circuits such as subtraction, multiplication,
division, address calculation, etc. [1], [2]. In most of these
systems, the adder is part of the critical path that determines
the overall performance of the system. That is why enhancing
the performance of the 1-bit full-adder cell is considered a
significant goal. The performance of the adder circuit is
greatly influenced by delay, sizes of transistors used, parasitic
capacitance. Every circuit contribute towards three types of
power dissipation. These are
1. Short Circuit Power: Due to direct path between
supply and ground.
2. Switching Power: Due to charging and discharging
of circuit capacitance.
3. Leakage Power: Due to flow of current when
transistor is in the off state.
The 2nd component contributes towards maximum power
dissipation. This paper is divided into 6 sections. Section I
introduces the topic. Section II gives the brief idea of adders
being proposed so far along with their advantages and
disadvantages. Some adders comprising of less transistors are
discussed in Section III. Section IV describes the hybrid adder
proposed. Results are shown in Section V and the paper is
concluded in Section VI.
II. ADDERS
An adder is an electronics device which performs the
addition operation of any two numbers. Adder circuit was
primarily based upon static CMOS logic The circuit diagram
of static CMOS adder circuit is shown in Fig. 1.1.
ISSN: 2231-5381
Fig. 1.1 : Static CMOS Adder Circuit
Certain advantages of adder in [3] are reliable operation even
at low voltages and arbitrary transistor sizing. Since it used
same number of NMOS and PMOS transistors, thereby
increasing the area occupancy. So to avoid these problems,
domino logic was proposed [4]. Dynamic logic circuit need
only single clocked precharge devices and implement the
logic using either the pull-up network (PUN) and pull down
network (PDN). However this results in the problem of charge
sharing. So to avoid this problem, domino logic circuit was
proposed. The dynamic static pair together is called Domino
gate because precharge resembles setting up a chain of
dominos, each triggering the next [5]. A single clock can be
used to precharge and evaluate all the logic gates within the
chain. The circuit diagram of domino logic full adder circuit is
shown in Fig. 1.2. The domino circuits are energy efficient
and fast logic but these circuits use global clock. The clock
distribution network dissipates 20 to 45% of overall
consuming power. Moreover in dynamic domino logic the
precharge phase occurs simultaneously by synchronizing all
the gates with the same clock signal. Thus causing precharge
phase to be slower [6].
Fig. 1.2: Domino Logic Full Adder
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 5 - Mar 2014
An alternative to CMOS gates is pass transistor logic. This
logic family use same MOS transistors that is either NMOS or
PMOS. It leads to reduction in the number of transistors as
compared to CMOS family. The reduced number of devices
has the additional advantage of lower capacitance [7]. Pass
transistor based designs consume very little power and area,
but suffer from poor performance and reliability when an
NMOS and PMOS is used alone act as imperfect switch. So
for high performance CPL (Complementary Pass Transistor
Logic) was proposed. The CPL adder circuit is as shown
III. LOW TRANSISTOR COUNT FULL ADDERS
A. 10T Transistor Adder
The 10 T falls under the category of the pass transistor type
logic style. It uses both the NMOS and PMOS transistors. The
10T adder comes first while searching for an adder with the
lowest number of transistors. 10 T in figure 1.6 [5, 20] use
more than one logic style for their implementation and they
are called Hybrid logic design style.
in Fig 1.3.
Fig. 1.3: CPL Adder circuit
CPL is not an appropriate choice for low power due to its
high switching activity of intermediate nodes, high transistor
count and overloading of its inputs [8]. The most widely-used
solution to deal with the voltage-drop problem is the use of
transmission gates. It builds on the complementary properties
of NMOS and PMOS transistors: NMOS devices pass a strong
0 but a weak 1, while PMOS transistors pass a strong 1 but a
weak 0. The ideal approach is to use an NMOS to pull-down
and a PMOS to pull-up. The transmission gate adder is shown
in Fig. 1.4. The main disadvantage of transmission gate logic
is that it requires double the number of transistors of the
standard pass-transistor logic or more to implement the same
circuit.
Fig. 1.6: 10 T adder circuit
This adder does not perform well upon analysis with the given
input stimulus. The carry out signal ( Cout) produces a strong1 which is a full supply voltage (VDD) or strong-‘0’ which is
0V only in some particular cases whereas the rest outputs
weak-‘0’ and weakest-‘1’.
B. 14 T Adder Circuit
The next low count full adder circuit is 14 transistor full
adder. It needs only 14 MOSFETs for its realization while
having full voltage-swing in all nodes. 14 T has advantage of
produce XOR/XNOR function at the same time. Thus it
eliminates the use of inverter for producing XNOR function
[9].
Fig. 1.5: Transmission Gate Adder
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Fig. 1.7: 14 T Adder Circuit
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 5 - Mar 2014
The hybrid full adder can be decomposed in three modules as
in [10]. Certain modifications have been made in module 1 of
the circuit. Next section depicts the changes being done.
IV. PROPOSED HYBRID ADDER
The module 1 as described in [10] is shown in Fig. 1.8.
However, this circuit suffers from the same threshold voltage
drop problem as any other pass transistor logic circuits. The
worst-case delay happens at the transition from 01 to 00 for
inputs AB.
Fig. 1.10: Module 2 for adder circuit
There are several choices for Module 2. Since its logic
expression is similar to that of Module 1, the cross back 6transistor can also be used [9], [11].However, it suffers from
insufficient driving power due to the pass transistors.
Therefore we use a similar circuit as that of TFA and 14 T, but
fully exploit the available XOR and XNOR outputs from
Module 1 to allow only a single inverter to be attached at the
last stage.
Fig. 1.8: Module 1 of adder circuit
Due to the unsatisfactory performance at low-supply voltage,
the circuit of Fig. 1.8 is modified to Fig.1.9.
Fig. 1.11: Module 3 for adder circuit
The module 3 circuit is based on complementary CMOS logic
style [12]. Complete circuit of adder circuit is given in Fig.
1.12.
Fig. 1.9: Modified Module 1 circuit
Two series PMOS transistors are added to solve the worstcase delay problem of transition from 01 to 00 for AB. Two
transistors in off state consume less power as compared to a
single on transistor [kroy]. With the application of the
concept, significant amount of power has been reduced. the
circuit diagram of remaining two modules is shown in Fig.
1.10 and 1.11 respectively. The results and circuit diagrams of
each adder described above is shown in the next section.
Fig. 1.12: Modified Hybrid full adder
V. RESULTS
All the adders are designed and simulated on Design Architect
by Mentor Graphics in 180 nm technology. Here technology
used means length of the channel in MOS transistors. The
threshold voltages of the PMOS and NMOS transistor are
around 0.4 and 0.8 V, respectively. Fig. 1.13 and 1.14 show
the circuit diagram and output waveforms of CMOS adder.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 5 - Mar 2014
TABLE I
COMPARISON BETWEEN DIFFERENT ADDERS
Adder
Name
Static
CMOS
Domino
CPL
TGA
10 T
14 T
HYBRID
Fig. 1.13: CMOS Full Adder
Power
Parameters
Delay
PDP
10.890
102.679
1118.174
10.720
17.409
7.712
7.241
2.901
5.468
146.151
118.6767
133.114
163.376
215.821
109.919
1566.738
2066.042
1026.575
1183.006
626.096
598.037
It is clear that CPL adder consumes highest power, because of
its dual-rail structure and the substantial number of internal
nodes. The additional inverters used to generate the
complement inputs have also increased the power
consumption. PDP of Hybrid adder is minimum as compared
to all other transistor.
Fig. 1.14: Output waveforms depicting delay
The modified hybrid adder is shown in Fig. 1.15.
VI. CONCLUSIONS
Adder is used extensively in many VLSI systems such as
microprocessors, and application specific DSP architecture,
addresses calculation etc. The quantitative overview of
performance of the full adder cell has been presented in terms
of power consumption, speed, power-delay product (PDP).
Hybrid full adder has 22%, 86% less power-delay product
compared to TGA and static full adder respectively. Hybrid
full adder generate the XOR and XNOR functions
simultaneously and a good drivability carry out is generated
by a complementary CMOS style circuit. In addition, laststage inverter in hybrid full adder de-couples the output and
input to improve the driving capability.
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Fig. 1.15: Modified Hybrid Full Adder
Simulation results show that the hybrid design consumes less
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ranged from 0 and VDD – Vt and not between 0 and VDD
as seen in the TGA and CMOS adders. The Power Delay
Product (PDP) is a quantitative measure of the efficiency and
a compromise between power dissipation and speed.
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