International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 8- Feb 2014
Design, Implementation and Performance Analysis
of Full Adder for Low power Dissipation
Khushbu Maheshwari1, Prof. Mukesh Tiwari2, Prof. Jai Karan Singh3
1
PG Student, Department of electronics & Communication, Sri Satya Sai Institute of Science & Technology, RGPV University,
Bhopal, MP, India
2,3
Department of electronics & Communication, Sri Satya Sai Institute of Science & Technology, RGPV University, Bhopal,
MP, India
Abstract— This paper will represent the design and
implementation of 1bit full adder, using four different CMOS
topology as static or conventional CMOS, Gate diffusion input
(GDI), low power feed through logic (LP-FTL) and High speed
feed through logic(HS-FTL) which is a dynamic technology.
Adder is the basic building for all arithmetic operations like
addition, subtraction. We have implemented the 16 bit ripple
carry adder in BPTM 45nm CMOS technology in LT spice IV.
family called feed through logic (FTL) was
proposed in [5], where FTL concept is extended for
the design of low power and high performance
arithmetic circuits. This logic works on domino
concept along with the important feature that output
is partially evaluated before all the inputs are valid.
Keywords— CMOS, GDI, FTL, BPTM.
II. POWER DISSIPATION
I. INTRODUCTION
Power consumption and it’s minimization is one
of the primary concerns in today VLSI design
methodologies because of two main reasons one is
the long battery operating life requirement of
mobile and portable devices and second is due to
increasing number of transistors on a single chip
leads to high power dissipation and it can lead to
reliability and IC packaging problems.
High performance dynamic circuits due to their
compactness and higher speed as compared to static
CMOS [1, 2] are increasingly being used, mainly in
wide fan in circuits. However the major drawback
with this logic is its excessive power dissipation
due to the switching activity and clock, also it
suffers from charge leakage, charge sharing and
requirement of additional output inverter during
cascading of logic blocks. As we know Full adders
are important components in applications such as
digital signal processors (DSP) architectures and
microprocessors. Apart from the basic addition
adders also used in performing useful operations
such as subtraction, multiplication, division,
address calculation, etc.
To improve the performance of dynamic logic
circuit in terms of speed and power, a new logic
ISSN: 2231-5381
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Ideally, in CMOS circuits the output node is
either connected to VDD or GND. Due to absence
of direct path between VDD and GND CMOS
circuits dissipates zero static power. But practically
MOS transistor never acts as perfect switch. There
is always leakage current which leads to static
power dissipation. The various sources of power
dissipation in CMOS are Static Power Dissipation
and Dynamic power Dissipation
The total power in a static CMOS is given by
P total = P static + P switching + P short-circuit
A. Static Power Dissipation
It is the power dissipated when there is no
switching activity within the circuit. Ideally, CMOS
circuit dissipates no static power, since there is no
direct path from VDD to GND. But practically
MOS transistor never acts as perfect switch. There
is always leakage current which flows when the
input(s) to and the outputs of a gate are not
changing, leads to static power dissipation. But as
the supply voltage is being scaled down to reduce
dynamic power, low VTH transistors are used to
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 8- Feb 2014
maintain performance. Reduction in VTH of
transistor leads to greater leakage current. The static
power dissipation is given by
P Static = VDD * I leakage
B. Dynamic Power Dissipation
It is the dominant portion of power dissipation
which occurs due to transition at gate outputs. It
consist two components of power dissipation
Switching Power dissipation (P switching) As the
nodes in a digital CMOS circuit transition back and
forth between the two logic levels, the capacitance
associated with the nodes gets charged and
discharged. The power dissipated during this
process is called as switching power and it is the
major source of power dissipation in CMOS circuits.
For a static CMOS circuit with N switching nodes
operating at clock frequency f clk, the switching
power is given by
P switching = ∑ αi Ci Vdd Vswing Fclk
Where αi is the switching activity at node i
VDD is the supply voltage
V swing Voltage swing at node i
αi Ci is the effective switch capacitance per
cycle at node i.
Another is short circuit power dissipation. This is
due to short circuit current (ISC) which flows
directly from VDD to GND when both PMOS and
NMOS transistor are on. When the input to the gate
stable at either logic level only PMOS or NMOS
transistors are ON. Hence no short circuit current
flows. But when output of a gate switches in
response to change in inputs, both PMOS and
NMOS transistors are conducts simultaneously for
a short interval of time. This interval of time
depends upon rise or fall time of input signal and
causes short circuit power dissipation.
Fig. 1 Schematic of Static CMOS full adder.
Fig. 2 Simulation result of Static CMOS full adder.
B. Gate Diffusion Input(GDI
A new low power design technique that solves
most of the problems known as Gate-DiffusionInput (GDI) is proposed. This technique allows
reducing power consumption, propagation delay,
and area of digital circuits. A basic GDI cell
contains four terminals – G (common gate input of
nMOS and pMOS transistors), P (the outer
diffusion node of pMOS transistor), N (the outer
diffusion node of nMOS transistor), and D
(common diffusion node of both transistors). The
implementation shows in figure 3 and figure 4.
PShort-circuit = VDD * ISC
III. IMPLEMENTATION OF 1BIT FULL ADDER
A. Static CMOS
The static CMOS is simulated in spice with input
frequency of 12.5MHz, 25MHz and 50MHz as
shown in figure 1 and figure 2.
ISSN: 2231-5381
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Fig. 3 Schematic of Static GDI full adder.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 8- Feb 2014
Fig. 4 Simulation result of GDI CMOS full adder.
Fig. 7 Schematic of Static LP-FTL full adder.
C. Feed through Logic(FTL)
This logic contains two types of implementation
methodology first is for high speed as shown in
figure 5 and figure 6 which uses less numbered
transistor compared to low power implementation
as shown in figure 7 and figure 8, uses a clock
signal of 232.5MHz.
D. Performance Analysis
As shown in table 1, all types of adder are
implemented and we got the minimum average
power dissipation and energy delay product in low
power feed through logic style compared to all
other logic.
Fig. 8 Simulation result of LP-FTL full adder.
TABLE I
PERFORMANCE ANALYSIS OF 1 BIT FULL ADDER
Logic
Style
Static
CMOS
GDI
Power
Dissipation (uW)
8.3168
Energy Delay
Product (fJ)
831.68
No. of
Transistor
28
6.3007
630.07
10
HS-FTL
9.0353
903.53
18
LP-FTL
2.3899
238.99
28
IV. CONCLUSIONS
Fig. 5 Schematic of Static HS-FTL full adder.
This paper present four logic style for 1bit full
adder implementation. After performance analysis
we can come to results than we got the minimum
power dissipation of 2.3899uW in the low power
feed through (LP-FTL) architecture since it uses
more number of transistors of 28 compared to high
speed feed through logic (HS-FTL) and gate
diffusion input (GDI) which are using lower
number of transistor 18 and 10 respectively.
Fig. 6 Simulation result of Static HS-FTL full adder.
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) – Volume 8 Number 8- Feb 2014
ACKNOWLEDGMENT
I want to specially thanks to my guide Prof. Jay
karan singh who encourage me throughout my work
and it’s completion.
[4]
[5]
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