International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 2- Dec 2013
Enhanced Multi Testability Implementation in ASIC Chips for
Improving High Speed
Rajkumar Lankapalli1, K.V.B Chandra Shekhar Rao2, P.Lakshmi Sarojini 3
1
M.Tech (VLSI SYSTEM DESIGN) (pursuing),Swarnandra college Of Engineering and Technology (SCET),Narsapuram, Andhra
Pradesh, India.
2
Associate professor, Department of ECE,Swarnandra college Of Engineering and Technology (SCET),Narsapuram, Andhra
Pradesh, India.
3
Professor, Department Of ECE,Swarnandra college Of Engineering and Technology (SCET),Narsapuram, Andhra Pradesh,
India.
ABSTRACT: The main objective of this paper is
to design an ASIC and testing by different testable
techniques. It contains two vital parts; one section
is testable by using of controllability testing
technique and the other is tested by logic BIST.
Implementation of an innovative and interactive
BIST design is presented with more advanced
algorithms. This BIST Technique is based on
STUMPS (Self-Test USING MISR and Parallel
Shift Registers) architecture which uses an on-chip
circuitry to generate the test patterns and analyze
the responses. This requires only two external
operations to initialize the built-in tests and to
check the test results. Power optimization, latency
is reduced by using these novel techniques.
Keywords
Controllability, PRPG, STUMPS, Logic-BIST,
Speed Testing, parallel scan test, ATPG, MISR,
ASIC Design, ASIC testing, Gates testability,
clocks reduced. Control logic.
INTRODUCTION
With recent advances in semiconductor
manufacturing technology, the production and
usage of very-large-scale integration (VLSI)
circuits has run into a variety of testing challenges
during wafer probe, wafer sort, pre-ship screening,
incoming test of chips and boards, test of
assembled
boards,
system test, periodic
maintenance, repair test, etc. Traditional test
techniques that use automatic test pattern
generation (ATPG) software to target single faults
for digital circuit testing have become quite
expensive and can no longer provide sufficiently
high fault coverage for deep submicron or
nanometer designs from the chip level to the board
and system levels. As circuits become larger their
testing complexity raises exponentially the demand
for efficient
testing techniques increases
and every testing technique needs a basis to
analyze the circuits. The testability of a circuit is
defined by the controllability and observability.
Controllability of a digital circuit is defined as the
difficulty of setting a particular logic signal to 0 are
1 observability for a digital circuit is defined as the
difficulty of observing the state of a logic signal.
The sequential controllability gives a rough
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measure of the number of times various flip-flops
must be clocked to control a signal and the
sequential obsertvability measure the no of times
various flip-flop must be clocked to observe a
signal generally these sequential measures
characterize the test length.
One approach to alleviate these testing
problems is to incorporate built-in self test (BIST)
features into a digital circuit at the design stage
with logic BIST. Another feature of BIST, at-speed
testing, as it is called, has become essential for
submicron chips, in which path delays and other
faults have become crucial to their operation. Most
large application-specific integrated circuits
(ASICs) use scan as a fundamental design for test
(DFT) methodology. The addition of BIST features
to electronics hardware frequently doesn’t
significantly increase a product’s size, cost, and
production time as was the case in the past.
Thus Logic BIST in system-on-a-chip
(SoC) ASIC design has a major role. It provides
fault coverage of 90 to 95 percent or more, using
only a clock and a “test-mode” signal.
LOGIC BIST
Logic BIST Architecture
The Logic-BIST chooses to implement a
STUMPS-based architecture, as it is easy to
integrate with scan/ATPG and is the architecture
widely used in the industry. We recommend using
one PRPG–MISR pair for each clock domain,
whenever possible, as the resulting BIST
architecture is easier to debug. In addition, the use
of one PRPG–MISR pair for each clock domain
can eliminate the need for additional design efforts
for managing clock skews between interactive
clock domains, even when they operate at the same
frequency. If it is required to use a single PRPG–
MISR pair to test multiple clock domains, these
clock domains should be placed with in physical
proximity in order to simplify physical
implementation. An example logic BIST system
based on the STUMPS architecture for testing the
design given is shown in Figure.1.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 2- Dec 2013
Fig.1: A typical LOGIC-BIST System
Fig.3: STUMPS-Based Architecture
Here the Logic-BIST controller for
coordinating the overall BIST operation. The logic
BIST controller consists of a test controller and a
clock gating block. The test controller initiates the
BIST operation upon receiving a Start signal,
issues a Finish signal once the BIST operation is
complete, and reports the pass/fail status of the test
through the Result bus.
At the end of the BIST session, the final
signature is so highly compacted that very little
information can be extracted from it for diagnostic
purposes unless the number of bits in error is very
small. In general, there is no bound on the
multiplicity of errors during BIST because a single
defect can cause a large number of vectors to
produce faulty responses and a large number of
scan cells can capture those faulty responses.
Diagnosis in a BIST environment adds an extra
level of difficulty compared with diagnosis in a
non-BIST environment because it requires
determining from compacted output responses
which test vectors have produced a faulty response
(time information) or which scan cells have
captured errors (space information).
One simple but highly inefficient way to
perform BIST diagnosis is to just bypass the MISR
and shift out the full output response for every test
vector to an external tester. The problem with this
approach is that typically a very large number of
test patterns are applied to the circuit during BIST
(orders of magnitude more than are applied in
conventional deterministic testing); consequently,
the tester may not have sufficient memory to store
the full output response data for every vector.
Moreover, the time required for collecting and
processing all of this data is generally not as cost
effective as other more efficient BIST diagnosis
approaches that are described in the remainder of
this section.
IMPLEMENTED SYSTEM
Fig.2: Implemented System
STUMPS ARCHITECTURE
Self-Testing Using MISR and Parallel SRSG
A BIST architecture that is widely used in
industry is the STUMPS architecture which is
illustrated in Figure 3. The core logic contains
multiple scan chains which are loaded from a
PRPG. After a test vector has been shifted in, the
system clock is applied and the output response is
captured back into the scan chains. As the next test
vector is shifted in the output response gets shifted
out and compacted into a MISR. For diagnosis, a
scan-in port can be connected to the PRPG to
externally load an initial seed (starting pattern), and
a scan-out port can be connected to the MISR to
shift out a final signature for observation.
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Structure and Operation of the proposed system
Implemented system is an ASIC that
consists of two blocks one is sequential and other is
combinational circuits shown in figure.4. The
sequential circuits which consists of decade
counters and they are tested by using technique of
controllability. In the combinational circuit which
consists of seven segment decoders they are tested
by using of Logic-BIST.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 2- Dec 2013
required signal is to generate the test patterns is the
clock.
“Linear Feedback Shift Register or LFSR
is a shift register whose input is the result of XOR
of some of its inputs”. There are two ways to
implement LFSRs: Internal feedback and External
feedback. These techniques differ in the way
feedback is applied. All the flip-flops that feed an
XOR gate are known as ‘taps’. These taps decide
the patterns generated by the LFSR and hence
define the characteristic polynomial of an LFSR. In
case of an external feedback LFSR the XOR gates
are in the feedback path and the input to the shift
register is the XOR of all the taps as illustrated in
figure .5.
Fig.5: External Linear Feedback Shift Registers
Fig.4: Proposed system block diagram
The frequency counter is used to
implement ASIC Chip it composed of two sections
one is sequential and other one is combinational.
The implemented work is tested by two modes (test
mode and normal mode).in the normal mode the
total system acts as frequency counter to count the
total number of clock cycles. The frequency
counter can count from 0 to 9999 clock cycles.
In the test mode if there is no fault it can
enable the decade counters and the data is
transformed to the XOR gates. For no fault
condition the XOR gate output is 0 if there is a
fault the XOR gate op is 1. In normal test mode
condition it can take 9999 clock cycles but the
proposed design required only 9 clock cycles with
the help of control logic. And this total section is
called the testing technique of controllabity and
observability of sequential circuits.
The other section of ASIC chip is tested
by using of LOGIC-BIST and it is testable by using
of STUMPS Architecture. LFSR generates the test
patterns and it is applied to the combinational
section of ASIC Chip. Combinational circuit which
consists four seven segment decoders and the
testable output is applied to the signature analyzer.
If there is a fault the signature analyzer produces
the output as 1 else the output is 0.
LFSR (Linear Feedback Shift Register)
One of the main parts of BIST is a Linear
Feedback Shift Register it is a clocked synchronous
shift register augmented with appropriate feedback
taps and receiving no external input. The only
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The characteristic polynomial p(x) for
both types of LFSR is P(x) =x0+x1 +x3+x4; n=4 ‘n is
the degree of the polynomial which is defined by
the number of bits/nodes of the LFSR. Notice that
the terms ‘x0’ and ‘xn ’ are always present and the
remaining terms indicate the location of the taps in
the circuit. The degree of the polynomial n is equal
to the number of bits in an n-bit LFSR pattern. An
all zeroes state is invalid for an LFSR as the state
would never change if all the bits are ‘0’. Therefore, the maximum number of unique patterns an nbit LFSR can generate = 2n – 1, A 4-bit
programmable LFSR has been designed for this
project. It is designed for both speed and area
considerations. It is because programmable LFSR
when we give the size as input. It generates random
patterns of the particular size. Every LFSR has a
characteristic polynomial that describes its
behaviour. The LFSR code was tested using the
MODELSIM tool. A seed was given and the LFSR
generated patterns corresponding to the seed given.
For each different seed it produces different
patterns.
Multiple-input signature registers (MISR)
MISR is can be used to reduce the
hardware required to compress a multiple bit
stream. The test patterns for BIST can be generated
at speed by an LFSR with only a clock input. Then
the outputs of the DUT (Device under test) must be
compared to the known good response which is
termed as the golden signature.
In this design collecting each output
response and off-loading it from the DUT for
comparison is too inefficient to be practical and this
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will consume a more storage capacity. In order to
compress the entire output stream into a single
signature value, a multiple input signature analysis
register can be used. Signature analysis is the most
popular compaction technique used today.
BIST Controller
BIST Controller is a most important part
of the BIST system it controls the operations of
different blocks of the BIST. Based on the test
mode input to the control the system either operates
in the normal mode or in the test mode. When the
T/N in this T is 1 the system enters the test mode it
gives the enable signal to the LFSR which
generates the test patterns and fed in to the DUT
and then it gives enable signal to MISR for
compaction of pattern from the DUT.
The controller takes charge of the overall
BIST flow. At the ASIC level, logic BIST and
memory BIST can share the same controller, and
the on-chip processor can function as the sequencer
during the memory BIST mode. However, the
controller contains an FSM. After the SCAN test
mode has been completed successfully, we enter
the memory BIST mode. The FSM actually
controls the scan test and BIST flow to test the rest
of the BIST circuitry.
The BIST controller that we designed
follows the STUMPS architecture and has a state
machine that controls the BIST session. The states
that were assumed in the state machine are: normal,
enable, BIST_run and BIST done. The controller
supports scan chain concatenation, presenting the
many short DUT scan chains and is designed to run
from an at-speed clock. The controller actually
applies the test. This consists of loading the scan
chains with data, handling the scan enable pin for
data capture and then unloading the scan chains.
output will be different from the golden values of
the circuit.
Signature Analyzer
Signature analyzer is capable of
distinguishing between good and bad circuits.
Golden signature refers to the good machine
signature which is the output of the MISR when the
circuit is working perfectly which has already been
evaluated and stored? Then it is comparing with the
Testing procedure of signature, if any discrepancy
is found then it say that the circuit is faulty.
Result Analysis
In this proposed paper proposed ASIC
Chip consists of mainly two sections one is
sequential and other one is combinational circuits.
The first section (sequential section) is tested by
observability and controllability. The Implemented
ASIC is a frequency counter. The other section of
ASIC chip is tested by use of LOGIC-BIST and it
is testable by using of STUMPS Architecture.
The given figure.6 shows for the normal
mode. In this mode the frequency can count 0 to
9999 clock cycles. And the output of the counter is
displayed by using seven segment displays.
Design under Test
The ASIC is to be tested is termed as the
Device under Test or the DUT. It is the circuit of
the IC that is going to be checked for any defects
after its manufacturing. The BIST scheme checks
for any physical defects that are bound to occur in
the IC namely bridging faults, and most
importantly stuck-at faults. Any digital design
represented in one of the Hardware Description
Languages (HDL’s) is used as a DUT. The BIST
controller gives the input size to the LFSR and
enables it. It generates random patterns of that size
and is fed to the DUT.
The DUT is converted into scan chains for
the purpose of testing. When the inputs to the DUT
is given, the scan chain works according to the
shift-capture loop, generates some output which is
then given to the MISR for compression. If the
particular circuit is faulty, then the patterns
generated by the circuit in response to the LFSR
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Fig.6: Normal mode output of designed system
The given figure.7 shows test mode output
without faulty condition (tnbar=1).in this mode all
the decade counters are enabled and the output is
observed at XOR gates. If there is no fault in the
decade counter XOR gate output is zero .if the
there is no error in the seven segment decoder the
signature analyzer produces the output as 0 (fop).
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 2- Dec 2013
In this dissertation a particular ASIC size
is fixed and hence the results are observed for
different test modules. In my project I have tested
the complete circuit operated with two modes such
as tnbar (test and normal mode) and clock cycle to
improve the speed of ASIC testability.
REFERENCES
Fig.7: Test mode output of designed system
without faulty condition
The given figure.8 shows faulty output of
the designed system .If the fault considered in
decade counter and seven segment decoder the
same output shown by using XOR gate as well as
signature analysis.
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Fig.8: Test mode output of designed system with
faulty condition
Conclusion
The Multi testability is designed in VHDL
and tested for a simple ASIC of frequency counter
and provides the testability in different modes. This
system consists the different combinational and
sequential circuits. The combinational circuits are
tested using the path synthesized analysis mode. In
this STUMPS architecture to reduce the clock
cycles generally that is used to convert serial mode
operation into parallel mode operation. The
sequential circuits are tested by using the
controllability and STUMPS architecture is used to
reduce the clock cycles.
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