International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- September 2013
Reconfigurable Correlator Module for Satellite
Data Pattern Recognition
D.Swathi (M.Tech student)
Dept of ECE, Sreenidhi Institute of Science and Technology, Andhra pradesh, India
Abstract—This paper realizes an reconfigurable correlator
module can be utilized to data pattern recognition in
remote sensing applications. Enhancement of data is one
of the essential parts of the data processing in remote
sensing applications. Enhancement of data possible
electronically and effectively by reconfiguration
computing. HDL code is used for developing the
reconfigurable correlator of FPGA,then developed
modules are compiled and thoroughly verified for meeting
the required timing specifications then are synthesized into
the target FPGA Also showing the configurability done
with the FPGA by giving the 128 bit correlate results.
Anti-fuse Switch by default is OFF; when programmed it is
ON. Advantages: negligible delay small area overhead
Disadvantages, not really reconfigurable; one time
programmable.SRAM-based
configuration
can
be
reprogrammed on the fly by downloading different
configuration bits into the SRAM memory cells. SRAM bit
cell stores the programmability of the device Advantages
can be reconfigured quickly and as repeatedly as required
no special fabrication steps Disadvantages: takes more area
loses charge when turned off coming to the flash, Switch by
default is ON;when programmed it is OFF.Advantages:
programming not lost when device is turned off.
Disadvantages require more manufacturing steps.
Keywords- FPGA, FSC, HDL
1.
INTRODUCTION
Reconfigurable computing has evolved from fieldprogrammable gate arrays (FPGAs).FPGA consist of a
matrix of logic blocks and an interconnection network. By
downloading bits of configuration data onto the hardware,
functionality of the logic blocks and the connections in the
interconnection network can be modified.Currently,using
hybrid architectures which integrate programmable logic
and interconnect with a microprocessor on the same chip.
On-chip integration of reconfigurable International
technology roadmap for semiconductors logic reduces the
memory access costs and the reconfiguration costs.
The speed and methodology of downloading bits of
configuration data onto the hardware depend on the
interface supported by the device. Two possible interfaces
are bit-serial and bit-parallel interface. The time taken for
downloading is directly proportional to the size of the bit
stream. Currently, there is a large class of FPGAs available
commercially. Nowadays most of the computing systems
have been constructed by integrating multiple FPGAs and
dedicated memory. Some systems also couple a general
purpose microprocessor or an ASIC such as a DSP to the
FPGAs An FPGA consists of an array of combinational
logic blocks overlaid with an interconnection network of
wires (see Fig.1). Both the logic blocks which includes logic
elements and input/output elements used to implement
combinational and sequential logic and for external
connections and the interconnection network are
configurable. The configurability is achieved by using either
anti-fuse elements or SRAM or flash memory bits to control
the configurations of transistors. Anti-fuse technology
utilizes strong electric currents to create a connection
between two terminals and is typically less reprogrammable.
ISSN: 2231-5381
Typical logic block architectures contain a look-up table, a
flip-flop, additional combinational logic, and SRAM
memory cells to control the configuration of the logic block
(see Fig. 1). N-LUT direct implementation of a truth table
any function of n-inputs.N-LUT requires 2N storage
elements (latches) N-inputs select one latch location (like a
Memory).The logic blocks at the periphery of the device
also perform the I/O operations. The interconnection
network can be reconfigured by changing the connections
between the logic blocks and the wires and by configuring
the switch boxes which connect different wires. The switch
boxes for the interconnection network are also controlled by
SRAM memory cells.FPGAs typically permit unlimited
reconfiguration. To map large applications onto
configurable logic, various systems have been designed
which have several FPGAs on a board. These architectures
also provide local memory and dedicated or programmable
interconnect between the FPGAs. These board-level
architectures are usually designed to function under an
external controller or use One of the on-board FPGAs as a
controller. Examples of such systems include the
experimental DECPeRLe board,SPLASH-2, Teramac, and
the commercial WILD series from Annapolis Microsystems.
Some software tools exist which can automatically partition
the design between multiple FPGAs on a board using higher
level abstractions(referred from ieee paper).
http://www.ijettjournal.org
Page 3971
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- September 2013
Correlation logic is a function that correlates the input bit
sequence received from satellite with a reference sequence
. As the data coming from satellites which are of 600-800km
away are encoded, randomized and pass through the
atmosphere, to detect the start of frame and to avoid losses
in the data the correlation logic is developed. Also error
allowances are programmable to detect the number of errors
available in the incoming data.
Figure1.Typical FPGA board, device, and logic block architecture.
FPGA
reconfigurability
can
be
achieved
by
SRAM,Flash,Anti fuse techniques each one has its own
properties. When one is building a reconfigurable device
with the FPGA,there are two options one is to work at the
level of the logic blocks available in the FPGA.In other
means ,it operates directly with the configuration bit stream
of the FPGA.This requires the knowledge of the internal
structure of the FPGA,and the configuration bit stream but
this can be slow. other option is a new reconfigurable circuit
is created on the top of an FPGA.This method also called as
virtual reconfiguration its implementation cost can be
significant, as everything must be implemented using
resources available on the FPGA,in both the cases,desiner
has to come up with a suitable e configurable logic blocks
and interconnections based on application.
Previously, all the designs were implemented using
microprocessors of 8bit,16bit,32 bit,64 bit those having
fixed input capabilities .when we want to design a new
module we have to change the whole system and to replace
a new processor consumes both cost and time. As
technology has improved we have FPGAs, in satellite data
acquisition needs designing of complex modules and testing
of those module places a very important rol. Based on the
application the data rate will change and th e data available
for less time so there is a need for using a faster and a
reconfigurable designs, to meet all these requirements.
Reconfigurability on a FPGA can be done using various
tools as VHDL,verilog,AHDL.This paper includes first
introduction to reconfigurable technology, then the design
and implementation of the 128bit correlator,results of
correlator and the floor plan shows the no of used LABs,
then conclusion and future scope, references.
This correlator was designed using AHDL. The design
consists of two independently clocked 128 bit shift registers,
an 128 bit register to store the output resulting from the bit
by bit comparison of the incoming input and value stored in
reference latches. An independently clocked digital
summing network calculates the number of errors occurred
during the comparison process. A raw detect will be
generated if the comparison is below the threshold or else
the flywheel logic is initiated according to the frame length
and will generate a loss pulse at the same point. Thus the
loss frames are detected by the number of loss pulses
generated.
128 bit shift register
128 bit latch register
A.
128 bit reference register
Xor gate output register
4 bit pipeline
summer
raw
det
ect
Threshold 2 bit
Figure2. Correlator block diagram
II.
RECONFIGURABLE CORRELATOR
IMPLEMENTATION
Using the reconfigurability advantage in FPGA,a
reconfigurable 128 bit correlator was designed. The FPGA
used was Altera’s Stratix device and the coding was done in
max plus II software. The major advantage of maxplus is, it
provides text editor, graphic editor to write the code and and
wave form editor for functional and timing simulation.
ISSN: 2231-5381
A part of the satellite data frame will consist of the start
of frame code usually in the beginning. This start of frame
data is to be correlated with the reference data generated by
Data Pattern Generator (DPG) in the satellite ground
segment . The DPG generates the data for a particular
satellite according to the format. The reference data
http://www.ijettjournal.org
Page 3972
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- September 2013
continuously comes from DPG to the 128 bit reference
register. Code is shown below
in_datareg=LCELL(LCELL(test.sout));
--in_data_reg[0]=in_datareg;
in_data_reg[0]=test.sout;
test_sout= in_data_reg[0];
The satellite data will be stored in another 128 bit shift
register having data and clock input. while comparing the
bits the satellite data in 128 bit register can be temparaly
stored in a 128 bit latch register. Then by using xor gates we
will compare bits, for matched bits result will be zero and
for unmatched the result will be one i.e one error. All the
outputs of xor gate stored in 128 bit register. Then
summing up of all errors in the pipe line summer is done.
The bits in the main shift register are divided into 32 sets
having 4 bits each which can also be represented by 4 x 32
will be present in 4 bit pipeline summer as shown in fig 2.
Now the 128 bit is reduced to 96 bit by true number
conversion method. From here each three bits are added
simultaneously using pipeline summer. The sum of those
gives a four bit sum of 32bit, similarly goes on the four bits
are added to give a five bit with each 20 bits and last of six
bit adder with each 12 bits.. The below code for pipe line
summer
for i in 0 to 15 generate
(fststg_reg[i*4+3],fststg_reg[i*4+2..i*4])=((0,bin_vector_va
lue[i*6+2..i*6])+(0,bin_vector_value[i*6+5..i*6+3]));
for j in 0 to 7 generate
This output detects the arrival of loss pulse if error has
been occurred and threshold value is less than the no of
error bits has occurred. If there is no error or a 2 bit error
which falls under the threshold value the raw detects pulse
occurs, which means the data receiving is valid. From these
pulses of loss and raw detect we adopt a strategy to generate
states of lock search verify and check.
In modern communication systems data is not transferred
as a simple stream of bits or bytes but in terms of frames or
packets In the serial frame synchronization that is when
each frame starts with an identical sync code, false sync
randomly generated by the data is completely eliminated by
appropriate
frame
synchronization
code.
Frame
synchronization is obtained by inserting in series (e.g. at the
beginning of each frame), or in parallel (i.e. on a separate
sync channel), a frame sync code (FSC). At the receiver, the
frame synchronizer correlates the received signal with its
own replica of the FSC for different bit shifts, until
synchronization is acquired. The synchronization is then
maintained by verifying the repetition of this code at each
frame provided the frame length is fixed.
ISSN: 2231-5381
In some other applications , data rates and the number of
data sources are not fixed but randomly vary then this
design is advantageous to change the frame length and data
format
In the selection of a frame-sync code, a decision must be
made as to its length and as to its composition of 1 's and
0's. 'Huts information theory indicates that the number of
bits required to specify the beginning of the frame is L= (25) log2 M.
Under very good channel conditions, however, a simple
AND gate may be used to detect the frame- sync code. But
if even one error is to be tolerated in the far proposed, which
is in operational use today, consist of a shift register of
length at least equal to that of the number of bits in the code
which feeds in parallel to a linear summing network in such
a way that the code to be detected may be programmed by
means of appropriate switches or logic.
In essence, a shift-register code recognizer serves as a
cross correlator and utilizes an m-out-of-n threshold logic
circuit for a decision as to when the code with acceptable
number of errors is in place on the shift register. It is readily
apparent that this same shift register may be used to drive
several or a number of linear summing network, each of
which is programmed to detect a specified code or cluster of
codes.The Frame Synchronization logic is realized in the
FPGA. The 128 bit correlation function is realized in the
FPGA. The incoming data is compared with the reference
frame sync code. When the correlation score is >= the
Threshold a Frame Sync Detect pulse is generated. If no
error is shown the correlator output is a sum of 128, if one
error is detected the sum is 127, and similarly for 2 errors
126 and 3 errors 125.A maximum of three errors are
allowed in the frame this can be adjusted by the 2 bit
threshold value given by the user given below,
if thresh_reg[] == 0 & sum_op[] == 128 then
raw_reg = TRUE;
elsif thresh_reg[] == 1 & sum_op[] >= 127 then
raw_reg = TRUE;
elsif thresh_reg[] == 2 & sum_op[] >= 126 then
raw_reg = TRUE;
elsif thresh_reg == 3 & sum_op[] >= 125 then
raw_reg = TRUE;
else raw_reg = FALSE;
To prevent false detects a flywheel logic is
included with strategy which has a search, check and lock
modes flow (shown in fig3) Flywheel is a free running
counter runs along with the correlator and detects the loss
pulse.When two consecutive syncs are detected the logic
will change from search to check and later to lock mode.
Likewise when a sync loss occurs the logic will change
from lock to check and when two consecutive sync losses
occur the logic will revert to search mode.This flywheel
shown in fig 3 is designed in maxplus by AHDL using 15
http://www.ijettjournal.org
Page 3973
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- September 2013
bit dff we can generate a count of 19199 like that we
design for other data rates as mentioned below.
fwf[].d=fwf[].q+1;
fw=(Fwf[]==33599);
fcout[]=fwf[];
dg2.clk=clk;
dg2.d=fw;
Welcome to
maxplusII
Design entry
For other datarates in which th e frame size is variable can
be seen in synthetic aperture radar antennas this flywheel
will be used.we can change the flywheel count in above
code as Fwf[]==33599 with required count Fwf[]==37248
for 4656 byte frame size.
Compilation &
Simulation
Synthesis
fitting
Design
change
Post layout
simulation
Search
Programming the
device
Verify LP/RD
LP
Figure4. Altera Maxplus II FPGA Devices Design Flow
Check
LP
RD
Lock
Figure 3. Flywheel technique
Ordinarily, when the system is in the acquisition mode, it
is scanning all bit positions until a sync indication is
produced by a frame-sync. Correlator, cit which time the
acquisition sequential circuit would change to the
verification mode. Since a false sync indication can be
produced by a data word or combination of data words
which pass the frame sync code test, some means is needed
to evaluate especially the first received sync indication. On
the other hand, after the system has locked into frame sync
there is a definite probability that a frame-sync indication
will be missed because of an excessive number of errors in
the received code or a signal drop-out; consequently there
must be a built-in memory capability in the acquisition
circuitry to allow the system to coast through short signal
perturbations.
The both correlator and flywheel design occupied 35%
of available logic on FPGA.The designed correlator is
simulated in maxplus tool using graphic editor. These
simulation results show the correlated output with raw
detect for detected frame and loss pulse for undetected
frame, also simulated the results for different error values by
changing the threshold value.
Designing involves a flow given in below diagram
ISSN: 2231-5381
Flow of design starts with design entry where we have to
develop a code for the module, then the functioning will be
verified along with the waveforms in the compilation and
simulation shown in the fig 4.Then synthesis can be done by
selecting the device which we used in the FPGA.
Various other frame synch detecting techniques
described, the beginning of the frame is determined by
recognizing a sync word ,or a binary sequence of given
length which is not likely to be confused with a string of
information bits. When further identification of sync words
occur at intervals equal to integer multiples of a length of a
frame ,then a final determination can be made that frame
synchronization has been attained. in this thesis the figure of
merit depends on how reliably good data is frame synched
,and how few errors are made in labeling as synched data
which is not properly synched or data which has a large
number of errors. Imagine a communication system with
two Data Terminal Equipments (DTEs) that have a major
difference in the speed of their system clocks. The receiver's
clock is running 12,5% ahead of time than the sender's one.
If the sender transmits a 8-bit word, the receiver will
interpret it as a 9-bit word, then receiver will not only
sample to much bits, it will also sample wrong bits. The
conclusion should be that there can be no unambiguous
interpretation of a common signal, if there is not a certain
degree of synchronization of clocks.
Another well-known problem of time dispersion is called
inter symbol interference. Signals belonging to different
symbols can be observed on the medium at the same time,
leading to interpretation errors at the receiver's end.
Synchronization techniques will guide the receiving system
http://www.ijettjournal.org
Page 3974
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- September 2013
in determining where data entities start and end and at
which time interval the sampling result is least error prone.
You can see bit and frame synchronization as a very basic
mechanism of error control which will reduce the need for
error control at higher levels.Frame Synchronization via
start and end flags is very widely used. The general idea is
to separate the single frames by special data sequences, the
flags. These flags are commonly referred to as "STX" which
stands for "start-of-text" and "ETX" for "end-of text".
Whenever the receiver encounters a STX flag it knows it
has detected the beginning of a new frame whilst ETX
signals the end of the current frame. This can be done using
the 8 bit microprocessor.
Stuffing algorithms for network transmission describe a
method of encoding the user data so that all occurrences of
the flag are removed. This encoding has to be 0 so that the
receiver can extract the user data after separating the frames.
Stuffing algorithms can be classified as bit or as byte
oriented algorithms. In the first case the receiver and sender
examine the received data in terms of bits. The flag is a
special sequence of bit values. This method is usually
chosen if the algorithm has to be implemented in hardware.
In the latter case both the sender and the receiver talk in
terms of bytes. This is useful if the algorithm is
implemented in software, because processors usually
operate on byte values rather than on bits. Using bits would
result in a slowdown of the algorithm because the
processing capabilities of the computer would not be
exploited. Modern processors can process at least complete
byte values at one step.
In digital communication systems frame synchronization
can be achieved by adding to the transmitted symbols
synchronization sequence known by the received symbols
though the correlator in order to improve the performance
need to increase the length of inserted synchronization
word, which reduces the spectral efficiency of the system.
Another solution to improve the system performance is to
take advantage of the code structure and consider frame
synchronization jointly with the decoding, rather than
placing the synchronization bits in a separate header
proposed to place them in a midamble. the observed
symbols are modeled as the output of a Markov chain
corrupted by additive white Gaussian noise, it is a blind
method of frame synchronization wherein no additional
sequence is added to the coded one. This synchronization
method is based on a MAP approach in the sense of
minimizing the probability of false frame synchronization of
a coded system.
Coming to the Stratix you can configure the Stratix
device directly, without turning off power, using the
Quartussoftware and the ByteBlasterMV cable, as follows.1.
Attach the cable to JP17.2. Open a Quartus II SRAM
Object File (.sof ), which launches the Quartus II
Programmer.3. Select ByteBlasterMV as the hardware.4.
ISSN: 2231-5381
Set the mode to JTAG .5. Click Start On successful
configuration, the conf_done LED (D5) illuminatesthis
stratix has the no of logic elements(Les)25560,M-RAM
Blocks 224,total ram bits1944576,dsp blocks 10 blocks,
embedded multipliers 80,voltage used is 1.5v internal,3.3v
I/O.
III.
RESULTS
Flywheel showing the raw detect and missing pulse:
Floor planning showing the used and unused LABS
IV.
CONCLUSION AND FUTURESCOPE
In satellite data acqisition erroneous data or the loss due
to false synchronization can be minimized through use of
frame synchronization codes having the lowest probability
of false sync i.e. optimum Frame sync codes.In some future
cases, data rates and the number of data sources are not
fixed and it is advantageous to change the frame length and
data format as this designed reconfigurable correlator
module will be used for different frame lengths by
considering more or less no of bits.Here the designed
correlator achived 105Mhz speed and used 35% of available
resources on FPGA.This can be improved for further higher
data rates by utilizing the unused LABs.
http://www.ijettjournal.org
Page 3975
International Journal of Engineering Trends and Technology (IJETT) – Volume 4 Issue 9- September 2013
Pattern recognition and correlation technique for the
future satellite is expected to be around 160Mbits per
second. The pattern generator and Correlator used are
developed for the next cartosat, SAR satellites.
V.
REFERENCES
[1] Hand book of telemetry and remote control.
[2] Fundamentals of Remote Sensing by George Joseph.
[3] Digital Electronics Text book by Godse.
[4] Reconfigurable Computing, a book by Scott Hauck and
Andre’Dehon.Advanced FPGA Design:Architecture, Implementation, and
Optimization By Steve Kilts.
[5] Altera Max plus II User Guide.Data sheet of Altera Devices
[6] Tobias Schumacher,tim sub,Christian plessl,and macro platzner “FPGA
acceleration of communication bound streaming applications architecture
modeling and 3D image compositing casew study.Hindawi publishing
corporation international journal of reconfigurable computing volume
2011,artcle ID 760954.
[7] G.Prasad , N.Vasantha “Design and Implementation of multi channel
Frame Synchronization in FPGA”
[8] Lukas Sekanina,Petr Mikusek “Analysis of Reconfigurable Logic
Blocks for Evolvable Digital Architectures”Evo Workshops 2008,LNCS
4974
[9] Aliazarian,mahmoodalimadi “Reconfigurable computing architecture “
survey and introduction ‘proceedings of the ieee,2009
[10] Mathew p Jacobson,Stephen l coy and Robert w field,Extended cross
correlation:A technique for spectroscopic pattern recognition
[11] Katherine Compton ,scott hauck,’an introduction to reconfigurable
computing
[12]www.nrsc.gov.in,www.altera.com,www.ieeexlore.org,en.wikipedia.org
[13] Rodrigue Imad, Guillaume Sicot and Sebastien Houcke “Blind frame
synchronization for error correcting codes having a sparse parity check
matrix”
[14] Robertson, P.German Aerosp. Res. Establ., Oberpfaffenhofen,
Germany
AgeneralizedframesynchronizerGlobalTelecommunicationsConference,199
2.ConferenceRecord.,GLOBECOM'92.Communication for Global Users.,
IEEE
ISSN: 2231-5381
http://www.ijettjournal.org
Page 3976