Microprocessors
2nd stage
30-4-2013
Lec. (16)
College of sciences for women ((())) Dept. of computer sciences
Year 2012-2013
22.2.1. Minimum & Maximum Mode Systems
In the minimum mode, all the control signals for the memory and I/O are
generated by the microprocessor. This reduces cost but provides low
functionality. In the maximum mode, a separate IC called the 8288 Bus
Controller is used to provide control signals for memory and I/O operations.
The S0-S2 pins are decoded by the 8288 to provide control signals as ALE,
DEN, DT/-R, -IOWC (I/O Write Command), -IORC (I/O Read Command),
-MWTC (Memory Write Control), -MRDC (Memory Read Control), -INTA etc.
The minimum mode signals can be divided into the following basic groups:
address\data bus
status
control
interrupt
DMA
Address / data bus
As an address bus , they are used to carry address information to the memory and
I/O ports. The address bus is 20 bites long and consists of signal lines A0 through A19.
Of theses , A19 represented the MSB and A0 the LSB. A 20- bites address gives the
8086 a 1M-byte memory address space .
Lecturer: Salah Mahdi Saleh
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The 16 data bus lines D0 through D15 are actually multiplexed with address lines
A0 through A15, respectively. By “multiplexed “We mean that the bus works as an
address bus during one period of time and as a data bus during another period . D 15 is
the MSB and D0 the LSB.
Status Signals :The four most signification address lines , A19 through A16 are also multiplexed ,
but in this case with status signals S6 through S3. These status bites are output on the
bus at the same time that data are transferred over the other bus lines.
Bits S4 and S3 together form a 2 – bit binary code that identifies which of the
8086 internal segment registers was used to generate the physical address that was
output on the address bus during the current bus cycle.
Control signals
The control signals are provided to support the 8086's memory and I/O
interfaces. They control functions such as when the bus is to carry a valid address, in
which directions data are to be transferred over the bus, when valid wire data are on the
bus, and when to put read data on the system bus.
Interrupt signals
Interrupt operations fall into two classes; software or hardware initiated.
Hardware interrupts can be classified as non-maskable or maskable. Interrupts result in
a transfer of control to a new program location. A 256-element table containing address
pointers to the interrupt service program locations.
DMA
the direct memory access (DMA) interface of the 8086 minimum -mode system
consists of the HOLD and HLDA signals. When an external device wants to take
Lecturer: Salah Mahdi Saleh
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control of the system bus, it signals this fact to the 8086 by switching HOLD to the 1
logic level .
Power
supply
INTR
Interrupt
Interface
Vcc
GND
A0-A15,A16/S3-A19-S6
INTA
TEST
D0-D15
NMI
ALE
RESET
BHE / S7
DMA
Interface
M / IO
HOLD
DT / R
HLDA
RD
WR
Vcc
DEX
Mode Select
READY
MN/MX
CLK
Clock
22.3 Registers 0f 8086 cpu
Most of the registers contain data/instruction offsets within 64 KB memory
segment. There are four different 64 KB segments for instructions, stack, data and
extra data. To specify where in 1 MB of processor memory these four segments are
located the processor uses four segment registers:
Code segment (CS) is a 16-bit register containing address of 64 KB segment
with processor instructions. The processor uses CS segment for all accesses to
instructions referenced by instruction pointer (IP) register. CS register cannot be
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changed directly. The CS register is automatically updated during far jump, far call
and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment
with program stack. By default, the processor assumes that all data referenced by
the stack pointer (SP) and base pointer (BP) registers is located in the stack
segment. SS register can be changed directly using POP instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment
with program data. By default, the processor assumes that all data referenced by
general registers (AX, BX, CX, and DX) and index register (SI, DI) is located in the
data segment. DS register can be changed directly using POP and LDS instructions.
Extra segment (ES) is a 16-bit register containing address of 64KB segment,
usually with program data. By default, the processor assumes that the DI register
references the ES segment in string manipulation instructions. ES register can be
changed directly using POP and LES instructions.
22.3.1 General registers
The eight, 16-bit general purpose registers are used for arithmetic and logical operations.
In addition, the four data registers labeled AX, BX, CX and DX may be further subdivided
for 8-bit operations into a high-byte or low-byte register, depending where the byte is to be
stored in the register. For example, MOV AL,6D would place the immediate hexadecimal
value 6D into register AL.
These registers are not completely general purpose in the same way that D0 through
D7 of the 68K are general purpose. The AX register, as well as its two half registers, AH and
AL, are also known as an accumulator. An accumulator is a register that is used in arithmetic
and logical operations. Accumulator can be used for I/O operations and string
manipulation. The AX register must be used when you are using the multiply and divide,
MUL and DIV, instructions. For example, the code snippet:
MOV AL,10
Lecturer: Salah Mahdi Saleh
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MOV DH,25
MUL DH
would do an 8-bit by 8-bit multiplication of the contents of the AL register with the contents
of the DH register and store the resultant 16-bit value in the AX register. Notice that it was
not necessary to specify the AL register in the multiplication instruction since it had to be
used for a byte multiplication.
Base register consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX. BL in this case contains the
low-order byte of the word, and BH contains the high-order byte. BX register usually
contains a data pointer used for based, based indexed or register indirect
addressing.
Count register consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX. When combined, CL register
contains the low order byte of the word, and CH contains the high-order byte. Count
register can be used as a counter in string manipulation and shift/rotate instructions.
Data register consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX. When combined, DL register
contains the low order byte of the word, and DH contains the high-order byte. Data
register can be used as a port number in I/O operations. In integer 32-bit multiply and
divide instruction the DX register contains high-order word of the initial or resulting
number.
22.3.2 Flag Registers
After the execution of an instruction the flags may be set (1), cleared or reset (0),
unchanged or undefined. Undefined means that the value of the flag prior to the execution of
an instruction may not be retained and its value after the instruction is executed cannot be
predicted. Flags are a 16-bit register containing nine 1-bit flags:
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• Bit 0: Carry Flag (CF) Set on a high-order bit carry for an addition operation or a borrow
operation for a subtraction operation; cleared otherwise.
• Bit 1: Reserved.
• Bit 2: Parity Flag (PF) Set if the low-order 8 bits of a result contain an even number of
1 bits (even parity); cleared otherwise (odd parity).
• Bit 3: Reserved.
• Bit 4: Auxiliary Carry (AF) Set on carry or borrow from the low-order 4 bits of the AL
general-purpose register; cleared otherwise.
• Bit 5: Reserved.
• Bit 6: Zero Flag (ZF) Set if the result is zero; cleared otherwise.
• Bit 7: Sign Flag (SF) Set equal to the value of the high-order bit of result. Set to 0 if the
MSB = 0 (positive result). Set to 1 if the MSB is 1 (negative result).
• Bit 8: Trace Flag (TF) When the TF flag is set to 1, a trace interrupt occurs after the
execution of each instruction. The TF flag is automatically cleared by the trace interrupt after
the processor status flags are pushed onto the stack. The trace service routine can continue
tracing by popping the flags back with a return from interrupt (IRET) instruction. Thus, this
flag implements a single-step mechanism for debugging.
• Bit 9: Interrupt-Enable Flag (IF) When set to 1, maskable, or lower priority interrupts are
enabled and may interrupt the processor. When interrupted, the CPU transfers control to the
memory location specified by an interrupt vector (pointer).
• Bit 10: Direction Flag (DF) Setting the DF flag causes string instructions to autoincrement
the appropriate index register. Clearing the flag causes the instructions to autodecrement the
register.
• Bit 11: Overflow Flag (OF) Set if the signed result cannot be expressed within number of
bits in the destination operand; cleared otherwise.
• Bits 12-15: Reserved.
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