Objectives:
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Designing a 4-bit counter
Capability of Set/Reset
Justification for choice of design
Proof of proper functionality
Drawing a layout that is DRC and LVS clean
Calculating rise time, fall time, propagation delay
Submitting the chip for fabrication
Design of the Counter:
I decided to design a 4-bit Up counter. An edge-triggered flip-flop had to be designed before going
into the design of the counter. I chose to design my counter using Master-Slave D-flip-flops. The reason
behind choosing D-flip-flop was it uses a very simple configuration. Also D-flip-flops can operate as any
other type flip-flop if the application requires. The type of counter that I chose to design was an
asynchronous one. It means that the clock signal was not common for all the bits. The clock propagated
through one stage to the other. Even though this approach made the counter slower, the configuration
is simpler. No additional gates or logics were needed in the final counter circuit. I also chose to use
asynchronous active low Set/Reset which meant that the output would go HI when the Set signal would
go LO and the output would go LO when the Reset signal would go LO, irrespective of the value of the
clock. Both Set and Reset could not go LO at the same time.
The figure below shows the schematic of the counter. Each block in the design is a Master-Slave Dflip-flop. The Qb output of each of the blocks went into its input, which meant that the output was
toggled every time there was a clock pulse. The first block had the actual clock at its clk input, but the
other blocks used the Qb output of the previous stage as its clk signal.
Figure: Schematic of the 4-bit Counter
The figure below shows the schematic of a Master-Slave D-flip-flop. Two D-flip-flops were
connected one after another. The two blocks used complimentary clocks to ensure edge-triggered
operation of the overall system. To ensure positive edge-triggered operation, the first block used the
inverted clock and the second block used non-inverted clock.
Figure: Schematic of the Master-Slave D-flip-flop
The figure below shows the schematic of a D-flip-flop. It has an inverter, 2 2-input NAND gates and
2 3-input NAND gates. The 3-input NAND gates were needed to accommodate the Set/Reset signals.
Figure: Schematic of the D-flip-flop
Layout:
After the design was complete, I performed the simulations to see if the design was functioning
properly. As the pre-layout and the post layout simulation matched pretty closely, I will show only the
post-layout simulation results in the report.
I went into the layout of the circuit then. The complete layout of the 4-bit counter is shown below.
It had an area of 432µm × 41.1 µm. The layout was DRC error free. I extracted the layout for LVS then
and the LVS matching was successful.
Figure: Layout of the 4-bit counter
Here is a zoomed in view of a part of the counter. This actually represents the layout of one of the 4
Master-Slave D-flip-flops that was used in the design.
Figure: Zoomed in View of the Layout
Post-Layout Simulation:
The extracted schematic was used to perform post-layout simulation. In this case, the clock
frequency was 100MHz and there were no load capacitance. The simulation result below shows the
proper functionality of the circuit. With each clock pulse, the count increased by 1 (Q3 is the MSB, Q0
the LSB). When the reset signal was LO, all the bits were LO and when the set was LO, all the bits were
HI.
Figure: Post-Layout Simulation Showing Proper Functionality
To provide ease of inspection, I converted all the signals into digital signals. I also made an output
bus, which consisted of the 4 output bits, named Count. The figure below shows the digital result from
the simulation.
Figure: Post-Layout Simulation Showing Digital Output
Calculation of Rise Time, Fall Time and Delay:
Using the calculator function of the simulator, the 10-90% Rise and Fall times for each bit was
calculated for different values of load capacitance. The load capacitance was varied from 1pF to 5pF.
Also the propagation delays with respect to the clock of the circuit for all the bits were calculated as
well for different load capacitance values. All these values are summarized in Table 1 below:
Load
Capacitance
(pF)
1
2
3
4
5
Rise Time (ns)
Fall Time (ns)
Q0
Q1
Q2
Q3
Q0
2.93 2.93 2.96 1.61 12.46
5.45 5.45 5.45 5.26 24.47
7.9
7.89 7.89 7.67 36.36
10.32 10.32 10.33 10.08 47.84
12.74 12.74 12.74 12.47 60.06
Q1
12.47
24.49
36.29
47.96
60.08
Q2
12.49
24.47
36.28
47.96
60.08
Propagation Delay (ns)
Q3
12.47
24.27
36.03
48.02
60.09
Q0
1.67
3.05
4.42
5.78
7.16
Q1
2.12
3.49
4.85
6.23
7.62
Q2
2.6
3.97
5.33
6.71
8.09
Table 1: Summary of Rise Time, Fall Time and Delay against Load Capacitances.
The figures below show the plots of different timing performances vs the load capacitances.
Rise Time vs Capacitance
14
12
10
Rise Time 8
(ns)
6
Q0
4
Q2
2
Q3
Q1
0
0
1
2
3
4
5
Capacitance (pF)
Figure: Plot of Rise Time vs Load Capacitance
6
Q3
3.08
4.45
5.81
7.19
8.57
Fall Time vs Capacitance
70
60
50
Fall Time (ns)
40
Q0
30
Q1
20
Q2
10
Q3
0
0
2
4
6
Capacitance (pF)
Figure: Plot of Fall Time vs Load Capacitance
Delay vs Capacitance
Delay (ns)
9
8
7
6
5
4
3
2
1
0
Q0
Q1
Q2
Q3
0
1
2
3
4
5
6
Capacitance (pF)
Figure: Plot of Propagation Delay vs Load Capacitance
As it can be seen, rise time, fall time and delay increase almost linearly with the increase of load
capacitance. The fall time is quite large in comparison to the rise time. This can be attributed to the
sizing of the N-Trees of the NAND gates. For equal rise and fall time, the P-Tree and the N-Tree should
have equal resistance. So, to make the resistance of the N-Tree smaller, so that the fall time would
decrease, the N- transistor sizes needed to be made larger (2 times larger for 2-input NAND and 3 times
larger for 3-input NAND gate).
Chip Fabrication:
The complete layout was placed in a padframe. This will be sent for fabrication. The figure below
shows the chip layout:
Figure: Layout in Padframe
Conclusion:
Overall the project was a successful one. The designed counter shows very good performance in
terms of functionality, area and propagation delays. I also learnt different aspects of circuit design and
layout while doing this project. I would like to perform the experimental tests once I get the chip back
after fabrication.