Design and Simulation of a Digital CMOS Synchronous 4-bit
Up-Counter with Set and Reset
Course Number: ECE 533
Spring 2013
University of Tennessee Knoxville
Instructor: Dr. Syed Kamrul Islam
Prepared by
Ifana Mahbub
April 26, 2013
1. Introduction
A counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, especially in digital logic or computing. 4-bit counters are among
the most basic designs of digital systems. Because of their simplicity they are also good
examples for beginners to start with their digital circuit design experience. 4-bit counter has vast
number of implementations. With options such as synchronous vs. asynchronous, what flip-flops
topology to use and the style of counting (binary, gray-code, etc.) various counters could be
designed. The counter presented in this paper is a synchronous up-counter with serial-carry
output and input set and reset options. With the serial-carry output it is possible for it to be
cascaded to build a counter with more than 4 bits. Synchronous and up counter means the whole
design is controlled by a single clock and that the counter will only count from 0 to F and start all
over again. The input set and reset pin enables the user to set the counter to ‘all-ones’ and ‘allzero’ state and then to start counting again. The counter reported in this paper has been realized
using JK flip-flops following a master-slave approach. This is a negative edge-sensitive flip-flop.
As the J-K flip-flop can easily be used for toggle operation putting both J and K input to ‘1’, the
use of it in counter design is rightly justified. The circuit has been implemented in the AMI 0.5u
process where the length was 0.6 µm for each NMOS and PMOS.
2. The design
A popular approach of designing a master-slave J-K flip-flop is using two 3-input NAND gates,
six 2-input NAND gates and two inverters in a feedback loop. A change of state occurs when the
flip-flop senses a negative edge of the clock signal. The logic diagram of this common is shown
below:
Figure 1 Common Logic Diagram of a J-K Flip-flop
This design has been further modified by incorporating a set and reset pin at the input. This has
been accomplished easily by the addition of eight extra gates (two AND, two OR gates and two
Inverters) as shown in Fig. 2.
Figure 2 JK FF schematic
3. Logic and truth table
The counter operates on the falling edge of the clock meaning the states do not change until the
clock signal inputted into the first JK flip-flop goes from logic HI to logic LO. When the set and
reset input S and R are at logic ‘0’, the flip-flop operates normally; whereas the output Q is
forced to ‘0’ irrespective of the input levels at J and K when R goes to ‘1’ and Q is forced to ‘1’
irrespective of the input levels at J and K when S goes to ‘1’. Therefore, the truth table of this JK flip-flop has been changed accordingly in Table 1.
Table 1 Truth table of JK flipflop with set and reset
S
0
0
0
0
0
1
R
0
0
0
0
1
0
J
0
0
1
1
d
d
K
0
1
0
1
d
d
Qn+1
Qn
0
1
~ Qn
0
1
As the counter operates on the falling edge of the input clock signal, the output only changes
when the CLK signal is going from 0 to 1 as illustrated in Table 2.
Table 2 Truth table of 4-bit counter
CLK
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
B2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
B1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4. Schematic and layout
The final schematic is shown in Fig. 3. The equivalent W/L ratio for NMOS gates is chosen to be
2.5 and that of PMOS is 5. The width of PMOS is selected to be twice the width of NMOS
because it does not hinder the correct functionality of the circuit and helps keeping the total chip
area low. Moreover, the performance of the circuit is highly acceptable within a wide frequency
range as we see from the simulation and different performance measurements. Different gates of
the JK flipflop (schematic and layout) are shown in the following figures.
Figure 3 Four bit counter Schematic
Figure 4 Inverter Schematic and layout
Figure 5 Two input AND gate Schematic and layout
Figure 6 Three input NAND gate Schematic and layout
Figure 7 Two input NAND gate Schematic and layout
Figure 8 Two input OR gate Schematic and layout
The layout of the JK flip flop is shown in Fig 9.
Figure 9 JK flip flop layout
The final layout of the 4 bit counter is shown in Figure 10. Three metal layers are used to help
reducing the area. The input clock signal, set and reset enter into each JK flip flop. The design on
the pad frame is shown in Figure 11. As the figure shows, the dimensions of the 4-bit counter
measure to be 731μm x 84μm which gives an overall area of 0.061 mm2 for the design.
Figure 10 Four bit counter layout
Figure 11 Layout of 4-bit counter on pad frame (left) and a closer look (right)
5. Simulation and results
Pre-Layout Simulations with set and reset pin enabled are shown in Fig 12 and 13.
Figure 12 Captured pre-Layout Simulation waveforms with set pin (left) and reset (right) enabled
Post-layout simulation of the design was done and the counter performed as expected. As Figure
14 shows, the counter counts up to ‘F’ and then restarts back at ‘0’.
Figure 14 Captured post-Layout Simulation waveforms with reset (left) and set (right) pin enabled
6. Performance analysis
Table 3 depicts the rise and fall times of the counter output bits with load capacitance of 1 pF.
The rise time was defined as the time it took the signal to go from 10% VDD (0.5V) to 90%
VDD (4.5V), and the fall time was defined as the time it took the signal to fall from 90% VDD to
10% VDD.
Table 3 Rise time and fall time for outputs with 1 pF load capacitance
Output bit
B0
B1
B2
B3
Rise time (ns)
10.908
10.698
10.698
10.659
Fall time (ns)
15.049
14.719
14.720
14.658
The rise time for each bit is less than the fall time for that bit. It means the charging RC constant
is less than that of the discharging one.
Figures 15 shows the delay vs. capacitance graphs of the counter output signals with load
capacitances varying from 1 to 5 pF. The delay time is defined as the time it took the signal to
get to 50% of VDD (2.5V) after the clock signal reached 2.5 V.
Cap Vs. Delay (B1)
Cap Vs. Delay (B0)
100.000
90.000
90.000
80.000
80.000
70.000
70.000
60.000
60.000
Delay (ns)
Delay (ns)
100.000
50.000
40.000
50.000
40.000
30.000
30.000
20.000
20.000
10.000
10.000
0.000
1
2
3
4
0.000
5
1
Load Capacitance (pF)
100.000
90.000
90.000
80.000
80.000
70.000
70.000
60.000
60.000
Delay (ns)
Delay (ns)
Cap Vs. Delay (B2)
100.000
50.000
40.000
2
3
4
Load Capacitance (pF)
5
Cap Vs. Delay (B3)
50.000
40.000
30.000
30.000
20.000
20.000
10.000
10.000
0.000
0.000
1
2
3
4
Load Capacitance (pF)
5
1
2
3
4
5
Load Capacitance (pF)
Figure 15 Delay vs. capacitance of the counter output signals with load capacitances varying from 1 to 5 pF
From the figure we can say that the delay time for the counter increases as the load capacitance
increases.
7. Test Result
The chip has been tested for various frequencies. They are shown below:
Figure 16 Output result for input frequency of 10 KHz
Figure 17 Output result for input frequency of 800 KHz
Figure 18 Rise time and fall time in the edges
8. Conclusion
This project has been a great opportunity for exercising the skills in designing digital VLSI
circuits with the help of the Cadence Virtuoso Custom IC Design Tool. From various design
steps of this project we have learned about many digital circuit design techniques, proper choice
of transistor sizes, design rules, laying out the circuit with minimum possible area, pre and post
layout simulation (with Spectre), layout extraction, LVS matching and measurement of different
performance factors. This project is successful as the chip came fabricated and the proper testing
has been performed.