Design for MOSIS Educational Program (Research)
Low Power and All Digital Frequency Synthesizer Design
Prepared by: Song Yuan, Kai Zhu, Melika Roknsharifi, M. Shahriar
Jahan, Tan Yang, Junjie Lu, Xiaojun Tu, Long Yu, Jinlong Gu
Dr. Jeremy Holleman, Dr. Syed Islam, Dr. Benjamin Blalock and
Dr. Nicole McFarlane
Institution: Electrical Engineering and Computer Science,
The University of Tennessee,
Knoxville, TN-37996-2100
Date of Submission of the Proposal: Oct 1th, 2011
Estimated Project Size: 16 mm2 in IBM8RF-DM 130nm CMOS process
Requested Date of Fabrication: Nov 7th, 2011
Requested Date of Design Submission: Nov 7th, 2011
Project Description
With the increasing demands on the biomedical electronics, the development of high-performance
integrated circuits with low power consumption has attracted great attention in recent years. Being a
crucial building block in a communication system, the phase-locked loop (PLL) is recognized as one of
the most power-consuming components. It is desirable to implement the PLL circuit for minimum power
consumption while maintaining the desirable performance such as the phase noise and output power to
satisfy the system specifications.
Traditional PLLs are based on mixed signal circuits and are usually called mixed signal PLLs. The
scaling down of lithographic feature size and supply voltage, together with implementing systems-on-chip
with large digital cores is making the design of high performance mixed-signal PLLs increasingly
difficult. All-digital phase locked loops (ADPLLs) working with all digital signals have been investigated
recently because it is easier to port into a different process technology. ADPLLs can also be designed
with shorter lock time than the analog charge-pump PLL (CPPLL). Fig.1 shows the block diagram of the
ADPLL, where the time to digital converter (TDC), the digital loop filter (DLF), and the DCO correspond
to the CP circuit, the RC loop filter, and the VCO of the analog CPPLL, respectively.
Frequency
Referece
Phase Frequency
Detector (PFD)
Time to
Digital
Convertor
(TDC)
Digital Loop
Filter (DLF)
Tuning
Word
Digital - Controlled
Oscillator (DCO)
Frequency
Divider(FD)
Fig.1 Block diagram of a all digital PLL
In this design, we’re targeted for the 0.7V supply voltage for the PLL system whose looking range is from
10 to 500MHz. This range is sufficient for many biomedical applications, especially for our application
working in the Medical Implant Communication Services (MICS) band.
For the DCO block in this PLL, a low voltage Schmitt-trigger-based relaxation oscillator and a low
voltage 14-bit R/2R ladder DAC have been combined together and used to reduce the power requirement.
The simplified circuit schematic of the R/2R current DAC is represented in Fig. 2(a). It consists of two
different R/2R ladders implementing the coarse and the fine banks, connected to the pMOS transistor M1
and an opamp. The opamp, consisting of a differential pair, connects both the ladders in feedback in order
to improve the linearity of the drain current IDAC of M1. A scaled copy of IDAC is delivered to the
relaxation oscillator by means of transistor M2. In order to save power during the idle state, the enable
switches are open and M1 goes to the cut-off region due to the large load resistance. Therefore, the DAC
power consumption is only determined by the opamp current. However, due to the low output capacitance
at node A, the required current to ensure the closed-loop stability is also low. RCOMP and CCOMP are used
for Miller compensation of the feedback loop comprising M1 and the opamp.
Fig.2 (a) Schematic of the DAC and (b) its equivalent circuit
Fig. 2(b) shows the current DAC equivalent circuit. The two R/2R ladders can be represented as the
parallel of two digitally tunable voltage sources Vcoarse and Vfine in series with fixed coarse and fine
resistances Rc and Rf. The voltage at node A is fixed to the reference voltage Vref by the feedback.
Fig. 3 Oscillator using Schmitt trigger and current sources
An oscillator using the Schmitt trigger is shown in Fig. 3. In the schematic MOSFETs Ma and Md behave
as current sources mirroring the current in Me and M2 (M2 is the same MOSFET in Fig. 2). When the
output of the oscillator is low, Mc is on and Mb is off. This allows the constant current from Md to charge
C. When the voltage across C reaches VSPH, the output of the Schmitt trigger swings low. This causes the
output of the oscillator to go high and allows the constant current from M a to discharge C. When C is
discharged down to VSPL, the Schmitt trigger changes states. This series of events continues, generating
the square wave output.
Chip Layout
The chip layout is shown below in Fig. 4, which occupies about 4mm x 4mm silicon area.
Fig. 4 Chip layout.
Test Results
The oscillating frequency of the DCO is designed to cover 10MHz to 500MHz. Fig. 5 shows the power
spectrum of output at 500MHz.
Fig. 5 DCO output spectrum at 500MHz.
The phase noise of the DCO is relatively high, compared with an LC oscillator. With 500MHz oscillating
frequency, the phase noise value at 1KHz offset is -40 dBc/Hz and -90 dBc/Hz at 100 MHz frequency
offset.
Fig. 6 Phase noise performance of the oscillator.
Fabrication Process
The IBM 130nm 8RF-DM CMOS process offered through MOSIS is ideal for developing the proposed
circuits.
Estimated Project Size
The estimated chip area is 4 mm x 4 mm or 16 mm2.
Packaging Requirements
We would like the chip to be packaged using OCP_LQFP64A through MOSIS.
Fabrication Schedule
We would like to request an area of 16 mm2 for the IBM 8RF-DM CMOS process run scheduled on
Nov.7 , 2010.
Simulation and Layout Plans
The circuit has been simulated using Cadence Spectre. Layout is done using Cadence Virtuoso. DRC,
extraction and LVS will be performed using Calibre. The extracted netlist will be simulated and compared
with the simulation results from the schematic netlist.
Test Plans
The fabricated chip will be tested in the Integrated Silicon Systems Laboratory of The University of
Tennessee, Knoxville. For board level testing, the die will be packaged and a FR4 PC board will be used
to test the functionality of the circuit.
References
[1] Salvatore Drago, Domine M. W. Leenaerts, Bram Nauta, Fabio Sebastiano, Kofi A. A. Makinwa, and
Lucien J. Breems, “A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS”, IEEE
Journal of Solid-State Circuits, vol. 45, no. 7, July 2010.
[2] R. Jacob Baker, “CMOS Circuit Design, Lauout and Simulation”, Wiley-Interscience 2008