Evaluation Board User Guide
UG-068
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Setting Up the Evaluation Board for the ADCLK948
PACKAGE LIST
The data sheet contains full technical details about the specifications and operation of this device.
Evaluation board with ADCLK948 component installed
Applicable documents (schematic, layout)
GENERAL DESCRIPTION
This user guide describes how to set up and use the evaluation
board for the ADCLK948. The ADCLK948 data sheet should be
used in conjunction with this user guide.
The ADCLK948 is a very high performance clock fanout buffer.
The evaluation board is fabricated using a high quality Rogers
dielectric material. Transmission line paths are kept as close to
50 Ω as possible.
08667-101
DIGITAL PICTURE OF EVALUATION BOARD
Figure 1. ADCLK948 Evaluation Board
Please see the last page for an important warning and disclaimers.
Rev. 0 | Page 1 of 8
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Evaluation Board User Guide
TABLE OF CONTENTS
Package List ....................................................................................... 1
Recommended Board Setup ........................................................3
General Description ......................................................................... 1
Clock Outputs ................................................................................4
Digital Picture of Evaluation Board ............................................... 1
Evaluation Board Schematic and Artwork.....................................5
Revision History ............................................................................... 2
ESD Caution...................................................................................8
Evaluation Board Hardware ............................................................ 3
REVISION HISTORY
11/09—Revision 0: Initial Version
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Evaluation Board User Guide
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EVALUATION BOARD HARDWARE
common-mode voltage for both inputs is provided by tying
VREF1 and VT1 together. This connection is made with R14
installed at the factory.
RECOMMENDED BOARD SETUP
The recommended setup for the ADCLK948 evaluation board
is shown in Figure 2. VCC is set to 3.3 V and VEE is set to GND.
The CLKSEL jumper (P2) is provided to select the desired input
configuration.
The range of the peak-to-peak input voltage swing at CLK1 is
0.2 V p-p to 1.7 V p-p. Note that output jitter performance is
degraded by an input slew rate, as shown in the data sheet.
On the evaluation board, Input CLK0 and Input CLK0 are set
up for dc-coupled operation to the ADCLK948 via J2 and J4.
This input configuration requires the user to provide the
appropriate ac swing and common-mode voltage to both
inputs. Refer to the ADCLK948 data sheet for input
specifications.
Table 1. Basic Equipment Required
Quantity
1
1
1
1
4
CLK1 is set up to evaluate with a single-ended source via the
balun on the evaluation board. In addition, series capacitors in
the path provide ac-coupled inputs to the ADCLK948. The
Description
Single power supply
Signal source
High bandwidth oscilloscope
High bandwidth Differential Probe (Optional)
Matched high speed cables
POWER SUPPLY
+3.3V
GND
VCC
VEE
CH 1
CLK1
CLK1
Qx
ADCLK948
EVALUATION
BOARD
OSCILLOSCOPE
CLK0
Qx
CH 2
CLK0
VREF 1
VT1
VREF 0
VT0
Figure 2. Recommended Setup for Device Evaluation
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CLOCK
SOURCE
GND
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Evaluation Board User Guide
CLOCK OUTPUTS
Table 2. Power Connections via P1
The ADCLK948 has eight differential outputs. Four of the
differential clock outputs on the evaluation board are biased to
GND via 200 Ω and ac-coupled to the SMAs. From the SMAs,
use matched 50 Ω coaxial cables into the oscilloscope for
evaluation. The other four differential outputs on the evaluation
board are not launched. Use a high bandwidth differential
probe and oscilloscope close to the ADCLK948 device for
evaluation. See the evaluation board schematic in Figure 4 for
more details.
Label
GND
VCC
VEE
ADCLK948
Connect to GND
Connect to 3.3 V
Connect to GND
LVPECL
ADCLK948
Q0
Q0
Q1
Q1
Q2
Q2
Q3
VREF 0
REFERENCE
Q3
Q4
VT0
Q4
CLK0
CLK0
Q5
VT1
Q5
CLK1
Q6
CLK1
Q6
Q7
IN_SEL
REFERENCE
Figure 3. ADCLK948 1:8 Clock/Data Buffer Block Diagram
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08667-001
VREF 1
Q7
LABEL CLK1B
LABEL CLK1
LABEL CLK0B
CLK0
GND
J3
J1
GND
CLK1B
CLK1
GND
J2
CLK0B
GND
LABEL CLK0
GND
0
OUT0B
C2
1 2
T2
GND
R10
100
LABEL "OUTPUT 7"
GND
J6
GND
J5
GND
LABEL "OUTPUT 7B"
1
2
R09 0
DNI
4
3
MABA-007159-000000
1
SEC
5
PRI
1
2
R08 0
DNI
OUT7
OUT7B
0.1UF
DNI
R52
49.9
DNI
R51
49.9
0.1UF
C4
1 2
DNI
R68
0.1UF
C3
1 2
DNI
R67
VEE
0
0
1
2
3
VREF0
4
VT0
5
6
7
VT1
VREF1 8
VEE
VEE
VCC
50 OHMS
50 OHMS
VEE
VCC
VEE
VCC
VEE
VEE
VCC
VEE
0
C12
1 2
0.1UF
0
0.1UF
DNI
R62
0
OHMS
OHMS
OHMS
OHMS
OHMS
TP12
DNI
1
OUT6B
LABEL "OUTPUT 6B"
R30
49.9
R29
49.9
50 OHMS
TP11
DNI
1 LABEL "OUTPUT 6"
OUT6
50 OHMS
50 OHMS
50
50
50
50
50
0.1UF
C7
OUT1B
49.9
49.9
0
R15
R28
OUT1 OUT1B
TP9 TP10
DNI
DNI
1
1
DNI
R64
0.1UF
C6
DNI
R63
C11
DNI
R61
24
Q2
23
CLK0
Q2B
22
CLK0B
Q3
U1
21
VREF0
Q3B
20
VT0 ADCLK948_PRELIM
Q4
19
CLK1
Q4B
18
CLK1B
Q5
17
VT1
Q5B
VREF1
INSEL
VCC
CLKSEL
50 OHMS
VEE
50 OHMS
C03 50 OHMS
0.1UF
C04
1 2
1 2
50 OHMS
50 OHMS
P2
1
2
3
0.1UF
LABEL "CLKSEL CONNECTS (CLKSEL)"
LABEL "VEE CONNECTS (CLK0)"
LABEL "VCC CONNECTS (CLK1)"
GND
J7
DNI
R50
49.9
DNI
R66 0
VEE
R1
R2
GND
200
200
LABEL "OUTPUT 0"
1
J4
R07
R11
2
49.9
DNI
R12
50 OHMS
R19
49.9
200
DNI 0.1UF
R49
49.9
50 OHMS
50 OHMS
200R7
R9 200
R18
PAD
32
31
30
29
28
27
26
25
VEE
VEE
VEE
VEE
VEE
VEE
DNI 4 3 2
R55
49.9
GND
0.1UF
0.1UF
C14
0
0
0.1UF
C18
1 2
DNI
R60
0.1UF
C17
DNI
R59
DNI
R69 0
0.1UF
C13
0
0.1UF
C16
1 2
DNI
R58
DNI
R70 0
0
0.1UF
C15
1 2
DNI
R57
0.1UF
C9
DNI
TP7
R43
DNI
R54
49.9
VCC
GND
GND
4 3 2
R45
R46
VT0
1
VREF1
DNI
TP2
VREF1
1
VT1
DNI
TP4
VEE
GND
GND
BYPASS CAPACITORS (SUPPLY)
VCC
VEE
VREF0
VT1
1
VT0
TP3
R47
R48
BYPASS CAPACITORS
VT1
VREF0 VREF1
VT0
LABEL "OUTPUT 5B"
LABEL "OUTPUT 5"
LABEL "OUTPUT 4B"
4 3 2
J11
1
J12
OUT5B1
OUT5
DNI
R53
49.9
R44
BYPASS CAPACITORS (DUT)
VEE
LABEL "OUTPUT 4"
DNI
TP8
R17
1
49.9
OUT4B
R16
49.9
1
OUT4
Z5.531.3425.0
ORDER WEILAND 25.600.5453.0 PLU
LABEL "VCC"
LABEL "GND"
LABEL "VEE"
STITCHING RESISTORS (O OHM)
GND
DNI
TP5
GND
LABEL "OUTPUT 3"VEE
1
OUT3
DNI
TP1
R25
49.9
DNI
1
TP6
VREF0
LABEL "OUTPUT 3B"
R27
49.9 1
OUT3B
4 3 2
DNI
R56
49.9 J10 LABEL "OUTPUT 2B"
OUT2B1
POWER
P1
C8
LABEL "OUTPUT 2"
J9
OUT2 1
DNI
R71 0
DNI
R72 0
VEE
R26
VEE
R21
200
0
R3
R4
R20
200
EPAD
IN_SEL
VCC_6
Q0
Q0B
Q1
Q1B
VCC_5
VCC_4
NC
VCC_1
Q7B
Q7
Q6B
Q6
VCC_2
VCC_3
9
10
11
12
13
14
15
16
200
R24
200
R8
200
R22
VCC
GND
C31
200
200
200
200
C34
C1
1 2
200
200
C32
VEE
C36
R23
1
2
3
4
VEE
0.1UF
DNI
R13
2
0
1
0.1UF
C35
2
R14
1
10UF
C33
0.1UF
C38
OUT0
0.1UF
LABEL "OUTPUT 0B"
08667-004
DNI
R65
0.1UF
0
R5
0
200
0
0
0.1UF
C37
C5
0.1UF
C41
10UF
0.1UF
C39
10UF
0
Rev. 0 | Page 5 of 8
R6
0.1UF
C40
0
Figure 4. ADCLK948 Evaluation Board Schematic
0.1UF
C42
0
J8
Evaluation Board User Guide
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EVALUATION BOARD SCHEMATIC AND ARTWORK
Evaluation Board User Guide
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Figure 5. Top Trace Layer
Figure 6. Ground Plane Layer
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Figure 7. VCC and VEE Power Plane Layer
Figure 8. Bottom Trace Layer
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Evaluation Board User Guide
NOTES
ESD CAUTION
Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express,
implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under
any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the
right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not
authorized to be used in life support devices or systems.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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