Evaluation Board User Guide
UG-067
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Setting Up the Evaluation Board for the ADCLK950
PACKAGE LIST
The data sheet contains full technical details about the specifications and operation of this device.
Evaluation board with ADCLK950 component installed
Applicable documents (schematic, layout)
GENERAL DESCRIPTION
This user guide describes how to set up and use the evaluation
board for the ADCLK950. The ADCLK950 data sheet should be
used in conjunction with this user guide.
The ADCLK950 is a very high performance clock fanout buffer.
The evaluation board is fabricated using a high quality Rogers
dielectric material. Transmission line paths are kept as close to
50 Ω as possible.
08666-101
DIGITAL PICTURE OF EVALUATION BOARD
Figure 1. ADCLK950 Evaluation Board
Please see the last page for an important warning and disclaimers.
Rev. 0 | Page 1 of 8
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Evaluation Board User Guide
TABLE OF CONTENTS
Package List ....................................................................................... 1
Recommended Board Setup ........................................................3
General Description ......................................................................... 1
Clock Outputs ................................................................................4
Digital Picture of Evaluation Board ............................................... 1
Evaluation Board Schematic and Artwork.....................................5
Revision History ............................................................................... 2
ESD Caution...................................................................................8
Evaluation Board Hardware ............................................................ 3
REVISION HISTORY
11/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
Evaluation Board User Guide
UG-067
EVALUATION BOARD HARDWARE
VREF1 and VT1 together. This connection is made with R14
installed at the factory.
RECOMMENDED BOARD SETUP
The recommended setup for the ADCLK950 evaluation board
is shown in Figure 2. VCC is set to 3.3 V and VEE is set to GND.
The CLKSEL jumper (P2) is provided to select the desired input
configuration.
The range of the peak-to-peak input voltage swing at CLK1 is
0.2 V p-p to 1.7 V p-p. Note that output jitter performance is
degraded by an input slew rate, as shown in the data sheet.
On the evaluation board, Input CLK0 and Input CLK0 are set
up for dc-coupled operation to the ADCLK950 via J2 and J4.
This input configuration requires the user to provide the
appropriate ac swing and common-mode voltage to both inputs.
Refer to the ADCLK950 data sheet for input specifications.
Table 1. Basic Equipment Required
Quantity
1
1
1
1
4
CLK1 is set up to evaluate with a single-ended source via the
balun on the evaluation board. In addition, series capacitors in
the path provide ac-coupled inputs to the ADCLK950. The
common-mode voltage for both inputs is provided by tying
Description
Single power supply
Signal source
High bandwidth oscilloscope
High bandwidth differential probe (optional)
Matched high speed cables
POWER SUPPLY
+3.3V
GND
VCC
VEE
CH 1
CLK1
CLK1
Qx
ADCLK950
EVALUATION
BOARD
OSCILLOSCOPE
CLK0
Qx
CH 2
CLK0
VREF 1
VT1
VREF 0
VT0
Figure 2. Recommended Setup for Device Evaluation
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CLOCK
SOURCE
GND
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Evaluation Board User Guide
CLOCK OUTPUTS
Table 2. Power Connections via P1
The ADCLK950 has 10 differential outputs. The five even-ordered
differential clock outputs on the evaluation board are biased to
GND via 200 Ω and ac-coupled to the SMAs. From the SMAs,
use matched 50 Ω coaxial cables into the oscilloscope for
evaluation. The five odd-ordered differential outputs on the
evaluation board are not launched. Use a high bandwidth
differential probe and oscilloscope close to the ADCLK950
device for evaluation. See the evaluation board schematic in
Figure 4 for more details.
Label
GND
VCC
VEE
ADCLK950
Connect to GND
Connect to 3.3 V
Connect to GND
LVPECL
ADCLK950
Q0
Q0
Q1
Q1
Q2
Q2
Q3
VREF 0
REFERENCE
Q3
Q4
VT0
Q4
CLK0
CLK0
Q5
VT1
Q5
CLK1
Q6
CLK1
Q6
Q7
IN_SEL
VREF 1
Q7
REFERENCE
Q8
Q8
Q9
Figure 3. ADCLK950 1:10 Clock/Data Buffer Block Diagram
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Q9
GND
GND
GND
CLK0
J3
J2
CLK0B
J1
GND
100 OHMS => DIFFERENTIAL
50 OHMS => SINGLE ENDED
142-0761-861
CLK1B
142-0761-861
CLK1
142-0761-861
CLK0B
142-0761-861
CLK0
J4
0
GND
R07
0
R09
DNI
2
142-0761-861
142-0761-861
1
J6
J5
3
4
MABA-007159-000000
GND
OUT8B
GND
GND
OUT8
1
T2
SEC
2
5
0
PRI
1
DNI
R08
50 OHMS
50 OHMS
142-0761-861
J7
2
.1UF
C2
R11
GND
C3
2
1
2
.1UF
C4
.1UF
1
GND
2
2
.1UF
1
.1UF
1
CLK1B
CLK1
OUT8
OUT8B
C04
C03
LABEL "VEE (CLK0)"
CLKSEL
LABEL "VCC (CLK1)"
VEE
2
VEE
R8
VEE
1
100
OUT9
1
1
50 OHMS
R9
100
VEE
1
1
VEE
100
VEE
2
1
OUT3
R16
VEE
VCC
1
1
GND
GND_03
OUT3B
50 OHMS
OUT2B
2
VEE
VEE
VEE
1
100
R15
VEE
2
1
OUT7
1
OUT7B
VEE
VEE
GND_07
GND
1
1 R17 2
50 OHMS
50 OHMS
VCC Q0
VCC
Q1
Q3
Q2
CLK_SEL Q0B Q1B Q2B Q3B VCC30 VCC
NC 29
CLK0
NC 28 R39 200 VEE C27 .1UF
CLK0B
Q4 27
VREF0
Q4B 26 100 OHMS
ADCLK950
VT0
Q5 25
CLK1
CP-40-8
R40 200 VEE C28 .1UF
CLK1B
Q5B 24
VT1
NC 23
DNI
DNI
VREF1
NC 22
R41 200 VEE C29 .1UF
VEE
VCC 21
Q9B Q8B
Q7B Q6B
VCC Q9
Q8
Q7
Q6 VCC
100 OHMS
VCC
VCC
VEE C30 .1UF
VCC
R42 200
DNI
DNI
1
2
3
VREF0 4
5
VT0
6
7
8
VT1
VREF1 9
VEE 10
U1
VEE VCC
1
OUT1B
VEE
VEE
R5
R6
R1
R2
OUT9B
VEE
VCC
1
OUT1
OUT0
1
GND
50 OHMS
GND_09
GND
1
50 OHMS
50 OHMS
1
2
3
P2
GND_01
50 OHMS
200
200
200
200
VEE
OUT2
OUT6B
OUT6
DNI
GND
GND
2
N0_C02
N0_C03
.1UF
C10 J10
1 2
J9
N0_C01
OUT4B
OUT4
GND_04
C9
.1UF
1
DNI
VEE
.1UF
C12
1 2
.1UF
C11
1 2
VEE
50 OHMS
50 OHMS
50 OHMS
142-0761-861
142-0761-861
DNI
GND
OUT2B
GND
OUT2
GND
OUT6B
GND
OUT6
VEE
OUT5B
OUT5
J12
142-0761-861
J11
142-0761-861
50 OHMS
VEE
R23
50 OHMS
.1UF
C18
1 2
.1UF
C17
1 2
.1UF
DNI
C16
1 2
.1UF
DNI
C15
1 2
GND
J16
142-0761-861
J15
142-0761-861
DNI
J14
142-0761-861
OUT5B
GND
OUT5
GND
GND
DNI
J13
142-0761-861
R43
R44
R45
VT0
VEE
VCC
VREF0
VT1
VREF1
VEE
GND
VEE
BYPASS CAPACITORS
VT0
VT1
GND
BYPASS CAPACITORS (SUPPLY)
VEE
VCC
BYPASS CAPACITORS (DUT)
VEE
R46
TP4
1 WHT
VT0
R48
R47
ORDER WEILAND 25.600.5453.0 PLUG
SAME AS ADCLK954 ENGR BRD
STITCHING RESISTORS (O OHM)
GND
LABEL "VCC (3.3V)"
LABEL "VEE (GND)"
POWER
P1
C31
C32
1
200 R7
Z5.531.3425.0
C34
C33
GND
49.9
.1UF
10UF
OUT0B
100
VEE
2
.1UF
2
1
100
DNI
R10
R12
.1UF C21
R32
200
R31
200
.1UF C19
R34
200
C23
.1UF
R14
50 OHMS
100 OHMS
R3
C20
.1UF
200
49.9
.1UF C26
R38
200
R21
R22
.1UF C22
100 OHMS
100
1 R18 2
2
200
200
.1UF
10UF
J8C1
1 2
DNI
R13
1
2
3
4
VCC
GND
0
.1UF C25
R36
200
.1UF C24
200
C35
C5
C36
PAD
40
39
38 200 R33
37
36 100 OHMS
35
34 200 R35
33
200 R37
32
31
100 OHMS
R20
11
12
13
14
15
16
17
18
19
20
R4
Figure 4. ADCLK950 Evaluation Board Schematic
200
1
200
1
R19
1
200
Rev. 0 | Page 5 of 8
R24
1
200
C39
OUT0B
.1UF
C38
0
1
.1UF
C37
10UF
0
0
0
1
.1UF
TP5
1 WHT
VT1
.1UF
C41
VREF0
.1UF
C40
.1UF
C42
0
1
VREF1
.1UF
.1UF
0
1
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0
142-0761-861
Evaluation Board User Guide
UG-067
EVALUATION BOARD SCHEMATIC AND ARTWORK
Evaluation Board User Guide
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08666-006
Figure 5. Top Trace Layer
Figure 6. Ground Plane Layer
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Evaluation Board User Guide
08666-008
Figure 7. VCC and VEE Power Plane Layer
Figure 8. Bottom Trace Layer
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Evaluation Board User Guide
NOTES
ESD CAUTION
Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express,
implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under
any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the
right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not
authorized to be used in life support devices or systems.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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