Evaluation Board User Guide
UG-006
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Setting Up the Evaluation Board for the ADCLK905/ADCLK907/ADCLK925
The data sheet contains full technical details about the specifications and operation of these devices.
PACKAGE LIST
Evaluation board with component installed
Applicable documents (schematic, layout, and so on)
GENERAL DESCRIPTION
This user guide describes how to set up and use the evaluation
board for the ADCLK905/ADCLK907/ADCLK925. The same
printed circuit board (PCB) is used to evaluate all three devices.
The ADCLK905/ADCLK907/ADCLK925 data sheet should be
used in conjunction with this user guide.
The ADCLK905/ADCLK907/ADCLK925 clock buffers are
very fast, making it important to use adequate high bandwidth
instruments to evaluate them. To that end, the evaluation board
is fabricated using a high quality dielectric material between
layers to maintain high signal integrity. Transmission line paths
are kept as close to 50 Ω as possible.
08182-001
DIGITAL PICTURE OF THE EVALUATION BOARD
Figure 1. ADCLK905/ADCLK907/ADCLK925 Evaluation Board
Please see the last page for an important warning and disclaimers.
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Evaluation Board User Guide
TABLE OF CONTENTS
Package List ....................................................................................... 1 Recommended Board Setup ........................................................3 General Description ......................................................................... 1 Clock Input Configuration ..........................................................4 Digital Picture of the Evaluation Board ........................................ 1 Evaluation Board Schematics and Artwork ...............................5 Revision History ............................................................................... 2 ESD Caution...................................................................................7 REVISION HISTORY
9/09—Revision 0: Initial Version
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RECOMMENDED BOARD SETUP
The recommended setup for the evaluation board is shown
in Figure 2. Note that there is no LVPECL output termination
on the evaluation board. LVPECL termination is accomplished
via the 50 Ω input of the oscilloscope. To meet the standard
LVPECL output termination (VCC − 2 V into 50 Ω), VCC is set
to 2 V and VEE is set to −1.3 V. This also meets the requirement
for VCC − VEE = 3.3 V.
Table 1. Basic Equipment Required
Quantity
1
1
1
4
Description
Dual power supply
Signal source
High bandwidth oscilloscope
Matched high speed cables
DUAL
POWER SUPPLY
+2.0V
VCC
COM
–1.3V
GND
VEE
OSCILLOSCOPE
Dx
CLOCK
SOURCE
Dx
ADCLK9xx
EVALUATION
BOARD
Qx
50Ω
Qx
50Ω
VREF x
V Tx
NOTES
1. FOR DC-COUPLED INPUTS, DISCONNECT VREF x AND V Tx.
2. FOR AC-COUPLED INPUTS, CONNECT VREF x AND VTx.
Figure 2. Recommended Setup for Device Evaluation
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08182-002
OPTIONAL AC OR
DC COUPLING
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Evaluation Board User Guide
CLOCK INPUT CONFIGURATION
It is recommended that the clock source be ac-coupled and
that VREFx and VTx be tied together. For single-ended operation,
ac-couple the unused input to ground with a 0.1 μF capacitor.
For more information about input configurations, refer to the
data sheet for the ADCLK905/ADCLK907/ADCLK925.
Figure 3 to Figure 5 show block diagrams for the three devices.
VREF 1
V T1
VCC
Q1
D1
Q1
D1
VEE
VEE
Q2
D2
Q2
D2
VCC
V T2
08182-004
The clock inputs of the ADCLK905/ADCLK907/ADCLK925
on the evaluation board are dc-coupled to the SMA connectors.
Therefore, the user must ac-couple the clock source, or the
clock source must supply the appropriate dc common-mode
voltage with adequate input swing.
VREF 2
VREF
Figure 4. ADCLK907 Dual 1:1 Clock/Data Buffer
VCC
VT
D
Q
VREF
D
Q
VT
VCC
Q1
D
Q2
Figure 3. ADCLK905 1:1 Clock/Data Buffer
Q2
VEE
08182-005
VEE
08182-003
Q1
D
Figure 5. ADCLK925 1:2 Clock/Data Fanout Buffer
Table 2. Jumper Connections
Jumper
TP1 (GND)
TP2 (VCC)
TP3 (VEE)
TP4 (GND)
TP5 (VREF1)
TP6 (VT1)
TP7 (VT2)
TP8 (VREF2)
ADCLK905/ADCLK925
Connect to GND
Connect to 2.0 V
Connect to −1.3 V
Connect to GND
Short T5 and T6 for input ac coupling, else no connection
Short T5 and T6 for input ac coupling, else no connection
No connection
No connection
Rev. 0 | Page 4 of 8
ADCLK907
Connect to GND
Connect to 2.0 V
Connect to −1.3 V
Connect to GND
Short T5 and T6 for input ac coupling, else no connection
Short T5 and T6 for input ac coupling, else no connection
Short T7 and T8 for input ac coupling, else no connection
Short T7 and T8 for input ac coupling, else no connection
AP LA NE
D2
J1
A PLANE
BLACK
TP3
V EE
ORANGE
2.2uF
TP4
C24
GND
0.1uF
AP LANE
D2
0.1uF
C22
0.1uF
C23
C27
A PLANE
J10
J7
AP LA NE
AP LANE
CAL_2
matched lengths
C21
0 Ohm resistors are NOT to be installed.
Solder bridges will be completed
by end user if desired.
A PLANE
0.1uF
C20
4
3
LFCSP16-3X3
ADCLK9xx
AP LA NE
0.01uF
C45
0.01uF
C44
matched length x2
D2
D2
D1
0.1uF
C11
0
C12
R1
16
V T1
V T2
0
2
C25
D1
0.1uF
C18
C9
C10
0.1uF
VREF 2
6
C26
0.1uF
5
R2
C15
15
VREF 1
13
VCC
0.1uF
VEE
7
9
Q2
Q2
PAD
10
Q1
VEE
11
C2
14
0.1uF
C14
2.2uF
12
0.1uF
0.1uF
VCC
C13
0.1uF
VEE
C8
8
0.1uF
C1
0.1uF
Q1
C16
0.1uF
A PLANE
AP LA NE
J9
matched lengths
C3
D1
0.1uF
1
0.1uF
C4
J2
C5
J8
0.1uF
C19
D1
0.1uF
AP LA NE
Q2
A PLA NE
J3
Q2
AP LA NE
J6
Q1
A PLANE
A PLANE
V CC
TP2
RED
GND
BLACK
AP LANE
TP1
Jumpers are NOT to be installed.
Solder bridges will be completed
by end user if desired.
V T2
A PLA NE
J4
C6
J5
J12
Q1
JP1
JP4
JP3
JP2
A PLANE
0.1uF
C38
A PLANE
0.1uF
C41
AP LA NE
0.1uF
0.1uF
0.1uF
VREF1
V REF 2
AP LA NE
A PLA NE
C37
V T1
V REF 2
V T2
V T1
TP5
YELLOW
YELLOW
TP7
TP6
TP8
C36
V REF 1
0.1uF
matched length x2
C7
C39
C40
C28
C32
0.1uF
0.1uF
C29
0.1uF
C33
C42
C30
C34
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C43
C31
C35
WHITE
0.1uF
JP8
JP7
JP6
JP5
WHITE
0.1uF
0.1uF
CAL_1
0.1uF
Rev. 0 | Page 5 of 8
0.1uF
Figure 6. ADCLK905/ADCLK907/ADCLK925 Evaluation Board Schematic
V REF 1
08182-006
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EVALUATION BOARD SCHEMATICS AND ARTWORK
C17
08182-009
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08182-007
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08182-008
08182-010
Figure 9. VREF and VT Plane Layers
Figure 7. Top Trace Layer
Figure 8. Ground Plane Layer
Figure 10. VCC and VEE Power Plane Layer
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08182-011
08182-012
Evaluation Board User Guide
Figure 11. Second Ground Plane Layer
Figure 12. Bottom Trace Layer
ESD CAUTION
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NOTES
Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express,
implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under
any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the
right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not
authorized to be used in life support devices or systems.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
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