Evaluation Board User Guide
UG-200
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluating the AD9467 16-Bit, 200 MSPS/250 MSPS ADC
FEATURES
DOCUMENTS NEEDED
Full featured evaluation board for the AD9467
SPI and alternate clock options
Internal and external reference options
VisualAnalog and SPI Controller software interfaces
AD9467 data sheet
HSC-ADC-EVALCZ data sheet, High Speed Converter
Evaluation Platform (FPGA-based data capture kit)
AN-905 Application Note, VisualAnalog Converter Evaluation
Tool Version 1.0 User Manual
AN-878 Application Note, High Speed ADC SPI Control Software
AN-877 Application Note, Interface to High Speed ADCs via SPI
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
2 switching power supplies (6.0 V, 2.5 A) CUI EPS060250UHPHP-SZ, included
PC running Windows® 98 (2nd ed.), Windows 2000,
Windows ME, or Windows XP
USB 2.0 port, recommended (USB 1.1 compatible)
AD9467 evaluation board
HSC-ADC-EVALCZ FPGA-based data capture kit
SOFTWARE NEEDED
VisualAnalog
SPI Controller
GENERAL DESCRIPTION
This document describes the evaluation board for the AD9467,
which provides all of the support circuitry required to operate the
AD9467 in its various configurations. The application software
used to interface with the device is also described.
The AD9467 data sheet, available at www.analog.com, which
provides additional information, should be consulted when using
the evaluation board. All documents and software tools are
available at http://www.analog.com/fifo. For any questions,
send an email to highspeed.converters@analog.com.
09436-001
TYPICAL MEASUREMENT SETUP
Figure 1. AD9467-250EBZ Evaluation Board and HSC-ADC-EVALCZ Data Capture Board
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
Rev. 0 | Page 1 of 28
UG-200
Evaluation Board User Guide
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Signals...................................................................................3
Equipment Needed ........................................................................... 1
Output Signals ...............................................................................3
Documents Needed .......................................................................... 1
Default Operation and Jumper Selection Settings ....................5
Software Needed ............................................................................... 1
Evaluation Board Software Quick Start Procedures .....................6
General Description ......................................................................... 1
Configuring the Board .................................................................6
Typical Measurement Setup ............................................................ 1
Using the Software for Testing.....................................................6
Revision History ............................................................................... 2
Evaluation Board Schematics and Artwork ................................ 10
Evaluation Board Hardware ............................................................ 3
Ordering Information .................................................................... 25
Power Supplies .............................................................................. 3
Bill of Materials ........................................................................... 25
REVISION HISTORY
10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Evaluation Board User Guide
UG-200
EVALUATION BOARD HARDWARE
The AD9467 evaluation board provides all of the support
circuitry required to operate the AD9467 in its various modes
and configurations. Figure 2 shows the typical bench characterization setup used to evaluate the performance of the AD9467.
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<1 ps rms jitter) to realize the
optimum performance of the signal chain. Proper filtering of
the analog input signal to remove harmonics and lower the
integrated or broadband noise at the input is necessary to
achieve the specified noise performance (see the AD9467
data sheet).
See the Evaluation Board Software Quick Start Procedures
section to get started and Figure 17 to Figure 31 for the
complete schematics and layout diagrams that demonstrate
the routing and grounding techniques that should be applied
at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2.5 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The other end is a 2.1 mm inner diameter jack that
connects to the PCB at P700. Once on the PC board, the 6 V
supply is fused and conditioned before connecting to low dropout
linear regulators that supply the proper bias to each of the various
sections on the board.
When operating the evaluation board in a nondefault condition,
E704, E705, E706, E707 can be removed to disconnect the
switching power supply. This enables the user to bias each section
of the board individually. Use P700 and P701 to connect a different
supply for each section. At least one 1.8 V supply is needed with
a 1 A current capability for 1.8 V AVDD1 and 1.8 V DRVDD;
however, it is recommended that separate supplies be used for
both analog and digital domains. An additional supply is also
required to supply 3.3 V to the DUT, 3.3 V AVDD2. This should
also have a 1 A current capability. To operate the evaluation board
using the SPI and alternate clock and amplifier options, a separate
3.3 V analog supply is needed in addition to the other supplies.
The 3.3 V supply, or 3.3 V 3P3V_AVDD, should have a 1 A
current capability.
INPUT SIGNALS
When connecting the ADC clock and analog source, use clean
signal generators with low phase noise, such as Rohde & Schwarz
SMA or HP8644B signal generators or the equivalent. Use a 1 m
shielded, RG-58, 50 Ω coaxial cable for making connections to
the evaluation board. Enter the desired frequency and amplitude
(refer to the specifications in the AD9467 data sheet).
If a different or external ADC clock source is desired, follow the
instructions in the Clock Circuitry section or use the on-board
crystal oscillator, Y200. Typically, most Analog Devices, Inc.,
evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave
input for the clock. When connecting the analog input source,
it is recommended to use a multipole, narrow-band band-pass
filter with 50 Ω terminations. Analog Devices uses TTE and
K&L Microwave, Inc., band-pass filters. The filter should be
connected directly to the evaluation board.
OUTPUT SIGNALS
The default setup uses the FIFO5 high speed, dual-channel
FIFO data capture board (HSC-ADC-EVALCZ). For more
information on this board and its optional settings, visit
http://www.analog.com/fifo.
Rev. 0 | Page 3 of 28
UG-200
Evaluation Board User Guide
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
SWITCHING
POWER
SUPPLY
SWITCHING
POWER
SUPPLY
ANALOG INPUT
SIGNAL
SYNTHESIZER
PC
RUNNING ADC
ANALYZER
OR VisualAnalog
USER SOFTWARE
09436-002
CLOCK
INPUT
SIGNAL
SYNTHESIZER
Figure 2. Evaluation Board Connection
Rev. 0 | Page 4 of 28
Evaluation Board User Guide
UG-200
Clock Circuitry
DEFAULT OPERATION AND
JUMPER SELECTION SETTINGS
This section explains the default and optional settings or modes
allowed on the evaluation board for the AD9467.
Power Circuitry
Connect the switching power supply that is supplied in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P700.
Analog Input Front-End Circuit
The evaluation board is set up for single-ended analog input
connection with an optimum 50 Ω impedance match of
350 MHz of bandwidth. For a different bandwidth response,
the input network needs to be changed or modified.
XVREF
XVREF is set to 1.25 V. This causes the ADC to operate with
the default internal reference in the 2.5 V p-p full-scale range.
A separate external reference option using the ADR130 is also
included on the evaluation board. Populate R400 with a 0 Ω
resistor. Note that ADC full-scale ranges from 2.0 V p-p to
2.5 V p-p are supported by the AD9467.
The default clock input circuitry is derived from a simple
transformer-coupled circuit using a high bandwidth 1:1
impedance ratio transformer (T201) that adds a very low amount
of jitter to the clock path. The clock input is 50 Ω terminated
and ac-coupled to handle single-ended sine wave types of inputs.
The transformer converts the single-ended input to a differential
signal that is clipped before entering the ADC clock inputs.
The evaluation board can be set up to be clocked from the
crystal oscillator, Y200. This oscillator is a low phase noise
oscillator from Vectron (VCC6-QCD-250M000). If this clock
source is desired, install C205 and C206 and remove C202. Jumper
P200 is used to disable the oscillator from running.
A differential LVPECL or LVDS clock driver can also be used to
clock the ADC input using the AD9517 (U300). Populate C304,
C305, C306, and C307 with 0.1 µF capacitors for one drive option
or the other and remove C209 and C210 to disconnect the default
clock path inputs. The AD9517 has many SPI-selectable options
that are set to a default mode of operation. Consult the AD9517
data sheet for more information about these and other options.
Dx+, Dx−
If an alternative data capture method to the setup shown in
Figure 2 is used, optional receiver terminations, R500 to R509, can
be installed next to the high speed backplane connector, P502.
Rev. 0 | Page 5 of 28
UG-200
Evaluation Board User Guide
EVALUATION BOARD SOFTWARE QUICK START PROCEDURES
This section provides quick start procedures for using the AD9467,
either on the evaluation board or at the system level design.
Both the default and optional settings are described.
CONFIGURING THE BOARD
3.
4.
5.
6.
7.
Figure 3. VisualAnalog, New Canvas Dialog Box
2.
If a different program is desired, follow Step 3.
USING THE SOFTWARE FOR TESTING
Figure 4. VisualAnalog, New Canvas Message Box
Setting Up the ADC Data Capture
3.
After configuring the evaluation board, set up the ADC data
capture block using the following steps:
1.
After the template is selected, a message box opens, asking
if the default configuration can be used to program the
FPGA (see Figure 4). Click Yes, and the window closes.
09436-004
2.
Connect the evaluation board and the HSC-ADC-EVALCZ
as shown in Figure 1 and Figure 2.
Connect one 6 V, 2.5 A switching power supply (such as
the CUI, Inc., EPS060250UH-PHP-SZ included) to the
evaluation board.
Connect one 6 V, 2.5 A switching power supply (such as
the CUI EPS060250UH-PHP-SZ included) to the HSCADC-EVALCZ board.
Connect the USB cable to J6 on the HSC-ADC-EVALCZ
board to the PC.
On the evaluation board, place jumpers on all four pin
pairs of P600 to connect the SPI bus.
On the evaluation board, ensure that P200 is jumpered to
the off setting to use the on-board 250 MHz Vectron VCC6
oscillator.
On the evaluation board, use a clean signal generator with
low phase noise to provide an input signal to the desired
channel. Use a 1 m, shielded, RG-58, 50 Ω coaxial cable
to connect the signal generator. For best results, use a
narrow-band band-pass filter with 50 Ω terminations
and an appropriate center frequency. (Analog Devices
uses TTE, Allen Avionics, and K&L band-pass filters.)
Open VisualAnalog® on a PC. AD9467 should be listed in
the status bar of the New Canvas window. Select the
template that corresponds to the type of testing to be
performed (see Figure 3).
To view different channels or change features to settings
other than the default settings, click the Expand Display
button located on the top right corner of the VisualAnalog
window, as shown in Figure 5 and Figure 6.
This process is described in the AN-905 Application Note,
VisualAnalog Converter Evaluation Tool Version 1.0 User
Manual. Once you are finished, click the Collapse Display
button.
EXPAND DISPLAY BUTTON
Figure 5. VisualAnalog Window Toolbar, Expand Display Button
Rev. 0 | Page 6 of 28
09436-005
1.
09436-003
Before using the software for testing, configure the evaluation
board as follows:
Evaluation Board User Guide
UG-200
menu and select the appropriate configuration. Note that
the CHIP ID(1) field should be filled to indicate whether
the correct SPI Controller configuration file is loaded (see
Figure 8).
09436-006
COLLAPSE DISPLAY BUTTON
4.
Program the FPGA of the HSC-ADC-EVALCZ board to a
setting other than the default setting as described in Step 3.
Then expand the VisualAnalog display and click the Settings
button in the ADC Data Capture block (see Figure 6). The
ADC Data Capture Settings box opens (see Figure 7).
09436-008
Figure 6. VisualAnalog, Main Window Expanded Display
Figure 8. SPI Controller, CHIP ID(1) Box
2.
Click the New DUT button in the SPI Controller (see
Figure 9).
09436-007
NEW DUT BUTTON
Select the Capture Board tab and browse to the appropriate
programming file. Next, click Program; the DONE LED, D6,
in the HSC-ADC-EVALCZ board should then turn on.
6.
Exit the ADC Data Capture Settings box by clicking OK.
Setting Up the SPI Controller
After the ADC data capture board setup has been completed,
set up the SPI Controller:
1.
Figure 9. SPI Controller, New DUT Button
3.
Open the SPI Controller software by going to the Start
menu or double-clicking the SPI Controller software
desktop icon. If prompted for a configuration file, select
the appropriate one. If not, check the title bar at the top of
the SPI Controller window to determine which configuration is loaded. If necessary, choose Cfg Open from the File
Rev. 0 | Page 7 of 28
Click the Run button in the VisualAnalog toolbar (see
Figure 10).
RUN BUTTON
Figure 10. VisualAnalog Window Toolbar, Run Button
09436-010
5.
09436-009
Figure 7. ADC Data Capture Settings, Capture Board Tab
UG-200
Evaluation Board User Guide
Applying Input Signal and Optimizing SFDR
Apply the input signal as follows:
Apply the input signal so that the fundamental is at the
desired level (examine the Fund Power reading in the left
panel of the VisualAnalog FFT window). See Figure 11
and Figure 12.
09436-013
1.
Figure 13. Typical FFT, AD9467 (No Buffer Current Optimization)
09436-012
Figure 11. VisualAnalog, FFT Graph, No Signal or Very Low Signal Applied
Figure 12. VisualAnalog, FFT Graph, Full-Scale Signal Applied
Rev. 0 | Page 8 of 28
To optimize SFDR performance, use Register 36 and
Register 107 to change the buffer current setting. In the
ADCBase 0 tab of the SPI Controller, find the BUFFER(36)/
BUFFER(107) box. Use the drop-down list box to select
the best current, if necessary. See the AD9467 data sheet, the
AN-878 Application Note, and the AN-877 Application
Note for reference.
09436-014
09436-011
2.
Figure 14. SPI Controller, BUFFER(36)/BUFFER(107)
Figure 15. SPI Controller, SPI Controller, BUFFER(36)/BUFFER(107) DropDown Setting
Rev. 0 | Page 9 of 28
09436-016
UG-200
09436-015
Evaluation Board User Guide
Figure 16. Typical FFT, AD9467 (With Buffer Current Optimized)
3 4
AGND
2
5
1
SMA-J-P-X-ST-EM12
AIN
3
4
5
AGND
1
J101
DNI
SMA-J-P-X-ST-EM1
AIN
J100
3
4
5
AGND
AGND
51
R100
DNI
51
R101
DNI
L OR R
L OR R
0
R102
DNI
10NH
L105
DNI
C101
5
0.1UF
C103
0.1UF
DNI
0
DNI
1
C105
AGND
PRI
0
4
6
2
3
1
AGND
2
NC
DIFF_IN
UNBAL
ADT1-1WT+
T101
1
3
R132
0
SEC
3
4
6
4
2
T104
1
3
6
0
R134
0
B0310E5050A00
BAL_PORT1
8
T105
BAL_PORT2
OFF
ON
R133
AMP
ENABLE
ADT1-1WT+
9 10
AGND
5
GND
7
DC
MABA-007159-000000
T100
R131
4
AGND
30
AGND
0
R104
AGND
3
4
30
R106 0.1UF
DNI
0
SEC
PRI
MABA-007159-000000
1
5
R126
AGND
0
R129
C102
AGND
0.1UF
SMA-J-P-X-ST-EM1
2
1
J102
T103
R105 0.1UF
R125
0.1UF
0.1UF
0
2
3
1
P100
0
DNI
R108
0
R107
0
T102
DNI
AGND
0
R124
0
R123
AVDD_3P3V
R110
AGND
12
2
3
4
1
U100
ADL5562_PRELIM
1
5
GND
ENBL
VIP2
VIP1
VIN1
VIN2
VCC
AGND
VOP
VON
PAD
VCOM
AGND
13
14
15
16
MABA-007159-000000
DNI
3
4
5
6
7
8
PAD
R109
SEC
PRI
9
11
10
DNI
DNI
C108
0.1UF
C110
0.1UF
C107
5.6
5.6
R118
0.1UF
AGND
AGND
0.1UF
R117
C109
AGND
R116
0
R115
0
C111
C106
0.1UF
DNI
AGND
DNI
AMPOUT-
R114
0
DNI
R113
0
DNI
AMPOUT+
0.1UF
C114
DNI
0.1UF
C113
DNI
C115
DNI
15
R120
15
R119
R122 0.1UF
1.00K
DNI
R121
1.00K
120NH
L100
DNI
DNI
15NH
L102
DNI
DNI
36NH
L103
DNI
C119
100PF
36NH
DNI
AGND
L104
15NH
C117
L101
DNI
10UF
P
R111
N
33
33
R112
R103
TBD0201
TBD0201
AVDD_3P3V
DNI
C116
DNI
C112
ANALOG INPUT CIRCUITRY
R130
TBD0201
AGND
0
R128
0
R127
AGND
DNI
C120
39PF
AIN-
AIN+
AMPOUT-
AMPOUT+
09436-017
C100
C104
TBD0201
Rev. 0 | Page 10 of 28
C118
Figure 17. DUT Analog Input Circuits
TBD0201
UG-200
Evaluation Board User Guide
EVALUATION BOARD SCHEMATICS AND ARTWORK
1
DNI
OSC
ENABLE
AGND
51
R202
DNI
0.1UF
C203
DNI
0.1UF
C202
OPT_CLK_N
C204
OFF
ON
3
2
1
P200
AGND
C200
AGND
1
AGND
E_D
10UF
AVDD_3P3V
3
GND
VDD
6
FO
CFO
4
5
Y200
AGND
AGND
AGND
OPTIONAL OSCILLATOR
SMA-J-P-X-ST-EM1
AGND
2 3 4 5
1
J200
AGND
51
R203
P
N
CLK
SMA-J-P-X-ST-EM1
AGND
2 3 4 5
R200
10K
R201
10K
C201
CLK
J201
T200
MABA-007159-000000
3
4
1
SEC
4
PRI
5
1
2
ADT1-1WT+
3
6
T201
DNI
(DEFAULT)
DNI
0.1UF
C206
DNI
0.1UF
C205
OPT_CLK_N
OPT_CLK_P
CAP FOR BALUN, 0 OHM FOR XFORMER
AGND
R204
OPT_CLK_P
249
249
Rev. 0 | Page 11 of 28
R205
Figure 18. DUT Passive (Default) Clock Circuit
0.1UF
0.1UF
DNI
AGND
0.1UF
C208
0.1UF
C207
AGND
33
R207
DNI
33
R206
DNI
CR200
DNI
3
HSMS-2812BLK
1
2
CLOCK CIRCUITRY
C209
0.1UF
C210
0.1UF
DNI
R208
200
CLK-
CLK+
Evaluation Board User Guide
UG-200
09436-018
AGND
BYPASS_LDO
CP
R306
1.00K
AD9517_CSB
R305
1.00K
0
R310
R309
1.00K
R316
200
AGND
LF
C302
SCLK_USB
SDI_USB
0.1UF
C303 0.1UF
AVDD_3P3V
OPT_CLK_N
OPT_CLK_P
BYPASS_LDO
CHARGE PUMP FILTER
C308
TSW-104-08-T-D
R304
1.00K
1800PF
1
2
3
4
5
6
7
8
AVDD_3P3V
C309
J300
DNI
C301
0.1UF
R313
100
OPT_CLK_N
0.1UF
.033UF
DNI
C310
R312
0
R300
1.00K
VS_LVPECL
13
16
14
17
7
18
11
12
8
CS_N
SDIO
SCLK
0
R315
SYNC_N
RESET_N
PD_N
CLK_N
CLK
LF
9 BYPASS
48 REFIN_REF1
47 REFIN_N_REF2
6 REF_SEL
0.1UF
C300
1500PF
C312
AVDD_3P3V
LF
PAD
PAD
AGND
AGND
VS
41
42
5
4
2
44
1
46
U300
SDO
OUT3_N
OUT4_OUT4A
OUT4_N_OUT4B
OUT5_OUT5A
OUT5_N_OUT5B
OUT6_OUT6A
OUT6_N_OUT6B
OUT7_OUT7A
OUT7_N_OUT7B
OUT3
OUT2_N
OUT2
SDO_USB
CP
AD9517-4BCPZ
15
20
22
23
35
34
33
32
26
27
28
29
19
39
OUT1
38
OUT1_N
OUT0_N
OUT0
STATUS
CP
LD
REFMON
CPRSET
RSET
VCP
10
24
25
30
31
36
37
43
45
3
AVDD_3P3V
C311
21
40
1
2
3
CR300
AGND
AGND
DNI
DNI
LVDS
CLK-
CLK+
AGND
AGND
R308
249
AGND
0.1UF
C321
0.1UF
C322
0.1UF
0.1UF
C316
0.1UF
C317
0.1UF
AGND
0.1UF
C323
0.1UF
C320
0.1UF
C315
C318
0.1UF
C319
AVDD_3P3V
0.1UF
C314
C313
DECOUPLING
0.1UF
C307
0.1UF
C306
R307
249
A
C
LNJ314G8TR
A (GREEN)
AGND
4.12K
R301
P300
R311
100
249
R303
5.11K
R302
OPTIONAL CLOCK PATH CIRCUIT
DNI
OPT_CLK_P
DNI
Rev. 0 | Page 12 of 28
.22UF
Figure 19. DUT Active Clock Circuit
R314
0
DNI
DNI
0.1UF
C305
0.1UF
C304
CLK-
PECL
CLK+
UG-200
Evaluation Board User Guide
09436-019
C404
0.1UF
DRVDD_DUT
C403
0.1UF
AVDD2_DUT
C402
0.1UF
AVDD1_DUT
C401
0.1UF
AVDD1_DUT
C409
0.1UF
C408
0.1UF
C407
0.1UF
C406
0.1UF
C414
0.1UF
C413
0.1UF
C412
0.1UF
C411
0.1UF
AGND
C419
0.1UF
AGND
C418
0.1UF
C417
0.1UF
C416
0.1UF
C454
0.1UF
C450
0.1UF
C422
0.1UF
C421
0.1UF
C456
0.1UF
C452
0.1UF
C445
0.1UF
AGND
C427
0.1UF
C426
0.1UF
AGND
C428
0.1UF
AVDD1_DUT
C455
0.1UF
C451
0.1UF
AGND
C425
0.1UF
C424
0.1UF
C423
0.1UF
3 VIN
5 SET
GND
2
C430
0.1UF
AGND
VOUT 4
C447
0.1UF
C440
0.1UF
U400
ADR130AUJZ
C457
0.1UF
C453
0.1UF
C446
0.1UF
C439
0.1UF
AGND
C429
0.1UF
AGND
C431
0.1UF
0
R400
DNI
C448
0.1UF
C441
0.1UF
C432
0.1UF
C449
0.1UF
C442
0.1UF
C433
0.1UF
AVDD1_DUT
AIN-
AIN+
AVDD2_DUT
C437
0.1UF
C438
0.1UF
AGND
DUT1
AVDD1_DUT
1
TP401
AVDD1_DUT
DRVDD_DUT
72 PIN LFCSP
AD9447/AD9467
AGND
D0/1_C
D0/1_T
D2/3_C
D2/3_T
D4/5_C
D6/7_C
D4/5_T
D6/7_T
DCO_C
DCO_T
D8/9_C
D10/11_C
D8/9_T
D10/11_T
D12/13_C
D12/13_T
D14/15_C
D14/15_T
AD9467BCPZ-250_PRELIM
AGND
DUT CIRCUITRY
C444
0.1UF
C435
0.1UF
AVDD1_DUT
AGND
C434
0.1UF
C443
0.1UF
C436
C420
0.1UF
0.1UF
C415
0.1UF
1
C410
0.1UF
CLK+
C405
0.1UF
CSB_DUT
SCLK_DUT
SDIO_DUT
2
3
4
5
6
7
8
9
CLK-
DNI
OR_T
OR_C
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AVDD1
AVDD1
AVDD1
VDD3_SPI
CSB
SCLK
SDIO
VDD8_SPI
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
OR_T
OR_C
DRGND
DRVDD
AVDD1
AVDD1
AVDD1
AVDD1
ENC
ENC_
AVDD1
AVDD1
AVDD1
AVSS
AVDD1
AVDD1
DVDD
DVSS
AVDD1
AVSS
DRGND
DRVDD
10
11
12
13
14
15
16
17
18
PAD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Figure 20. DUT Circuitry
DRVDD_DUT
PAD
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
VIN_NEG
VIN_POS
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
REFERENCE
AVDD1
AVDD1
C400
0.1UF
D0_1_C
D0_1_T
D2_3_C
D2_3_T
D4_5_C
D4_5_T
D6_7_C
D6_7_T
DCO_
DCO
D8_9_C
D8_9_T
D10_11_C
D10_11_T
D12_13_C
D12_13_T
D14_15_C
D14_15_T
Rev. 0 | Page 13 of 28
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD1_DUT
Evaluation Board User Guide
UG-200
09436-020
UG-200
Evaluation Board User Guide
OPTIONAL TERMINATION
DCO_T
D0/1_T
D2/3_T
R500
DNI
100
R501
DNI
100
R502
DNI
DCO_C
D0/1_C
D2/3_C
100
R503
DNI
D6/7_T
100
R504
DNI
D6/7_C
D8/9_T
100
R505
DNI
D8/9_C
D10/11_T
100
R506
DNI
D10/11_C
D12/13_T
100
R507
DNI
D12/13_C
100
R508
DNI
100
R509
DNI
D4/5_T
D14/15_T
OR_T
D4/5_C
D14/15_C
OR_C
100
D4/5_C
D6/7_C
D8/9_C
P502
PLUG HEADER
AGND
Figure 21. Digital Output Interface
Rev. 0 | Page 14 of 28
FPGA_SDIO
FPGA_SCLK
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
AGND
SDO_USB
SDI_USB
SCLK_USB
P501
PLUG HEADER
P502
PLUG HEADER
C10
BG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
P501
DG1
6469169-1
P501
C1
C2
C3
C4
C5
C6
C7
C8
C9
D0/1_C
D2/3_C
D10/11_C
D12/13_C
D14/15_C
OR_C
P501
A10
PLUG HEADER
D1
D2
D3
D4
D5
D6
D7
D8
D9
P501
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
6469169-1
AGND
09436-021
AGND
FPGA_CSB
P502
PLUG HEADER
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
AD9517_CSB
CSB_USB
D10
P502
A1
A2
A3
A4
A5
A6
A7
A8
A9
DCO_C
PLUG HEADER
PLUG HEADER
PLUG HEADER
C10
PLUG HEADER
D10/11_T
D12/13_T
D14/15_T
OR_T
C1
C2
C3
C4
C5
C6
C7
C8
C9
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
A10
D0/1_T
D2/3_T
D4/5_T
D6/7_T
D8/9_T
P501
P502
PLUG HEADER
PLUG HEADER
A1
A2
A3
A4
A5
A6
A7
A8
A9
PLUG HEADER
P502
DCO_T
Evaluation Board User Guide
UG-200
SPI CIRCUITRY
AVDD1_DUT
C600
AGND
0.1UF
SDIO
R606
CSB
U600
5
1.00K
R603
0
VCC
SDO_USB
A1
3
A2
10K
Y1
R607
R604
6
Y2 4
0
1.00K
R608
GND
NC7WZ07P6X
2
SDI_USB
AVDD_3P3V
AGND
AGND
SDIO
0
SDIO_DUT
SCLK_USB
R605
1.00K
CSB_USB
R609
0
TSW-104-08-G-D
FPGA_CSB
DNI
FPGA_SDIO
DNI
AVDD1_DUT
C601
R610
AGND
0.1UF
U601
VCC
AVDD_3P3V
1
A1
3
A2
SCLK_DUT
Y1
6
SCLK
R611
R600
10K
Y2 4
10K
R601
FPGA_SCLK
CSB
0
GND
2
SCLK
0
5
DNI
NC7WZ16P6X
09436-022
8
7
6
5
4
3
2
1
R602
P600
1
CSB_DUT
AVDD1_DUT
AGND
Figure 22. SPI Interface Circuitry
Rev. 0 | Page 15 of 28
1
2
3
4
P701
Z5.531.3425.0
1
2
3
4
P700
Z5.531.3425.0
AGND
3P3V_AVDD
DUT_AVDD1
AGND
DUT_AVDD2
DUT_DRVDD
CONNECTIONS
OPTIONA L POWER
E701
E700
2
E702
2
45OHMS
1
2
2
45OHMS
1
45OHMS
1
E703
45OHMS
1
AGND
AGND
0.1UF
AGND
AGND
C706
C703
C701
C700
C702
C707
0.1UF
C705
0.1UF
C704
0.1UF
P
N
P
N
P
N
P
10UF
10UF
10UF
10UF
AVDD_3P3V
AVDD1_DUT
AVDD2_DUT
DRVDD_DUT
1 2
PWR_IN3
PWR_IN2
PWR_IN3
PWR_IN2
SH1
3
1K
R702
1K
R701
RAPC722X
C714
10UF
EN
OUT
OUT2
PAD
AGND
2 PAD
IN2
ADJ
GND1
IN
SENSE
5
6
EN
OUT
PAD
OUT2
AGND
2 PAD
IN2
ADJ
GND1
IN
SENSE
5
6
1 F700 2
2A
EN
OUT
PAD
OUT2
AGND
2 PAD
IN2
SS
GND1
IN
SENSE
5
6
1
7
3
4
8
OUT
PAD
OUT2
AGND
2 PAD
IN2
SS
GND1
IN
SENSE
EN
5
6
ADP1706ARDZ-1.8-R7
U703
1
7
3
4
8
ADP1706ARDZ-3.3-R7
U702
R704
750
1
7
3
4
8
U700
ADP1708ARDZ-R7
R703
348
1
7
3
4
8
U701
ADP1708ARDZ-R7
PGND
6VDC , 2A MAX
C710
P
N
J700
C709
C708
C718
N
SIG
SH2
4.7UF
4.7UF
4.7UF
C713
4.7UF
C719
C716
C715
E704
2
2
E706
2
E707
2
45OHMS
1
3
FL700
BNX016-01
DUT_DRVDD
3P3V_AVDD
DUT_AVDD1
DUT_AVDD2
CR700
S2A-TP
45OHMS
1
45OHMS
1
E705
45OHMS
1
A
C
1
4
6
5
2
A
C
CR701
AGND
S2A-TP
PWR_IN0
A
AGND
R700
249
C
WALWART POWER SUPPLY CIRCUITRY
0.01UF
0.01UF
4.7UF
C717
4.7UF
4.7UF
Rev. 0 | Page 16 of 28
C720
Figure 23. Power Supply Circuitry
4.7UF
A
S2A-TP
C
CR705
PWR_IN2
A
S2A-TP
C
CR704
PWR_IN1
A
C
CR703
S2A-TP
PWR_IN3
UG-200
Evaluation Board User Guide
09436-023
CR702
UG-200
09436-024
Evaluation Board User Guide
Figure 24. Top (Layer 1)
Rev. 0 | Page 17 of 28
Evaluation Board User Guide
09436-025
UG-200
Figure 25. Ground (Layer 2)
Rev. 0 | Page 18 of 28
UG-200
09436-026
Evaluation Board User Guide
Figure 26. Power Plane (Layer 3)
Rev. 0 | Page 19 of 28
Evaluation Board User Guide
09436-027
UG-200
Figure 27. Ground Plane (Layer 4)
Rev. 0 | Page 20 of 28
UG-200
09436-028
Evaluation Board User Guide
Figure 28. Ground Plane (Layer 5)
Rev. 0 | Page 21 of 28
Evaluation Board User Guide
09436-029
UG-200
Figure 29. Power Plane (Layer 6)
Rev. 0 | Page 22 of 28
UG-200
09436-030
Evaluation Board User Guide
Figure 30. Ground Plane (Layer 7)
Rev. 0 | Page 23 of 28
Evaluation Board User Guide
09436-031
UG-200
Figure 31. Bottom Side (Layer 8)
Rev. 0 | Page 24 of 28
Evaluation Board User Guide
UG-200
ORDERING INFORMATION
BILL OF MATERIALS
Table 1.
Item
1
2
Qty
1
38
3
7
Reference Designator
9467CE01A
C101, C102, C104, C105, C106, C107, C108,
C109, C110, C111, C201, C202, C204, C207,
C208, C209, C210, C302, C303, C313, C314,
C315, C316, C317, C318, C319, C320, C321,
C322, C323, C428, C431, C600, C601, C700,
C701, C702, C703
C112, C200, C704, C705, C706, C707, C714
4
1
C308
5
1
C309
6
1
C310
7
55
8
8
9
2
C400, C401, C402, C403, C404, C405, C406,
C407, C408, C409, C410, C411, C412, C413,
C414, C415, C416, C417, C418, C419, C420,
C421, C422, C423, C424, C425, C426, C427,
C429, C430, C432, C433, C434, C435, C437,
C438, C439, C440, C441, C442, C443, C444,
C445, C446, C447, C448, C449, C450, C451,
C452, C453, C454, C455, C456, C457
C708, C709, C710, C715, C716, C717, C718,
C720
C713, C719
10
1
C116
11
12
2
5
CR300, CR702
CR700, CR701, CR703, CR704, CR705
13
14
1
8
15
1
CR200
E700, E701, E702, E703, E704, E705, E706,
E707
F700
16
17
18
1
3
2
FL700
J100, J102, J201
J300, P600
19
20
21
1
1
3
J700
L105
P100, P200, P300
22
2
P501, P502
23
13
R107, R110, R123, R124, R125, R129, R310,
R312, R314, R315, R606, R608, R610
Description
PCB
Capacitor, 0.1 µF, 0402, X7R,
ceramic
Manufacturer
Part Number
Murata
GRM155R71C104KA88D
Capacitor tantalum, 10 µF,
10 V, 10%, SMD
Capacitor, 1800 pF, 25 V,
ceramic, 0402, SMD
Capacitor, ceramic, 0.033 µF,
10%, 16 V, X5R, 0402
Capacitor, 1500 pF, 0402,
25 V, ceramic, X7R
Capacitor, ceramic, 0.1 µF,
6.3 V, X5R, 0201
AVX
TAJA106K010RNJ
Panasonic
ECJ-0EB1E182K
Panasonic
0402YD333KAT2A
Panasonic
ECJ-0EB1E152K
Murata
GRM033R60J104KE19D
Murata
GRM188R60J475KE19D
Panasonic
ECJ-0EB1C103K
Murata
GRM0335C1E1R8CD01D
Panasonic
Micro
Commercial
Components
Corp
Avago
Panasonic
LNJ314G8TRA
S2A-TP
Tyco/Raychem
NANOSMDC110F-2
Murata
Samtec
Samtec
BNX016-01
SMA-J-P-H-ST-EM1
TSW-104-08-T-D
Switchcraft
Coilcraft
Samtec
RAPC722X
0603CS-10NXJLW
TSW-103-08-G-S
Tyco
6469169-1
Panasonic
ERJ-2GE0R00X
Capacitor, ceramic, 4.7 µF,
6.3 V, X5R, 0603
Capacitor, 10,000 pF, 0402,
16 V, ceramic, X7R
Capacitor, ceramic, 1.8 pF,
25 V, C0G 0201
LED green USS type 0603
Rectifier SIL 2A 50 V DO214AA
Diode Schottky dual series
Bead core 3.2 × 2.5 × 1.6
SMD T/R, 45 Ω @ 100 MHz
Polyswitch 1.10 A reset fuse
SMD
EMI filter LC block choke coil
SMA, end launch, COAX
CONN-PCB header 8-pin
double row
Power supply connector
Inductor SM, 10 nH
Conn-PCB BERG HDR ST
male 3P
CONN_PCB 60-pin RA
connector
Resistor, 0 Ω, 0402, 1/16 W,
1%
Rev. 0 | Page 25 of 28
HSMS-2812BLK
EXCCL3225U1
UG-200
Evaluation Board User Guide
Item
24
Qty
2
Reference Designator
R117, R118
25
2
R119, R120
26
2
R206, R207
27
4
R105, R106, R111, R112
28
5
R200, R201, R600, R601, R602
29
2
R127, R128
30
6
R204, R205, R303, R307, R308, R700
31
10
32
1
R300, R304, R305, R306, R309, R603, R604,
R605, R701, R702
R704
33
1
R703
34
1
R301
35
1
R302
36
1
R316
37
2
R103, R130
38
2
R311, R313
39
40
41
42
2
2
1
1
T101, T104
T103, T200
T105
DUT1
43
1
U100
44
1
U300
45
1
U400
46
47
48
1
1
2
U600
U601
U700, U701
49
1
U702
50
1
U703
51
1
Y200
Description
Resistor, 5.60 Ω, 1/16 W, 1%,
0402, SMD
Resistor, 15 Ω, 1/20 W, 5%,
0201, SMD
Resistor, 33 Ω, 1/10 W, 5%,
0402, SMD
Resistor, 33 Ω, 1/10 W, 5%,
0402, SMD
Resistor, 10.0 kΩ, 0402,
1/16 W, 1%
Resistor, 0.0 Ω, 1/20 W, 0201,
SMD
Resistor, 249 Ω, 0402,
1/16 W, 1%
Resistor, 1.00 kΩ, 0402,
1/16 W, 1%
Resistor, 750 Ω, 1/10 W, 5%,
0402, SMD
Resistor, 316 Ω, 0402,
1/16 W, 1%
Resistor, 4.12 kΩ, 0402,
1/10 W, 1%
Resistor, 5.1 kΩ, 0402,
1/16 W, 5%
Resistor, 200 Ω, 1/10 W, 1%,
0402, SMD
Resistor, 20 Ω, 1/20 W, 5%,
0201, SMD
Resistor, 100 Ω, 1/10 W, 5%,
0402, SMD
XFMR, 1:1 impedance ratio
Balun, 1:1 impedance ratio
Balun, 1:1 impedance ratio
IC-ADI LFCSP 10 mm ×
10 mm plus EPAD
IC 2.6 GHz ultralow
distortion differential IF/RF
amplifier
IC-ADI 12-output CLK GEN
with INT 1.6 GHZ VCO
IC, voltage ref, precision
series, SOT23_6
IC tinylogic UHS dual buffer
IC tinylogic UHS dual buffer
IC, regulator 0.8 V to 5.0 V,
low dropout CMOS, SO8
IC-ADI low dropout CMOS
linear regulator
IC-ADI low dropout CMOS
linear regulator
250 MHz, XTAL 3.3 V LVPECL
OSC
Rev. 0 | Page 26 of 28
Manufacturer
Vishay/Dale
Part Number
CRCW04025R60FNED
Panasonic
ERJ-1GEJ150C
Panasonic
ERJ-2GEJ330X
Panasonic
ERJ-2GEJ330X
Panasonic
ERJ-2RKF1002X
Panasonic
ERJ-1GE0R00C
Panasonic
ERJ-2RKF2490X
Panasonic
ERJ-2RKF1001X
Panasonic
ERJ-2GEJ751X
Panasonic
ERJ-2RKF3160X
Panasonic
ERJ-2RKF4121X
Panasonic
ERJ-2GEJ512X
Panasonic
ERJ-2RKF2000X
Panasonic
ERJ-1GEJ200C
Panasonic
ERJ-2GEJ101X
Minicircuits
Macom
Anaren
Analog Devices
ADT1-1WT+
MABA-007159-000000
BD0205F5050A00
AD9467BCPZ-250
Analog Devices
ADL5562ACPZ-R7
Analog Devices
AD9517-4BCPZ
Analog Devices
ADR130AUJZ
Fairchild
Fairchild
Analog Devices
NC7WZ07P6X
NC7WZ16P6X
ADP1708ARDZ-R7
Analog Devices
ADP1706ARDZ-3.3-R7
Analog Devices
ADP1706ARDZ-1.8-R7
Vectron
VCC6-QCD-250M000
Evaluation Board User Guide
Item
52
Qty
7
Reference Designator
MP101, MP102, MP103, MP104, MP105,
MP106, MP107
53
4
MP111, MP112, MP113, MP114
UG-200
Description
Part of assembly, 100 mil
jumpers, place into P100
(Pin 2 to Pin 3), P200 (Pin 1
to Pin 2), J300 (Pin 3 to
Pin 4), P600 (Pin 1 to Pin 2,
Pin 3 to Pin 4, Pin 5 to Pin 6,
Pin 7 to Pin 8)
Part of assembly, insert/
snap into the large holes
from the bottom side of
board, 14 mm height, dual
locking standoffs for circuit
board support
Rev. 0 | Page 27 of 28
Manufacturer
SAMTEC
Part Number
SNT-100-BK-G-H
RICHCO
CBSB-14-01
UG-200
Evaluation Board User Guide
NOTES
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
Legal Terms and Conditions
By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions
set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you
have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc.
(“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal,
temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided
for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional
limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term
“Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including
ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may
not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to
promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any
occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board.
Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice
to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO
WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED
TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL
PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF
THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE
AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable
United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of
Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby
submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
UG09436-0-10/10(0)
Rev. 0 | Page 28 of 28