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MAX AND MIN FUNCTIONS USING MULTIPLE-VALUED RECHARGED
SEMI-FLOATING GATE CIRCUITS
H. Gundersen and Y. Berg
Department of Informatics, University of Oslo, Blindern, N-0316 Oslo, Norway
henningg@ifi.uio.no
ABSTRACT
In this paper we present a new proposal for implementing
a voltage-mode Multiple-Valued (MV) maximum or minimum function. The circuit has been implemented using
Recharged Semi Floating-Gate (SFG) transistors. The benefit with this design is, the proposed circuits can easily be
fabricated using a conventional CMOS process. The circuit is suitable for a low power design, Vdd < 2 volt. It has
high noise margin and good linearity. The simulation results
for the proposed circuit are evaluated using AMS 0.35µm
CMOS device parameters.
2. RECHARGED SFG INVERTERS
2.1. The SFG Recharged Binary Inverter
1. INTRODUCTION
Multiple-valued logic has in the last few decades been proposed as a possible alternative to binary logic. Whereas binary logic is limited to only two states, ”true” and ”false”,
multiple-valued logic (MVL) replaces these with finitely or
infinitely numbers of values. A MVL system is defined as a
system operating on a higher radix than two [1]. A radix-n
set has n elements, {0, 1, ...., n-1}. The feasibility of MVL
depends on the availability of the devices constructed for
MVL operations [2]. The devices should be able to switch
between the different logical levels, and preferably be less
complex than the binary counterparts.
The multiple-input FG transistors can be used to simplify the design of multiple-valued logic [3]. The initial charge on the floating-gates may vary significantly and
therefore impose a very severe inaccuracy unless we apply
some form of initialization. Some work on floating-gate reset strategies have been presented [4] [5].
By recharging of the semi-floating-gate (SFG) we do not
only avoid the problems linked to programming or initializing of the floating gates, but we convert the non-volatile
floating gates to semi-floating-gates. The control of the actual floating gate charges in terms of predictable long term
charge restoration becomes easier. The SFG is not influenced by a random FG charge distortion due to a periodic
or frequent charge restoration or reset. The recharge of the
SFGs is accomplished by a local recharge transistor or a
0-7803-8251-X/04/$17.00 ©2004 IEEE
pass gate temporarily connecting the output to the floating
gate of a gate.
One of the most fundamental function in all digital logic
is the inverter or the NOT function. The Recharged SFG binary inverter and the SFG MVL inverter will briefly be presented in section 2. Section 3 covers an important function
in Multiple-valued Logic, the Down-Literal Circuit. In section 4 we look closer on the Pass Gate circuit. Section 5 will
look upon realization of the voltage mode MAX and MIN
functions using SFG Recharged Logic.
Clk
Pe
Ci
Vin Vsfg
Ci
Clk
Vout
Vin
Vout
Vsfg
Ne
Fig. 1. SFG binary inverter. The transistor sizes are Pe (w =
3.0µm and l = 0.35µm ) and Ne (w = 0.6µm and l = 0.35µm ).
The capacitor Ci is equal to 7.7f F
The inverter is truly a fundamental gate in all digital logic. The simple Recharged single input SFG Binary
Inverter[5] is shown in Figure 1. The SFG Binary Inverter
acts just like an ordinary inverter, except it has a recharge
Clk signal, the transfer characteristics is given in Figure 7,
output signal labeled Bin Inverter. As we can see the
output signal is “0” or “1” in the validation period of the
recharged signal and Vdd /2 in the recharge period.
2.2. The SFG Recharged MVL Inverter
The analog inverter is very useful for realization of the NOT
function in multi-valued logic[6]. In order to make a voltage
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N and a P transistor, and two capacitors Ci1 and Ci2 where
Ci1 is slightly less than Ci2 to set the threshold voltage of
the circuit to determine the switching point between Vin1
and Vin2 . The threshold voltage of the DLC can be varied
by the summation of the input voltages on Ci1 and Ci2 .
Clk
&'
Cf
Ci
Vin
Vsfg
!
Ci
Vout
Clk
$%
Cf
Pe
Vin
Vout
Vsfg
"#
Ne
Clk
Pe
Ci1
Ci1
Vin1
Fig. 2. The SFG MVL Inverter. The transistor sizes are Pe (w =
3.0µm and l = 0.35µm ) and Ne (w = 0.6µm and l = 0.35µm ).
The capacitor Ci = 7.7f F and Cf = 6.29f F
mode multi-valued signal, high accuracy is necessary, hence
high linearity, because the voltage levels for each logic level
is an equal division of Vdd . That is why the analog inverter is a key element in Multiple-Valued Logic. The SFG
Recharged MVL Inverter[5] is shown in Figure 2. It has
a weighted negative feedback mechanism (Cf ), and ideally
the gain is −1.The transfer characteristic of the analog inverter, which is given by Eq. 1, is determined by capacitive
Cf
Ci
and kf = Ctotal
).
division factor ki and kf ( ki = Ctotal
Vout = Vdd − Vin
(1)
Where Vin and Vout are the voltages on the input and output terminals, Vdd is the supply voltage.
Ideally Ci = Cf , however Cf has to be slightly smaller
than Ci due to the output conductance and the parasitic capacitance, Cgd [7]. The transfer characteristics of the SFG
Recharged MVL Inverter are shown in figure 7, output signal labeled M V L Inverter, this shows the NOT function
of MV signal labeled input1 .
3. MVL RECHARGED SFC DOWN LITERAL
CIRCUIT
One of the most important functions in multi-valued logic is
the Down-Literal Function[8], it divides logic levels in the
multi-valued logic into a binary state at an arbitrary threshold. A Down Literal Circuit(DLC) is said to be a binary
inverter with a multi-valued input and a threshold[9]. The
function of a DLC Dj(x) is given by Eq. 2. It outputs R − 1
if x is equal or less to the threshold j, else the output is
zero[10].
R−1
(x≤j)
Dj(x) = { 0
(2)
(x≥j+1)
Where x ∈ {0, 1, 2, .., R − 1} and j ∈ {0, 1, 2, .., R − 2},
and R is the Radix of the signal.
We have proposed the down literal circuit with Semi Floating Gate Transistors (Figure 3). The DLC is made with a
Vsfg
./
Vin2
*+
8
()
,
,-
Vout
45
23
89
Vsfg
0
01
67
Vout
Vin2
:;
Ci2
4
Vin1
Clk
<=
Ne
Ci2
Fig. 3. The SFG MVL DLC. The transistor sizes are Pe (w =
3.0µm and l = 0.35µm ) and Ne (w = 0.6µm and l = 0.35µm ).
The capacitor Ci1 = 38f F and Ci2 = 44f F
3.1. The Voltage Comparator
By combining the analog inverter and the DLC circuit, we
can make a voltage comparator [6]. If we look at the output
labeled DLC in figure 7 we notice, if input2 is lower than
input1 the output labeled DLC is equal to Vdd , otherwise
Vss . This gives a comparison between the two input signals
input1 and input2 .
4. MVL SFC PASS GATE
A pass gate (PG) network is a popular way to realize a multivalued logic function in hardware [11]. Fig 4 shows a ptype and a n-type CMOS Pass-Gate. The control voltage
for the pPG and nPG is defined as the voltage on the gate
terminal of n-channel and p-channel MOS transistor. pPG
and nPG has a path between in and out when their control
voltage is Vss and Vdd , respectively, or else it acts as an
open circuit(high resistivity), no connection between in and
out.
As we can see also the PG circuit is clocked. The proposal is to make sure that the output is clamped to the input
signal in the recharge period, or else the output will not be a
valid recharged signal, resulting in an undefined level in the
recharge period.
5. MULTI-VALUED RECHARGED SFG MIN AND
MAX FUNCTION
The MAX and MIN functions are also fundamental functions in Multiple-valued logic. The MAX function corresponds to the binary function OR, and the MIN function is the AND function in the binary world. The MAX
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Ne
Clk
In
>?
BC
DE
@A
Out
In
Out
pPG
In
Pe
Clk
FG
Input 2
JK
LM
HI
Out In
Ž
Out
nPG
Clk
Ne
Pe
nPG
Ž
v
vw
Clk
Clk
„
x
C2
ˆ
(a) pPG
C3
ˆ‰
†
†‡
š›
‚
‚ƒ
C1
(b) nPG
š
Input 1
Fig. 4. The Pass Gate Circuits. The transistor sizes are Pe (w =
Œ
MVL Inv
Out
C4
z
x
z{
Š‹
œ
œ
’“
y
€
€
~
~
|
|}
DLC Out
C5
˜™
–—
”•
Bin- Output

‘
Out
pPG
Œ
0.6µm and l = 0.35µm ) and Ne (w = 0.6µm and l = 0.35µm ).
Input 2
Clk
P
Clk
Clk
PQ
RS
C2
T
C3
TU
Z
^
^_
`
`a
Z[
XY
t
p
Input 1
bc
pq
\]
MVL Inv
Out
C4
NO
DLC Out
r
rs
h
hi
j
jk
C5
VW
C1
tu
no
l
Binlm
Input 2
Input 1 Bin Inverter
DLC
MVL Inverter Clock
= 7.7f F , C2 = 6.3f F , C3 = 38f F , C4 = 44f F and C5 = 7.7f F
2
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0.5
0
0
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Time (s)
2
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x 10
Fig. 7. The Maximum and Minimum Plot (radix 16), simulated
with Cadence 4.4.5.100.10 with spectre simulation tool using AMS
0.35µm CMOS device parameters Hit Kit version: 3.30.42.00.
pPG
de
Fig. 6. The MVL Recharged SFG Min Circuit. The capacitors C1
Minimum Maximum
and MIN function has been presented earlier using NeuronMOS Transistors[6], [10],[12]. However another way of
realizing these functions is by using Semi-Floating Gate
Recharge Logic. This makes it possible to implement a lowpower digital system with reduced dynamic power dissipation. The advantage of this technology is presented in [5]
and the circuit is presented in fig 5. As we can see the circuit use the analog inverter and the DLC to make a voltage
comparator. It then gives a selection signals to the PassGate network, which consists of a pPass-Gate and a nPassGate circuit, If the output signal labeled DLC is “high”,
input1 is selected, and if the signal labeled DLC is “low”,
input2 is selected. Just by changing the pPass-Gate(nPG)
with a nPass-Gate(nPG) and nPG with pPG we can achieve
the minimum function as shown in fig 6. The output of the
MIN circuit (labeled M inimum) is shown in fig 7.
The heart of this circuit is the analog inverter and the
DLC. We know that the analog inverter can be made with
high linearity and good precision, just by adjustment of C1
and C2 . This is described in [7]. As mentioned in section 3
the DLC divides logic levels in the multi-valued logic into a
binary state at an arbitrary threshold. The DLC is a 2 input
inverter, and by making C4 slightly less than C3 , we make
sure the threshold voltage is set correct, and the output of the
DLC is set “high” when Input1 is equal to Input2, hence
PassGate network will work properly.
f
fg
Output
Input 1
Out
Input 2
"Max"
Out 1
nPG
"Max"
Input 3
Input 4
"Max"
Out 2
Fig. 5. The MVL Recharged SFG Max Circuit. The capacitors C1
= 7.7f F , C2 = 6.3f F , C3 = 38f F , C4 = 44f F and C5 = 7.7f F
Fig. 8. The 4 input MAX Circuit
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Input 1
Input 2
2
1.5
1
0.5
0
Input 3
2
1.5
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0.5
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Input 4
2
1.5
1
0.5
0
Maximum
7. REFERENCES
2
1.5
1
0.5
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2
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0.5
0
[1] K.C. Smith, “Multiple-Valued logic: a tutorial and apprecation,” IEEE Computers Vol. 21, pp. 17–27, 1988.
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
[2] D. Etiemble, “On the performance of Multiple-Valued
integrated circuits: Past, present and future,” Proceedings of the 22nd IEEE International Symposium on MultipleValued Logic(ISMVL’92), pp. 154–164, 1992.
3.2
−6
x 10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
[3] T. Shibata and T. Ohmi, “A Functional MOS Transistor Featuring Gate-Level Weigheted Sum and Threshold
Operations,” IEEE Transactions on Electron devices, vol.
39(6), pp. 1444–1455, 1992.
−6
x 10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
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1.8
2
2.2
2.4
2.6
2.8
3
3.2
[4] K. Kotani, T. Shibata, M. Imai, and T. Ohmi, “Clocked
Neuron-Mos Logic Circuits Employing Auto Threhold
Adjustment,” IEEE International Solid-State Circuits Conference(ISSCC), pp. 320–321,388, 1995.
−6
x 10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
−6
x 10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6 1.8
Time(s)
2
2.2
2.4
2.6
2.8
3
[5] Y. Berg, S. Aunet, O. Mirmotahari, and M. Høvin,
“Novel Recharge Semi-Floating-Gate CMOS Logic For
Multiple-Valued Systems,”
Proceedings of the 2003
IEEE International Symposium on Circuits And Systems in
Bangkok(ISCAS2003), 2003.
3.2
−6
x 10
The 4 input max Circuit (radix 16), simulated with
Cadence 4.4.5.100.10 with spectre simulation tool using AMS
0.35µm CMOS device parameters Hit Kit version: 3.30.42.00.
[6] M. Inaba, K. Tanno, and O Ishizuka, “Analog Inverter with
Neuron-MOS Transistors and Its Application,” IEICE
Trans. Fundamentals, Vol.E85-A, No.2 February 2002, pp.
360–365, 2002.
6. CONCLUSION
[7] Y. Berg, T. S. Lande, Ø. Næss, and H. Gundersen, “UltraLow-Voltage Floating Gate Transconductance Amplifiers,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing,vol.48,no.1, Jan. 2001.
Fig. 9.
In this paper we have presented a new proposal for implementing a voltage-mode minimum and maximum function,
which are fundamental functions in multiple valued logic.
Furthermore we have pinpointed the advantages and disadvantages of using Recharged SFG MVL in the design of the
circuits. The MAX and MIN applications show high linearity, and can be fabricated using a conventional CMOS
process. And as we can see, it is easy to make a multiple
input MAX- or MIN Circuit(4,8,16,32,64...) just by adding
the MAX or MIN circuits together as shown in fig 8. The
simulated result of this application is presented in fig 9.
[8] J. Shen, K. Tanno, and O. Ishizuka, “Down Literal Circuit with Neuron-Mos Transistors and Its Applications,”
Proceedings of the 29nd IEEE International Symposium on
Multiple-Valued Logic(ISMVL’99), 1999.
[9] M. Syuto, J. Shen, K. Tanno, and O. Ishizuka, “Multi-Input
Variable-Threshold Circuits for Multi-Valued Logic Funcions,” Proceedings of the 30nd IEEE International Symposium on Multiple-Valued Logic(ISMVL’00), 2000.
[10] M. Inaba, K. Tanno, and O. Ishizuka, “Multi-Valued FlipFlop with Neuron-CMOS NMIN Circuits,” Proceedings of
the 32nd IEEE International Symposium on Multiple-Valued
Logic(ISMVL’02), 2002.
[11] J. Shen, M. Inaba, K. Tanno, and O. Ishizuka, “MultiValued Logic Pass Gate Network Using Neuron-MOS
Transistors,” Proceedings of the 30nd IEEE International
Symposium on Multiple-Valued Logic(ISMVL’00), 2000.
[12] M. Inaba, K. Tanno, and O. Ishizuka, “Realization of
NMAX and NMIN Functions with Multi-Valued Voltage
Comparators,” Proceedings of the 31nd IEEE International
Symposium on Multiple-Valued Logic(ISMVL’01), 2001.
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