Study of CMOS Process Variation by
Multiplexing Analog Characteristics
by
Karen Mercedes Gonzalez-Valentin Gettings
Bachelor of Science, Universidad de Puerto Rico-Recinto de MayagUez, June 2000
Master of Science, Massachusetts Institute of Technology, June 2002
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
May 23, 2007
©Massachusetts Institute of Technology, 2007. All Rights Reserved.
Author
D~partment of Electrical-4 ngiering and Computer Sciente
May 23, 2007
Certified by
-. - ning
Professor of Electrical Encineefrino ins] Comnnt-r Science
ervisor
Accepted by
Smith
Studies
Graduate
on
Committee
Chairman, Department
Department of Electrical Engineering and Computer Science
AU '20237
BARKER
Study of CMOS Process Variation by
Multiplexing Analog Characteristics
by
Karen Mercedes Gonzilez-Valentin Gettings
Submitted to the Department of ElectricalEngineeringand Computer Science
on May 23, 2007, in partialfulfillment of the requirementsfor the degree of
Doctor of Philosophy
Abstract
Aggressive technology scaling raises the need for efficient methods to characterize
and model circuit variation at both the front and back end of line, where critical
parameters such as threshold voltage and parasitic capacitance must be carefully modeled
for accurate circuit performance. This thesis addresses this need by contributing a test
circuit methodology for the extraction of spatial, layout and size dependent variations at
both device and interconnect levels. The test chip uses a scan chain approach combined
with low-leakage and low-variation switches, and Kelvin sensing connections, providing
access to detailed analog device characteristics in large arrays of test devices. Front end
of line (FEOL) test structures include transistors of different sizes, number of polysilicon
fingers, polysilicon fingers proximity, and orientation, for both NMOS and PMOS
MOSFETs. Back end of line (BEOL) test structures include parasitic coupling, plane to
plane and crossover capacitances, measured using a charge-based capacitive
measurement (CBCM) methodology integrated with switches in the scan chain.
The testing of the designed test chip has proven successful for both device and
interconnect test structures. Different layout practices in both NMOS and PMOS
transistors are seen to result in significant differences in mean and standard deviation of
measured output current, with 95% confidence or more. The FEOL structure analysis
shows strong dependencies between layout practices: orientation offers a consistent but
opposite offset in NMOS and PMOS transistors and variation increases for gate lengths
split among fingers. Variation due to sizing follows Pelgrom's model, showing that
variation increases for smaller gate lengths and widths, in both NMOS and PMOS
transistors. Threshold voltage extraction and variation analysis also demonstrate how
variation increases for smaller features. BEOL capacitances were extracted and subfemto Farad changes were detected for capacitive test structures. Spatial analysis reveals
a large die-to-die trend in device performance. The parameter extraction and variation
analyses made possible by the variation test chip enable the identification of likely
variation sources, quantification of circuit impact and sensitivity, and specification of
layout practices for variation minimization.
Thesis Supervisor: Duane S. Boning
Title: Professor of Electrical Engineering and Computer Science
3
4
Acknowledgements
When thinking back about my seven year career at MIT, I can only thank the God
Almighty for having blessed me with the opportunity of attending such a prestigious
institution, and rub shoulders with so many fantastic and impressive people. It has been a
long, windy road, and its successful conclusion could have not happened without the help
and support of many people and institutions.
I would like to thank my advisor, Prof. Duane Boning, for giving me the opportunity
to join his research group and guiding me through my master's and doctorate degrees.
Duane, your infinite patience, big heart, enthusiasm, impressive knowledge, and attention
to detail have made me feel comfortable at MIT for the last seven years. Thank you very
much for all your help and guidance.
Special thanks to Prof. Joel Dawson, whose friendship and selfless help with the
analog part of my thesis have been invaluable. I also want to thank Prof. Anantha
Chandrakasan for his help and guidance with circuit design and life in general since my
first day at MIT, and more recently as a thesis committee member. Also, thanks to Prof.
Luca Daniel, also a thesis committee member, whose enthusiasm, motivation and good
ideas have been very helpful in completing this thesis.
I was able to collaborate with very talented people during the design and analysis of
the work presented in this thesis. I wholeheartedly appreciate the collaboration of JinKyu Park, from Samsung Electronics, for providing ideas and guidance with the CBCM
test structures. I also appreciate the help of Dr. Robert Lefferts for his enthusiastic help
with the design of the test chip architecture, particularly the low leakage switches. I
appreciate the help I received during my master's thesis that also influenced this thesis,
including the contributions of my M.S. thesis partner Joseph Panganiban, and IBM's Sani
Nassif and his research group, whose contributions in the scan chain design and design of
experiments were very helpful for the design of this new test chip. I also very much
appreciate the help in the understanding of device behavior from Prof. Jesus del Alamo,
Cait Ni Chldirigh, and Niamh Waldron, all from MTL.
I very much appreciate the comradery, collaboration and friendship from all my
group mates at the Metrology group at MIT, present and past: Aaron Gower-Hall, David
White, Han Chen, Brian Lee, Vikas Mehrotra, Tamba Gbondo-Tugbawa, Tae Park,
Joseph Panganiban, Allan Lum, Michael Mills, Nigel Drego, Xiaolin Xie, Hong Cai,
Tyrone Hill, Hayden Taylor, Shawn Staker, Kwaku Abrokwah, Brian Tang, Mehdi
Gazor, Karthik Balakrishnan, Daihyun Lim, Shyam Vudathu, Daniel Truque, Ali
Farahanchi, Ajay Somani, and Edward Paul. Nigel, thank you for all your noble help and
support with the design, tape out, and testing of the test chip, not to mention all the scripts
and all the support when things were not going so well. I am so lucky to have you and
Vidya as my friends. Daihyun and Karthik, thank you for all of your great ideas regarding
the design and testing of the chip. To everybody else: thanks for all the collaboration, all
the fun conversations, all the donuts, and all the good times. You will always be in my
heart.
5
Many thanks to everybody at MTL for all their support and friendship. Special thanks
go out to my dear friend Debb Hodges-Pab6n. Thank your friendship and for making me
part of your life. You are the best ambassador MTL could wish for. Also, many thanks to
Sharlene Blake, Duane's assistant, who has helped me with so many administrative
matters, and with whom I have shared so many enjoyable conversations. I wish you and
your family the very best in life.
Thanks to all my friends everywhere for their continuous support, and for constantly
reminding me of how much more there is in life besides work. Many thanks also to all of
my previous educators who paved the way for my successful tenure at MIT, especially
Dr. Efrain Rosario.
Not many girls from Las Marifas, Puerto Rico, have the chance of getting a Ph.D.
from MIT. There are two people who deserve a lot of credit for helping me get here: Dr.
Susan Cohen, who has been my mentor and role model since 1999, when I had the
privilege of working for her at IBM in a summer internship, and who was the first person
to suggest that I go to graduate school. Susan, thank you so much for all your motivation,
guidance and encouragement. I will always be grateful for all you have done for me, and
for your beautiful friendship. The second person is Dr. Keith Whittingham, who held my
hand through the process of applying and getting a full fellowship for graduate school.
Thank you very much for your help and mentorship.
Last but not least, my family deserves all the credit for this accomplishment, as they
have supported me every step of the way with complete selflessness. It has been that
support that has made me strong enough to deal with all that life has to offer, good and
bad. Many thanks to my amazing husband Andrew Gettings, the love of my life and who
has made my life happier than I could have ever imagined. Thank you for your
unconditional support and love. Graduate school would have been unbearable without
you. Betsy, thank you for all your love, your beautiful friendship and all your support. I
am so lucky to have you as my sister. Tatito, thank you for being such a great brother, for
all your love, and for the beautiful Marcos, Kristina and Waleska. Papi, there are no
words to thank you enough for all that you have done for me. Thank you for being the
best father one could wish for, for the upbringing you gave me and for all your
encouragement and support in everything I do. Mami, I am sure you are enjoying this
moment from Heaven. I thank the Lord for letting me have the very best mother on Earth
for 26 years. I miss you, but I feel comfort in knowing that you wanted me to reach this
milestone, and hopefully I am making you proud. To all my family, this milestone is
dedicated to you. Special thanks also go to Andy's parents, D. Anne and D. Larry. Thank
you for taking care of me here in New England like your own daughter, and for all your
warmth and encouragement.
This research has been funded in part by the Samsung Electronics, the MARCO
Interconnect Focus Center and the Center for Circuits, Systems and Solutions, by the
IBM Ph.D. Fellowship, and by the Bell Laboratories Cooperative Research Fellowship
Program.
6
A la memoria de mi madre
y el amor de mi esposo, padre y hermanos.
To the memory of my mother
and the love of my husband, father and siblings.
7
8
Table of Contents
CHAPTER 1
1.1
1.1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.3
1.4
1.5
CHAPTER
INTRODUCTION............................................................................................19
M otivation...............................................................................................
Our Previous Work.................................................................................
Review of Test Structures from Literature .............................................
Dedicated Variation Test Structures ........................................................
Ring Oscillator Variation Test Structures...............................................
M ethods to Extract Full I-V Curves.........................................................
M ethod to Measure and M odel Interconnects ........................................
Thesis Contributions ...............................................................................
Thesis Outline ..........................................................................................
Sum m ary .................................................................................................
2 TEST CHIP ARCHITECTURE .....................................................................
19
20
22
23
24
26
28
30
31
32
33
2.1
2.2
2.3
2.4
2.5
2.5.1
2.6
2.7
2.8
M ethodology .............................................................................................
Tile ..........................................................................................................
Row ..........................................................................................................
Chip..............................................................................................................38
Feedback Im plem entation........................................................................
Operational Amplifier Design ..................................................................
Implem entation of Low Leakage Switches.............................................
Sim ulation Results ...................................................................................
Sum m ary .................................................................................................
39
40
43
46
49
CHAPTER
3 TEST STRUCTURES DESCRIPTION ............................................................
51
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
Front End of Line Structures....................................................................
NM OS and PM OS Structures of Different Sizes....................................
Orientation ..............................................................................................
Polysilicon Spacing ..................................................................................
Number of Polysilicon Fingers ...............................................................
Back End of Line Structures ...................................................................
Charge Based Capacitive Measurement Methodology and
Im plem entation........................................................................................
Plane Structures .......................................................................................
Comb Structures......................................................................................
Grid Structures ........................................................................................
Sum m ary .................................................................................................
51
51
52
53
54
55
3.2.2
3.2.3
3.2.4
3.3
CHAPTER
4.1
33
34
37
55
59
59
60
60
4 RESULTS AND ANALYSIS FOR LAYOUT-DEPENDENT TEST
STRUCTURES............................................................................................
63
Functionality ............................................................................................
63
9
Electrical Repeatability ...........................................................................
4.1.1
Leakage Currents ......................................................................................
4.1.2
Variation Analysis ...................................................................................
4.2
W ithin Chip and Chip to Chip Components .............................................
4.2.1
W ithin Chip Variance.........................................................................67
4.2.1.1
4.2.1.2 Chip to Chip Variance ......................................................................
4.2.1.3 Total Variance ...................................................................................
4.2.1.4 Aggregated Variance ........................................................................
4.2.2 Normalized Variation................................................................................68
Evaluation of Mean Differences .............................................................
4.2.3
4.2.4 Evaluation of Variance Ratios .................................................................
Layout Dependent Variation Analysis....................................................
4.3
Orientation ...............................................................................................
4.3.1
4.3.1.1 Variance Components and Variation................................................
4.3.2
Polysilicon Spacing..................................................................................
4.3.2.1 Variance Components and Variation..................................................80
Number of Polysilicon Fingers ...............................................................
4.3.3
4.3.3.1 Variance Components and Variation..................................................86
Summary .................................................................................................
4.4
CHAPTER
64
65
65
66
67
68
68
69
70
70
70
77
77
81
86
5 RESULTS AND ANALYSIS OF TEST STRUCTURES OF TRANSISTORS OF
DIFFERENT SIZES ....................................................................................
89
89
Functionality ............................................................................................
5.1
93
Transistors of Different Sizes at Saturation .............................................
5.2
99
Transistors of Different Sizes with Voltage Sweeps ...............................
5.3
Transistors of Different Sizes with Gate Voltage Sweeps........................99
5.3.1
5.3.2
Threshold Voltage Variation Analysis.......................................................102
NM OS Threshold Voltage...................................................................103
5.3.2.1
108
PM OS Threshold Voltage ...................................................................
5.3.2.2
114
Summary ....................................................................................................
5.4
CHAPTER
6 RESULTS AND ANALYSIS OF INTERCONNECT TEST STRUCTURES ........... 115
6.1
6.1.1
6.2
6.3
6.3.1
6.4
6.5
6.6
Measurement M ethod Review and Adjustments ....................................... 115
117
Electrical Repeatability ..............................................................................
Results............................................117
Overview of M easured Capacitances
119
Comb Capacitances Results and Analysis .................................................
120
.....................
and
Thickness
Spacing
Finger
Between
Variation Analysis
Plane to Plane Capacitances Results and Analysis .................................... 121
Grid Capacitances Results and Analysis....................................................122
125
Summary ....................................................................................................
CHAPTER 7 SPATIAL ANALYSIS ....................................................................................
7.1
7.2
127
Chip to Chip Spatial Analysis....................................................................127
Within Chip Spatial Analysis.....................................................................130
10
7.3
CHAPTER
8.1
8.2
8.3
8.4
8.5
CHAPTER
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.3
Summary ....................................................................................................
134
8 SUGGESTIONS FOR FUTURE IMPLEMENTATIONS .....................................
137
Gate Leakage in Newer Technologies .......................................................
137
Design of the On-Chip Feedback...............................................................138
Design Review of FEOL Low Leakage Switches ..................................... 138
Off Tiles Leakage Currents........................................................................140
Summary ....................................................................................................
141
9 CONCLUSIONS............................................................................................143
Thesis Contributions ..................................................................................
143
Test Chip Design and Implementation.......................................................143
Testing Results and Analysis of the Test Structures..................................144
Future W ork ...............................................................................................
146
On-chip M easurements ..............................................................................
146
Study of Sub-threshold Variation ..............................................................
146
Charge Based Capacitance Measurement Structures.................................146
Coupling Capacitances Structures .............................................................
147
Directly Probed Transistors .......................................................................
147
Summary of Contributions.........................................................................148
REFERENCES...................................................................................................................149
APPENDIX
I TEST STRUCTURES NOMENCLATURE AND Row LOCATION ..................... 153
APPENDIX 11 CALCULATION FOR CROSSOVER CAPACITANCE......................................161
APPENDIX
III LAYOUT SCREEN SHOTS..........................................................................163
11
12
List of Figures
Figure 1-1: Agarwal et al. VT mismatch test structure [8]. ...........................................
23
Figure 1-2: Bhushan, Ketchen at al. ring oscillator stage to measure AVT [14] ........... 25
Figure 1-3: Transistor array test structure proposed by Quarantelli et al. [18].............27
Figure 1-4: Lefferts architecture [4]...............................................................................28
Figure 1-5: C B C M structure [22]......................................................................................29
Figure 2-1: Traditional (a) method of testing vs. proposed (b). ....................................
34
Figure 2-2: Tile block diagram for FEOL test structures. ............................................
35
Figure 2-3: Tile block diagram for BEOL test structures.............................................
35
Figure 2-4: Tile layouts. ................................................................................................
36
Figure 2-5: Row block diagram....................................................................................
37
Figure 2-6: Chip block diagram....................................................................................
38
Figure 2-7: Die photo of full test chip ..........................................................................
39
Figure 2-8: Feedback network for VDD regulation. .......................................................
40
Figure 2-9: Feedback implementation..........................................................................
40
Figure 2-10: Opamp architecture.................................................................................
41
Figure 2-11: Opamp frequency response......................................................................
42
Figure 2-12: Step response of the opamp. .....................................................................
42
Figure 2-13: Low leakage switch (left), when enabled (center) and when not enabled
(right)........................................................................................................
. . 43
Figure 2-14: RON resistance for enabled switch. ...........................................................
44
Figure 2-15: Schematics for low leakage switch...........................................................45
Figure 2-16: Simulated data VDS sweep for NMOS 0.50 jim /0.18 gm device.............46
Figure 2-17: Model for simulation of row....................................................................
47
Figure 2-18: NMOS probed alone.................................................................................47
Figure 2-19: Simulated opamp limitations for NMOS 0.50 gm /0.18 gm device. ....... 48
Figure 2-20: Scan chain functionality . .........................................................................
49
Figure 3-1: Different size FEOL test structures, with different channel lengths (L)
and w idths (W )..........................................................................................
52
Figure 3-2: Orientation FEOL test structures...............................................................
53
Figure 3-3: Poly finger spacing FEOL test structures. ..................................................
54
Figure 3-4: Number of poly fingers FEOL test structures.............................................54
Figure 3-5: Interconnect capacitances - 1. Fringing, 2. Coupling, 3. Plane..................55
Figure 3-6: CBCM structure with switches.......................................................................56
Figure 3-7: BEOL switch schematic. ...........................................................................
58
Figure 3-8: Layouts of BEOL tiles...............................................................................
58
Figure 3-9: BEOL plane structure.................................................................................59
Figure 3-10: BEOL comb structures. ...........................................................................
60
Figure 3-11: Grid test structures...................................................................................
60
Figure 4-1: Gate voltage sweeps at 1.8V VDS for all FEOL test structures, NMOS
and PMOS, for one row of a single test chip (728 structures total)...........64
Figure 4-2: Representation of chip-to-chip versus within-chip variation..................... 66
Figure 4-3: Orientation effect for NMOS and PMOS transistors..................................71
Figure 4-4: Orientation effect for NMOS and PMOS transistors with confidence
intervals for the mean.................................................................................
73
13
Figure 4-5: NMOS orientation effect on a chip by chip basis......................................74
74
Figure 4-6: PMOS orientation effect on a chip by chip basis. ......................................
Figure 4-7: Current difference between adjacent NMOS vertical-horizontal test
. 76
structures. .................................................................................................
Figure 4-8: Current difference between adjacent PMOS vertical-horizontal test
. 76
structures. .................................................................................................
(right)..................78
Figure 4-9: Poly finger spacing effect for NMOS (left) and PMOS
Figure 4-10: Mean(left) and normalized variation (right) in saturation current for
NMOS transistors with different number of polysilicon fingers. Statistics
for N=560 DUTs consisting of 16 replicates per chip, for 35 chips..........83
Mean(left) and normalized variation (right) in saturation current for for
4-11:
Figure
PMOS transistors with different number of polysilicon fingers. Statistics
for N=496 DUTs consisting of 16 replicates per chip, for 31 chips..........83
85
Figure 4-12: M OSFET cross section .............................................................................
Figure 5-1: VDS sweep for VGS ranging from 0-1.8V in 0.1V intervals.......................90
Figure 5-2: Semi-log plot of a VDS sweep for VGs ranging from 0 to 1.8 V in 0.1V
91
intervals, showing the limitation of our measurements. ...........................
V
in
0.IV
to
1.8
Figure 5-3: Semi-log plot of a VDS sweep for VGS ranging from 0
intervals. The opamp's ground voltage is set at -100 mV..........................91
Figure 5-4: Comparison between simulated and measured data for a VDS of 1.8 V,
ranging from 0 to 1.8 V in 0.1 V intervals, for eight replicates of one
93
type of transistor in one chip (N=8). .........................................................
Figure 5-5: Variation in NMOS currents at VDS=1.8V and VGS=1.8V, N=280 (8
replicates in 35 chips).................................................................................
94
Figure 5-6: Variation in PMOS currents at VDS=1.8V and VGS=0 V, N=248 (8
94
replicates in 31 chips).................................................................................
Figure 5-7: Relative current variation in NMOS transistors as a function of device
5
are a.................................................................................................................9
device
of
as
a
function
transistors
in
PMOS
Figure 5-8: Relative current variation
6
are a.................................................................................................................9
Figure 5-9: VGATE sweep for transistor in scan chain at VDS
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Of
0.1 V to 1.8 V, and
99
opamp ground set at -I00mV ...................................................................
5-10: Normalized variation (/[t) of the output current at different VGATE
values, for devices with different channel lengths. Measurements of one
test chip, N=176 (16 replicates of 11 different gate widths at a fixed gate
10 0
len gth ). .........................................................................................................
5-11: Variation of a simulated transistor. The variance is calculated from the
curve of a transistor in a typical simulation corner and another transistor
w ith a 5% variation in VT.............................................................................101
5-12: NMOS VT error-bar plots, ±1-y bars shown. N=480.................................103
5-13: Variation in NMOS threshold voltage........................................................106
5-14: Linearity of NMOS threshold voltage according to size............................106
5-15: PMOS VT error-bar plots, ±1-a bars shown. N=416..................................109
5-16: Variation in PMOS threshold voltage.........................................................112
5-17: Linearity of PMOS threshold voltage according to size.............................112
6-1: Measurements of interconnect test structures...............................................118
14
Figure 6-2: Capacitive loads to study automated simulation-based extraction tool
crossover capacitance extraction..................................................................123
Figure 7-1: Location of test dies within the wafer. Shaded squares indicate the dies
available for spatial measurement and analysis. ..........................................
Figure 7-2: Spatial mean currents (left) and normalized standard deviations (right)
per chip across wafer for NMOS 3-finger structure. N=32. ........................
Figure 7-3: Spatial saturation mean currents (left) and normalized standard
deviations (right) per chip across wafer for all NMOS of different sizes.
N = 5 2 8 ...........................................................................................................
Figure 7-4: Spatial saturation mean currents (left) and standard deviations (right) for
threshold voltage of NMOS transistors with 0.18 gm gate length. N=176.
Figure 7-5: Within-row spatial analysis for most replicated NMOS, showing mean
current values for the sixteen replicates per row for 35 chips. N=35. .........
Figure 7-6: Within-row spatial analysis for most replicated NMOS, showing 1-sigma
current values for the sixteen replicates per row for 35 chips. N=35. .........
Figure 7-7: Within-row spatial analysis for most replicated NMOS, showing
saturation current values for the sixteen replicates per row in a specific
chip . N =1 ......................................................................................................
Figure 8-1: Feedback implementation for technologies with high gate leakage
currents.........................................................................................................137
Figure 8-2: Revised NMOS and PMOS FEOL tiles........................................................139
Figure 8-3: Problem with FEOL switches.......................................................................140
127
128
12 9
129
131
132
134
15
16
List of Tables
Table 2-1: Opamp dimensions and specifications........................................................41
Table 2-2: Variation comparison between probing DUT directly and with the switch .... 45
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
45
2-3: Sw itch transistors sizing...............................................................................
3-1: Sizes of test transistors, NMOS and PMOS.................................................52
3-2: CBCM measurements capabilities...................................................................57
58
3-3: BEOL switch transistors sizing....................................................................
4-1: Bias conditions for layout dependent variation analysis.............................70
4-2: Tabulated orientation effect for NMOS and PMOS transistors...................71
72
4-3: Two-way ANOVA for NMOS with different orientation. .........................
4-4: Two-way ANOVA for PMOS with different orientation ............................ 72
4-5: Variances and variation for orientation test structures.................................77
4-6: Tabulated poly spacing effect for NMOS and PMOS transistors................78
4-7: Two-way ANOVA for NMOS with different finger spacing......................79
4-8: Two-way ANOVA for PMOS with different finger spacing.......................79
4-9: Variances and variation for polysilicon spacing test structures...................80
4-10: Tabulated poly spacing effect for NMOS and PMOS transistors..............82
84
4-11 :Variance ratios of NMOS multiple fingers structures. ...............................
84
4-12: Variance ratios of PMOS multiple fingers structures. ..............................
4-13: Variances and variation for polysilicon-fingers test structures..................86
5-1: Variances and variation in saturation current, VDS=VGS=1.8 V, for NMOS
97
transistors of different sizes, N=560. .........................................................
5-2: Variances and variation in saturation current, VDS=1.8 V and VGS=0 V,
98
for NMOS transistors of different sizes, N=496. .......................................
5-3: Tabulated NMOS VT calculation for devices of different sizes. ................... 104
5-4: Three-way ANOVA for NMOS threshold voltage........................................105
5-5: Variances and variation for V1 in NMOS transistors of different sizes.
10 7
N =4 80 ...........................................................................................................
5-6: Tabulated PMOS VT calculation for devices of different sizes.....................110
5-7: Three-way ANOVA for NMOS threshold voltage........................................111
5-8: Variances and variation for VT in PMOS transistors of different sizes.
1 13
N =4 16 ...........................................................................................................
capacitances.
measured
and
by
simulation
extracted
6-1: Comparison between
1 19
N = 5 60 ...........................................................................................................
6-2: Two-way ANOVA for comb capacitances made with different metal
12 0
layers. ...........................................................................................................
6-3: Variation (1-sigma/mean) in comb test structures. ........................................ 121
6-4: Variance ratios of coupling test structures.....................................................121
6-5: Two-way ANOVA for plane to plane test structures.....................................122
6-6: Two-way ANOVA for grid test structures.....................................................125
17
18
Chapter 1
Introduction
Aggressive technology scaling raises the need for efficient methods to characterize
and model circuit variation at both the front and back end of line, where critical
parameters such as threshold voltage and parasitic capacitance must be carefully modeled
for accurate circuit performance. This thesis addresses this need by proposing a test chip
that is capable of extracting parameters and distributions of transistors and interconnects.
This introductory chapter will first look at the motivation of our research in
Section 1.1. It continues by describing other work in the field in Section 1.2, focusing in
four main areas: dedicated test structures for variation extraction in a specific parameter,
ring oscillators to detect parameter variation by comparing frequencies, test circuits that
enable generalized measurement of analog characteristics, and a description of the charge
base capacitance methodology to measure interconnect parasitic capacitances. We present
the contribution of this thesis in Section 1.3, and in Section 1.4 we outline the structure of
the rest of the thesis. Finally, in Section 1.5 we summarize this chapter.
1.1
Motivation
The study of process variations has greatly increased in importance due to aggressive
technology scaling. Previous research has shown the substantial impact that process
variations in front end of line structures have in reducing yield in integrated circuits [1],
[2]. Robust circuit design depends on a more complete characterization of these
variations and their impact on circuit-level parameters, as the degradation in the precision
of device and interconnect parameters has elevated variability to a first order limitation to
continue technology scaling [3].
19
This thesis seeks to address this issue by developing a methodology capable of testing
a large number of front-end-of-line (FEOL) and back-end-of-line (BEOL) structures, and
modeling variations in threshold voltage and leakage currents, among other parameters.
This is achieved by designing and implementing test circuits that include a large number
of high performance devices (devices under test or DUTs) controlled by low leakage
switches and sensors to ensure a nominal bias condition at the DUT terminals. This
architecture is partially based on the test structure proposed by Lefferts [4]. By accessing
analog characteristics of a large number of DUTs, it is possible to gather the statistics
necessary to identify and model these variations, and prevent them from contributing to
performance failure. Through this we expect to provide a replicable methodology so that
the effect of variation sources may be quantified in different technologies.
This thesis studies variations in circuits due to the one of the fundamental sources of
variations in integrated circuits, as noted by Nassif [5]: physical factors (e.g. polysilicon
dimension variation) arising from the fabrication process. Physical factors can fall into
two categories: die-to-die physical variations and within die physical variations. Analysis
includes separation of spatial, layout dependent, and random variation components within
die and as a function of wafer location.
1.1.1 Our Previous Work
Our group has previously built a test chip to study the impact of layout dependent
variations on circuit performance [1]. The test chip consists of a range of differently
designed ring oscillator circuits which are made sensitive to some of the most common
and critical layout-dependent variations. Analysis of the ring oscillator output frequencies
enables assessment of variation impact at both the device (FEOL) level and interconnect
20
(BEOL) level. FEOL variations studied are dense vs. isolated polysilicon gates,
polysilicon finger proximity, global polysilicon density, orientation and others. BEOL
variations studied include parasitic coupling, fringing and planar capacitance, among
others.
The testing of the ring oscillator based test chip has proven successful for both device
and interconnect test structures. Different ring oscillator layout practices are seen to result
in significant differences in mean and standard deviation of measured ring oscillator
frequencies. Increases in variance of nominally identical structures due to layout practice
are ascertained with 95% confidence level tests on variance ratios. ANOVA is performed
to demonstrate that the means of different structures are different at a high (over 95%)
confidence. The FEOL structure analysis shows strong dependencies between the layout
practice and gate length variations: spacing between poly fingers can shift ring oscillator
frequency by 4.4%, and polysilicon density can change frequency by 2.1%. BEOL
structure analysis shows dependencies due to the metal geometry. Spatial analysis reveals
both a large die-to-die (within-wafer) trend, and systematic within-die spatial patterns for
particular test structures.
The analysis of the ring oscillator test chip shows several areas where improvements
are needed. For example, threshold voltage variations were suspected but not proven or
quantified for the FEOL structures. A means to identify specific device variations which
cause circuit variation is needed. In addition, BEOL structures need an improved
technique for measurement so that we can improve accuracy and separate interconnect
capacitance components, in order to characterize interconnect variations. In this thesis we
target these and other issues inspired by the analysis of our previous test chip.
21
1.2
Review of Test Structures from Literature
Semiconductor device or circuit test structures have been in use since the 1960's [6],
with publications dating back to 1974 reporting the use of test structures to accept or
reject wafers. Research in the area of characterization of technologies using more
efficient methods than probing each transistor independently has increased greatly in the
last few years [6], likely due to the non-idealities of device models because of the
aggressive scaling that the semiconductor industry has kept following Moore's Law [7].
Broadly speaking, three approaches can be identified for front end of line variation
analysis. In the first family of structures, dedicated test structures or circuits focus on an
extraction of variation in a specific parameter of substantial importance, such as
MOSFET threshold voltage. These test circuits are often large arrays to gather the
statistics necessary and identify variation dependencies. A second approach is to use ring
oscillators as the test structure, and study ring oscillator (RO) frequency variation in
structures that are made to be more or less sensitive to particular layout or device
parameters. These RO test structures may be used in large arrays, or may be small
enough that they can be distributed as monitors in scribe lines or within product chips.
Finally, the third test circuit family seeks to enable generalized measurement of device or
interconnect response, using pad sharing or on-chip digitization approaches.
In the following subsections, we illustrate each of these three approaches with
examples from the literature. The work presented in this thesis pursues the third
approach, to enable the relatively rich characterization of a large number of test devices
through current-voltage (I-V) measurements using a scan chain based pad sharing
architecture. The fourth subsection illustrates a methodology to measure interconnect
22
parasitic capacitances, which we also implement in this thesis.
1.2.1 Dedicated Variation Test Structures
There has been extensive work through many years to model variation in front end of
line (FEOL) devices. The accurate modeling of the variation in these devices is important
to quantify design corners and not over- or under-estimate worst case scenarios, both
within chip and between chips [5]. In this section we present a few examples of these
types of test structures, all focusing on a specific variation extraction.
Force drain
-
Force gate (V)
IP
1
V.
MUT
Device
Array -
-w
.
HE
k
_d
d
T
HE
----*-------------
---- - -
Source fdlower
sense drain
Figure 1-1: Agarwal et al. VT mismatch test structure [8].
Agarwal et al. [8], [9] have modeled mismatches between adjacent SRAM devices,
concluding that the large variations observed in the extracted threshold voltage statistics
indicate that the random dopant fluctuation is the reason behind mismatch in the adjacent
devices. Their further research [10] includes a test chip to measure threshold voltage
mismatches of adjacent transistors. The structure is described in Figure 1-1. Once a row
and column is activated, the applied current IDS flows through the device under test, and
the threshold voltage shift of the device is measured by sensing the corresponding source
voltage through the sense source line. This technique is powerful because the mismatch
can be measured with a single measurement, but the reference VT (which is only one
23
device) must be fully characterized beforehand.
Drego et al. [11] designed a highly dense test chip also, to measure scattered VT
variation. With approximately 140,000 transistors, their structure can map variations in
threshold voltage by comparing two currents, with which they can extract the needed
parameters to isolate AVT in subthreshold, taking advantage of the subthreshold current
characteristics where AVT can be dominant. One may also characterize the actual VT
value of one device per chip for chip-to-chip comparison of AVT.
1.2.2 Ring OscillatorVariation Test Structures
A ring oscillator continues to be an attractive type of test structure because of its
simple implementation and single output. Back in 1984, Cassard [12] presented a ring
oscillator test chip to measure within chip and chip-to-chip variation, and compared these
test results with SPICE simulations. The test structures were accessed using a probe card,
and the experiments were able to conclude that the polysilicon gate width was indirectly
proportional to the frequency and was the primary cause of the frequency variation.
Cassard also concluded that intra-chip parameter variations can influence SPICE
sensitivity. Today ring oscillators are a commonly used test structure, as they only require
one (start up) or no (self oscillating) input signals and can provide a simple frequency
readout. A ring oscillator can be easily digitally controlled, making it a prime candidate
for a large array, such as we did in our previous work [1].
Bhushan, Ketchen et al. [13], [14], [15], have done extensive work using ring
oscillators to identify the effect of variations in a number of specific MOSFET
parameters. The measurements represent an average of hundreds of identically designed
MOSFETs, therefore being resistant to random statistical fluctuations in the parameters
24
of isolated single MOSFETs. For example, part of their work [14], [15] includes a test
chip capable of isolating AVT. The circuit schematic of a single stage in the RO is shown
in Figure 1-2. The full ring oscillator includes four of the stages pictured in Figure 1-2
and a two-input NAND gate as an enable, for a total of five stages. The structures were
placed in scribe lines, not consuming any of the area already reserved for non-test chips
in the wafer. The delay of the passgate is strongly modulated by threshold voltage, and,
because of sizing, the switching delay is designed to be highly sensitive to the
characteristics of the passgate. The variation of threshold voltage can then be obtained by
measuring the difference in frequencies among several ring oscillators. This is an
efficient method of modeling AVT as there is no need to individually characterize any of
the individual devices. However, we can only gather the variation out of it, and not an
actual threshold voltage value.
PFET Keeper
NFET
Passgate
Inverter
Load
Figure 1-2: Bhushan, Ketchen at al. ring oscillator stage to measure AVT [14].
The work from Bhushan and Ketchen extends to ring oscillators beyond standard
MOSFET dc characterization [16]. They also use ring oscillator test structures that
perform in the multiple GHz range, so that they are representative of today's
microprocessors. With various ring oscillator designs they can measure a range of
parameters, from resistance distributions to sub-picosecond delay measurements, all with
25
simple 1/0 requirements so that they are compatible with standard in-line parametric
testers.
Pang et al. [17] designed, implemented and tested a test chip similar to our previous
work as presented in Section 1.1.1, with ring oscillators that enhance variation due to
layout practices. The delay in the ring oscillators is characterized through the spread of
ring oscillator frequencies and the transistor leakage is measured by using an on-chip
analog to digital converter, which enhances the test structure ability when compared to
[1]. With these functionalities they are able to conclude that regular layout reduces the
systematic layout-dependent process variations, something that was not captured by
automated simulator extractors.
1.2.3 Methods to Extract Full I-V Curves
In the previous subsections we highlighted the importance of using test structures to
extract variation. However, because they focus on variation in specific device parameters,
those test structures are not able to provide full analog I-V curves, and only a few or no
parameters can be measured from them. Other test structures, like the one presented in
this thesis and the ones described below, can gather enough analog characteristics to not
only measure variation in a test chip (due to large repeatability), but also extract the set of
parameters needed to generate models for the transistors.
Quarantelli et al. [18] proposed a test structure based on transistor arrays, as seen in
Figure 1-3. The structure is small to minimize the effect of inter and intra die variation.
The structure consists of columns of transistor arrays, with multiplexed gates and shared
sources throughout the entire structure, and shared drains per column. The rows are
multiplexed by a self-resetting scheme controlled by off chip circuitry. Saxena et al. [19]
26
built the proposed structure to analyze layout induced variation, for example, proximity
between polysilicon fingers in stacked gates. They analyzed the I-V characteristics at
only a few critical points: off state current, drive current and threshold voltage. They
successfully measured and analyzed this data and arrived at conclusions on layout-based
variation consistent with [1]. The structure provides a good assessment of layout induced
variation, but it utilizes off chip control circuitry and the data gathering is limited to a
given number of bias conditions.
Col #1
-
CoI#2
CoI#3
CoI#4
1A
Row #2
I
022
CI
aX
CD
LRo
Reset__
#32F
t
CLK
Figure 1-3: Transistor array test structure proposed by Quarantelli et al. [18].
Lefferts et al. [4] proposed a test structure architecture to characterize and monitor a
CMOS 0.25 gm technology process. Their objective was to do this in a small area so it
could fit in scribe lines, and avoid using the area reserved for non-test chips in the wafer.
Lefferts' 0.25 jim test structure architecture consists of 340 test devices controlled by 14
probes, as seen in Figure 1-4. The probes provide access to the drain and source voltages
of the DUTs, and to guarantee accuracy in testing they both have full Kelvin connections
to eliminate the IR drop down the long test row. Testing was performed using an off chip
27
semiconductor analyzer for the drain current measurement and voltage sensing, and an
off-chip operational amplifier (opamp) ensured a desired drain voltage (nominally
ground).
4-
14 Probe Paas
0 000
-p
75 Devices
-
-
0 0 0 0 3 00O
DUT
09*
On Probe Card
Figure 1-4: Lefferts architecture [4].
With his test structures, Lefferts successfully modeled both device and interconnect
variation, with accuracy that goes beyond conventional test structure testing because of
the Kelvin sensing. However, the several off-chip elements needed to perform the testing
make this architecture inconvenient to the user. In addition, the design of the switch that
turns the devices on and off is not disclosed.
Wang and Shepard [20] designed a test chip to gather full analog characteristics onchip and with on-chip current measurements. They built a prototype in 0.25 Im
technology as proof of concept, where they were able to measure currents in both
saturation and sub-threshold for a given voltage range. This type of test structure
architecture is powerful because they are able to do on-chip current measurements, but it
is quite complex because of the additional circuitry needed for the current measurements.
1.2.4 Method to Measure and Model Interconnects
Physical sources of variation also include wire or interconnect variations. Nassif [5]
28
---
Nxa-
__
-
____
- __
__ -
Mwmffl
- ---
concludes that wire variations are expected to increase in importance dramatically in
future IC technologies, and appropriate methods of modeling these variations must be
developed to keep up with technology scaling. Proper characterization of interconnects is
increasingly important as technology scales, as interconnects are increasingly affected
with scaling [21], and this can give rise to timing errors, voltage degradation and other
problems likely to affect both analog and digital circuit design. Charge-based capacitance
measurement (CBCM) techniques [22] provide sufficient accuracy to model many of the
interconnect sources of variation.
NWELL
VDD(No Cap)
AL
VDD (Cap)
A'
V2
V1
Figure 1-5: CBCM structure [22].
Chen et al. [22] describe the CBCM structure, pictured in Figure 1-5, as follows: the
structure on the left is identical to the one on the right in every manner except that it does
not include the target capacitance to be characterized. Both structures are driven by two
non-overlapping signals. When the PMOS transistor turns on, it will draw charge from
VDD to charge up the target interconnect capacitance. This amount of charge will then be
subsequently discharged through the NMOS transistor into ground. By measuring the
29
current at the source of the PMOSFET, the DC value of this charging current can be
measured. The difference between the two DC current values is used to extract the target
interconnect capacitance, determined by I'-I=Inet and Ine =C
Vdd-f,
where C is the target
capacitance andf the frequency in which the structure charges and discharges.
The CBCM technique has been extended to a fully differential approach and
implemented by [23], [24], and [25]. We use the differential method in this thesis, and its
design and implementation are explained in Section 3.2.1.
1.3
Thesis Contributions
The contributions of this thesis focus in two main areas: the design of a test structure
capable of efficiently gathering analog characteristics of devices and interconnects, and a
statistical methodology to study variation for both devices and interconnects.
In order to address need for variation analysis of large sets of data to properly model
distributions of devices and interconnects, we propose a test circuit that can access output
currents and provide a range of input voltages to a number of devices under test. The
devices under test are accessed using a scan chain approach, which use low leakage and
low variation the switches to turn the DUTs on or off. This allows us to share terminals of
the DUTs and therefore save considerable chip area. The devices will not be probed
directly, and therefore we need to assure that their terminals are at the nominal voltage
we intend them to be. For this we implement Kelvin sensing, so that the intended voltage
at the terminals of the DUT is the desired one. The architecture is flexible enough to
allow us to measure both front and back end of line test structures. FEOL test structures
focus on typical design issues (e.g. orientation) and different sizes, and BEOL test
structures focus on interconnect capacitances, which allows a rich set of data that enables
30
us to perform various types of variation analysis.
The variation
analysis uses methodologies
including ANOVA
and variance
confidence interval ranges to identify which design practices or parameters can affect
circuit performance the most. We also separate the impact of inter and intra die variation
using nested variances, to not overestimate the chip to chip variation. Spatial analysis to
map wafer and die trends are also accomplished. With the analysis and the large sets of
data one can identify variation sources, quantify circuit impact, and specify layout
practices for variation minimization.
These contributions are distributed across the thesis, the organization of which is
described in Section 1.4.
1.4
Thesis Outline
This thesis work focuses on creating a test chip methodology that can efficiently
model both device and interconnect variation, its implementation, testing and analysis. In
Chapter 2 we describe the architecture of the test chip, including the building blocks of
the test chip (tile, row and chip), design of an on-chip Kelvin sensing methodology, and
low leakage switches. Chapter 3 describes the test structures that are implemented in the
test chip, including both front and back end of line. In Chapter 4 we present the testing
results and analysis of the front end of line test structures that focus on layout induced
variation, including a description of the statistical analysis that is used throughout the rest
of the thesis. Chapter 5 also includes testing results and analysis, but in this case focusing
in variation due to the sizing of transistors. Chapter 6 focuses on the testing results and
analysis of the BEOL test structures, and Chapter 7 on within-die and within-wafer
spatial analysis. In Chapter 8 we offer suggestions for the implementation of the test chip
31
methodology in other technologies. Conclusions and other suggestions for future work
are presented in Chapter 9.
1.5
Summary
In modem integrated circuits it is becoming increasingly important to detect and
model process variations for critical parameters, at both the front and back end of line.
This thesis contributes a methodology to gather full I-V curves for transistors and to
measure interconnect capacitances using a differential CBCM approach, to not only
model variation, but also extract device parameters. In this chapter we summarized and
commented on the features of several different types of test structure architectures. With
our design we intend to take advantage of the positive features that these architectures
have taught us and contribute new extensions to the methodology for variation test
circuits and variation analysis. The following chapter describes the architecture of this
test chip, and further chapters discuss the analysis of our methodology and its test
structures.
32
Chapter 2
Test Chip Architecture
The architecture for the test chip, referred to as the "Analog Multiplexed
Characteristics" chip, or AMC, is designed similar to the V-2 chip as in [1] and [2],
emphasizing hierarchy, regularity, and repetition in a scan chain approach. This approach
helps to transfer the test chip design to other technologies using automated tools. The
hierarchical approach of the test chip also allows the user to choose pieces of it
depending on the area they have available or other limitations. This chapter describes the
architecture of the test chip, including a description of the methodology used
(Section 2.1), and its building blocks: the tile (Section 2.2), row (Section 2.3) and the
overall chip (Section 2.4). Two of the most important parts of the design are the
implementation of low variation switches that turn the Devices Under Test (DUTs) on
and off, and the implementation of a feedback network that allows the user to generate IV curves without having to probe the drain voltage of each DUT. Section 2.5 describes
the feedback network, while Section 2.6 explains in detail the design of the switches.
Simulations results are shown in Section 2.7, and an overall summary is presented in
Section 2.8.
2.1
Methodology
This work contributes a methodology to effectively model and characterize IC
fabrication processes by measuring test structures using an architecture that multiplexes a
small number of pads to measure a large number of devices under test. The DUTs are
composed of front-end-of-line structures (MOSFETs) and interconnect structures
attached to charge-base capacitance measurement (CBCM) structures. The architecture is
33
based in part on Lefferts' test chip architecture [4], and on our previous scan chain based
architecture [1], [2].
Traditionally, detailed device I-V measurements are obtained by connecting each
terminal to a pad, from which the appropriate signals and/or measurements will be
applied, as illustrated in Figure 2-1 (a). This results in large amounts of wasted area in the
test chip.
The proposed methodology, illustrated in Figure 2-1 (b), uses a small number of pads
for an entire row of test structures. The test chip has 1456 FEOL structures and 672
BEOL structures, for a total of 2128 structures, all controlled by 33 pads, and the user is
still able to gather traditional DC analog characteristics. The chip is composed of mainly
three building blocks: the tile, row, and chip blocks. Each of these are described in detail
in the subsequent sections.
(b)
(a)
Figure 2-1: Traditional (a) method of testing vs. proposed (b).
2.2
Tile
The tile sub-block is the basic building block of the chip. There are two different
types of tiles, the FEOL tile and the BEOL tile.
Each of the FEOL tiles contains a DUT, switches, and a flip flop (DFF) that works as
part of a scan chain, as shown in Figure 2-2. A shift register controls the switches that
34
turn the DUT on or off. The output of the DUT is wired to the output bus through a
switch. Section 2.6 describes the design and implementation of the switches, to obtain
low variation and low resistance control of each DUT.
Vgate
Switch
en /en
Output/Ground
Switch
en /en
Data
Scan Clock
-
en
Reset
Figure 2-2: Tile block diagram for FEOL test structures.
Each of the FEOL tiles has the following input signals: scan-clock (the clock for the
shift registers), data signal (the control signal for the DFF), reset (resets the registers),
Vgate (gate voltage controller for DUT), and power. Each tile has one overall
ground/output bus signal.
Vii
Switch
V2i
Switch
neti
netj
Switch
Vlj
Switch
V2j
en /en
en /en
Output/Ground
en /en
Data
Scan Clock
D
>
Q -en
-/en
Reset
Figure 2-3: Tile block diagram for BEOL test structures.
35
The BEOL DUTs have a different tile because its implementation requires many
more switches, and the area must be bigger because of the metal capacitance structures
that are attached to them. Figure 2-3 shows a block diagram of the BEOL tile.
Each of the BEOL tiles has the following input signals: scan-clock (the clock for the
shift registers), data signal (the control signal for the DFF), reset (resets the registers),
four different Vgates (gate voltages controller for CBCM structure), and power. Each
BEOL tile has have one overall output bus signal.
FEOL Tile
BEOL Tile
Figure 2-4: Tile layouts.
Figure 2-4 illustrates the layout of the tiles. The FEOL tiles have separate supply
voltages for DUT, switches and DFF, and separate ground lines for the switch and DFF.
The dimensions of the switches are 15 gm wide by 12 gm tall, the ones for the DFF are
16 pm wide by 6 gm tall, and the overall FEOL tile measures 18 gm wide by 21 jim tall.
36
The BEOL tiles also have separate supply voltages for the CBCM structure, switch and
DFF. There are separate ground lines for the switch and DFF, and four separate gate
voltage lines to control the CBCM structure. The overall BEOL tile measures 18 gm
wide and 40 gm tall. The wires that complete the BEOL DUTs take the entire space of an
additional tile.
2.3
Row
A horizontal chain of tiles comprises the row sub-block. This array is shown in
Figure 2-5.
Tile
Output/Ground
Vsupply
Fdck
Feedb-ack
-
Vgate-~
Scan Clockp
Reset
Figure 2-5: Row block diagram.
Each row has a feedback network in order to compensate through Kelvin sensing for
the losses in the power line. There is a feedback network for the power and one for the
ground line. The feedback network for the power line is entirely on chip, and its
implementation is explained in detail in subsequent sections. The feedback network on
the ground line is implemented off chip because the instrumentation needed to take
current measurements (ammeter synchronized with Labview software) has a large input
capacitance that would make our designed on-chip circuitry unstable.
The FEOL and BEOL rows are different because BEOL rows need more signals to
control the switches of the CBCM structures. There are two FEOL rows in the chip.
There are 728 FEOL tiles in a row, including eight blank tiles to prove the functionality
37
of the scan chain. The row is subdivided in eight sub-rows. Each sub-row is of the
horizontal length of the test chip (except for pad area) and contains one of each of the
unique FEOL structures. All FEOL structures are repeated eight times per row (the three
finger, minimum spacing test structure is repeated 16 times). The order in which the tiles
are placed per sub-row varies, for a broader spatial analysis.
There are two BEOL rows on the chip, each with eight sub-rows, as in the FEOL
case. These sub-rows have 42 tiles each, and they are about as long as each FEOL subrow. Each BEOL DUT is repeated three times per sub-row. As in the FEOL case, the
order in which the tiles are placed per sub-row varies, for a broader spatial analysis.
Appendix I lists the sequence of test structures in each row. Appendix III shows screen
shots of the layouts of both the FEOL and BEOL rows.
2.4
Chip
The chip is simply four rows put together: two FEOL and two BEOL rows,
intercalated as in Figure 2-6. Each chip can access 2128 test structures. We received 35
individual bonded chips in 40-pin ceramic DIPs, for a total of 74,480 tiles accessible in
our set of packaged chips. We also received five un-bonded chips, for a total of 10,640
tiles that are accessible by a probing station.
Tile
Figure 2-6: Chip block diagram.
The fabricated chip for the 0.18 gm CMOS logic process is shown in Figure 2-7. The
38
measurements of each die are 3 mm x 2.33 mm.
Figure 2-7: Die photo of full test chip.
2.5 Feedback Implementation
The power lines to control the power supply and ground voltages of the test rows are
long, as they go from one end of the test chip to the other. The lines are parallel
connected for each sub-row in order to minimize losses in the lines; however, a Kelvin
sensing approach will yield more accurate voltages for the desired DUT. This is critical
in this architecture, as the power voltage can not be directly measured for each DUT, but
its value must be known accurately in order to create IDS vs. VDS and vs. VGS curves, and
other analog characterizations. Figure 2-8 shows the feedback network needed in order to
keep the desired voltage accuracy.
39
--
Vref
..
VdasIrain
.. t
Vdrop
Figure 2-8: Feedback network for VDD regulation.
The goal is to achieve the following:
Vdrain(s)
a(s)
(s
1+ a(s)
Vej(s)
Vdra-(S)
Vdrop(s)
1 for very large a(s)
(2.1)
1
0 for very large a(s)
1+ a(s)
(2.2)
For this one can use an operational amplifier, as illustrated in Figure 2-9.
I
a(s)
Vref
Vdrain
td
Vdrop
I ~0A
Power Supply
VGATEr
----------------- A
Off chip due to large cap.
o on Ammeter
mee
Figure 2-9: Feedback implementation.
2.5.1 OperationalAmplifier Design
The operational amplifier (opamp) used in the feedback network is a classic two stage
differential-pair and common source amplifier, with an output buffer to provide the
necessary current for the DUTs. The architecture of the opamp is shown in Figure 2-10
[26].
40
4
Qbia s
IQ5
I
Q6
I
LL
Q8
V]
Q1
Q2
I+
A
Rbias
Out
Cc
Qc
Q3
Bias
Diff Input
Q9
7
Q4
CS Gain
Out Buffer
Figure 2-10: Opamp architecture.
Thick oxide transistors are used to minimize variation and glitches in the opamp, and
also to provide high enough voltages in the output to drive the DUTs to 1.8V. It has to be
carefully designed to provide as much current as the DUTs will need, while staying stable
and minimizing offsets. The opamp is sized in order to fulfill these conditions, as shown
in Table 2-1.
Transistors
Q1, Q2, Q5, Q6, Q7, Qbias
Q3, Q4
Q8, Q9
Qc
Other specifications
VDD
Vss
Cc
Rbias
Dimensions
Width [pm]
24
12
600
Length [pn]
0.4
0.4
0.4
1
0.4
Values
3.3 V
0V
200 fF
4.15 KQ
Table 2-1: Opamp dimensions and specifications.
41
10K
0
0)
Ao Max = 3.35K
1K-
100
10
-A
180
160
CL
(I)
0
140
120
100
on
Unity Gain Phase Margin:
56.60
60-
1
10
''100O
K 100K
Frequency (log) [Hz]
1M
lOM
Figure 2-11: Opamp frequency response.
The opamp has a maximum gain of 3.3K, and phase margin of 56.6 degrees, as
shown in Figure 2-11. The frequency response is important to ensure correct functionality
in the feedback network. A phase margin near 600 provides the stability needed for
feedback. The closer to 600, the faster it will settle in time and the less ringing it will
suffer. Figure 2-12 illustrates how quickly the designed (simulated) opamp settles and
how little ringing it shows.
2.0
1.8
1.6
>
1.4
& 1.2
-
0
1.0
0.8
0.6
0.4
0.2
0
0
500n
lu
Time (s)
1.5u
2u
Figure 2-12: Step response of the opamp.
42
The large size of the input transistors minimizes problems with mismatch and
potential offsets. The large output buffer provides the currents that the DUTs need to turn
on all the way to full saturation.
2.6 Implementation of Low Leakage Switches
In this design, low leakage switches turn the DUTs on and off in a precise manner, so
that the input and output signals of the DUTs can be shared. New technologies have low
and sensitive threshold voltages, and to assure a DUT on and off state it must be
controlled by robust circuits. The switches designed here achieve both low variation and
low resistance, to minimally perturb the DUTs. The switches for the FEOL test structures
are expected to manage a large range of currents, from sub-threshold to saturation. This
design is based in part on concepts by Lefferts [27].
/en
en
/en
en
/en
VGATE
VGATE
en
/en
VREF
en
en
VREF
/en
VREF
Figure 2-13: Low leakage switch (left), when enabled (center) and when not enabled (right).
The switches are built with thick oxide, high VT devices to minimize their variation,
and they follow the schematic shown in Figure 2-13. When enabled, the gate of the DUT
accesses the voltage VGATE through a transmission gate, and the source connects to
ground, which also functions as an output bus. When not enabled, the gate connects to
ground and the source connects to the reference voltage of the opamp, double ensuring
that the DUT will be off by grounding the gate and short-circuiting the drain and source.
The drain of the DUT is connected to the output of the opamp at all times.
43
A problem with these simple switches is that when large amounts of currents go
through the drain, the "on" resistance in the switch that connects the source connection to
ground results in a small voltage offset from the ground potential, perturbing the bias
condition from the desired state. As a result, the output current can be different than if it
had been measured by probing directly. This is diminished by enlarging the gate width of
the switch device, as shown in Figure 2-14. This transistor was made as big as possible as
long as it could still fit within the tile (i.e., not be wider than the control block), as shown
in Figure 2-4.
/en
VGATE
9en
.i1 .)VGATE
.
.
.
en
/en
VREF
Figure 2-14:
RON
resistance for enabled switch.
Any variation in the switch could also possibly have an effect on the variation
observed in the DUT measurement. Using high VT (thick gate oxide) and large devices in
the switch, this variation can be minimized. Table 2-2 illustrates this by comparing
simulation results on the variation observed when the DUT experiences VT variation and
it is not connected to any switches ("Variation DUT probed directly" column), and when
the DUT is connected to the switch and the DUT has no variation but the switch does
("Variation Switch" column).
As shown in Table 2-2, when the devices that form a specific DUT (NMOS of
minimum length, in this case) have their nominal VT varied by, for example, 20%, its
standard deviation of the output current is of 39.4 gA When the devices of the switch
44
have their VT varied by the same amount (and the DUT has its nominal VT value), the
effect of variation is about 130 times less, with a standard deviation of the output current
of 0.3 gA.
VT
DUT
probed directly [pA]
a Switch WA]
+20
3.94E-05
3.OOE-07
-20
4.11E-05
2.36E-07
+10
1.99E-05
1.17E-07
-10
2.03E-05
1.87E-07
+5
9.97E-06
5.13E-08
-5
l.OlE-05
5.13E-08
% Change
Table 2-2: Variation comparison between probing DUT directly and with the switch
The sizes of the transistors in the switch are shown in Table 2-3, following the
schematic of Figure 2-15.
I kJ
Q[
1
Q2 Q3
Q4
5Q6
Figure 2-15: Schematics for low leakage switch.
Transistor
Q1
Q2
Q3
Q4
Q5
Q6
Gate Width [im
2
2
2
100
2
2
Gate Length [pm]
0.35
0.30
0.35
0.35
0.30
0.35
Table 2-3: Switch transistors sizing.
45
2.7 Simulation Results
Simulations of the current at the Ground/Out node of a row tile, composed of an
opamp, 727 "off' tiles and one NMOS "on" tile (consisting of a DUT of a single finger
gate with W/L=0.50 gm /0.18 pm) are shown in Figure 2-16. We see that the design is
capable of gathering a wide range of IDS-VDS curves for a given DUT. When comparing
these measurements to the traditional method of probing the individual NMOS transistor,
the plot shows how the test DUT closely mimics the traditional method.
3.5
x 104 Simulated Data: DUT in Row vs. NMOS Alone
-e-.
3-
DUT in Row
SNMOS Alone
2.52-2-
1.5-
00
0
-0.5
0
0.5
1
1.5
2
VDS [V]
Figure 2-16: Simulated data VDS sweep for NMOS 0.50 pm /0.18 gm device.
In Figure 2-16, the "DUT in Row" curves refer to the curves taken by simulating the
circuit shown in Figure 2-17, plotting the current through the "Output/Gnd" line as the
"lout" current and the voltage between "Power Supply" and "Output/Gnd" as the "Vds"
voltage. The signals shown, "Power Supply," "Vgate," "Data," "Scan Clock," "Reset,"
46
"VddSwitch," "VddCtrl," "GndCtrl," and "Output/Gnd" are controlled off-chip. The
short circuit between VddSwitch and the Power Supply is also made off chip.
POWER
SUPPLY
Vgate
Data
Scan Clock
Reset
VddSwitch
Vdd Ctr
Gnd Ctri
On
Tile
Off
Tile
Off
Tile
Off
Tile
Off
Tile
Off
Tile
Output/Gnd
Figure 2-17: Model for simulation of row.
The "NMOS Alone" curves refer to those simulated by simply sweeping the voltages
of a single NMOS W/L=0.50 [tm /0.18 pm device in Spice, with each terminal connected
to a specified supply, as shown in Figure 2-18, mimicking the traditional method of
probing a transistor with a separate voltage probe per terminal.
VSUPPLY
VGATE
Output/Gnd
Figure 2-18: NMOS probed alone.
There are some limitations in the on-chip voltage control for DUT measurement.
First, the opamp cannot provide a full output swing because of the output buffer.
Figure 2-19 illustrates how 100 mV is our limit for VDS voltage sweep. This simulation
includes a single "on" tile (an NMOS with dimensions 0.50 gm /0.18 pm), and 727 other
"off' tiles. The leakage current of these off tiles is approximately 2 nA, and Figure 2-19
illustrates the second limitation: it is not possible to accurately measure currents less than
47
this 2 nA limit. However, 2 nA currents and under only occur at the very lowest bias
voltages, and we are able to gather the majority of desired I-V characteristics despite
these two known design limitations.
Simulated Data: DUT in Row vs. NMOS Alone
-2
10
10
-
10
--
0
10
-
10
10
AAAAAAAAAn,
102
10
00.1
0.5
1
Vds [V]
1.5
2
Figure 2-19: Simulated opamp limitations for NMOS 0.50 pm /0.18 pm device.
The functionality of the scan chain is also tested using a model like that in
Figure 2-17, but with three tiles with devices of size: 1.75/0.18, 1.75/0.36, and
1.75/0.54 tm. Figure 2-20 shows that when the Data-in signal is high at the falling edge
of the clock, the first tile will be turned on. If the Data-in signal is low by the next fall of
the clock, then the first tile turns off and the second one turns on. Had the Data-in tile
stayed high, then both tiles would be on. The process repeats at every falling edge of the
clock until all tiles are addressed.
48
Scan Chain Functionality
1.2m
Tile 1
800U
600u
400u
Tile 3
200u
0_1.8-
I
I
I
I
1.6 1.4-
G)
1.2 ~
1.00.87
0
0.6
0.4
0.2
I
I
I
I
I
I
I
I
I
I
------ Data In
Clock
-
00
1OOm
200m
Figure 2-20: Scan chain functionality.
In the test chip there are a number of "blank" tiles, or tiles with no DUT in them, to
test the functionality of the scan chain, by verifying that no current is measured at the
expected blank tile point in the control sequence.
2.8
Summary
The analog multiplexed characteristics test chip, or AMC, is composed of three main
building blocks: the tile, row, and chip blocks. The tile includes a device under test
(DUT) that is connected to low leakage switches in both the gate and drain terminals,
which are carefully designed to ensure the on and off states of the DUTs. The tile also
includes control circuitry (scan chain) to open and close the switches. A row is a group of
tiles, with an on-chip Kelvin sensing feedback system to guarantee the drain voltage that
each DUT receives. The chip is the group of all rows, and there are four rows per chip:
two front end of line rows and two back end of line rows. Each FEOL row has 728 tiles,
and each BEOL row has 42 tiles each, for a total of 2128 test structures per chip. The
49
chip was fabricated using a 0.18 pm CMOS logic technology, with 35 packaged chips in
40-pin ceramic DIPs, for a total of 74480 tiles accessible by measurement of packaged
chips. The devices under test implemented in these tiles are described in Chapter 3.
50
Chapter 3
Test Structures Description
One of the advantages of the analog multiplexed characteristics test chip is that its
architecture is generic enough to include a large array of test structures as devices-undertest in its tiles. This chapter describes the particular DUTs implemented in this test chip.
The design of experiments for this test chip include transistors that are designed to
accentuate one source of variation, in order to extract that variation and link it to circuit
performance, and also transistors of different sizes from which parameters like threshold
voltage can be extracted. Section 3.1 describes these structures, while Section 3.2
considers back-end-of-line, or interconnect dominated test structures. Section 3.3 is an
overall summary of the test structure design of experiments.
3.1
Front End of Line Structures
Front end of line, or FEOL, test structures include an array of different NMOS and
PMOS transistors designed to provide information about the behavior of a device at
different bias conditions, and to model variation due to different layout practices, as in
our previous work [1]. The FEOL structures are divided into those with different sizes,
different orientation, different spacing between polysilicon fingers and different number
of polysilicon fingers.
3.1.1 NMOS and PMOS Structures of Different Sizes
An array of NMOS and PMOS transistors of different sizes provides information on
how much variation affects a transistor given its size. The set of different size devices
also enable one to extract parameters such as threshold voltage, as a function of channel
length, width and area. The concept of these structures is shown in Figure 3-1.
51
i
U
Eli Im
LmI
U
U
U
U
IIIIIIIIIIIIIIII
Figure 3-1: Different size FEOL test structures, with different channel lengths (L) and widths (W).
The gates of all the size dependent transistors are single-fingered, and the sizes vary
as shown in Table 2-3. There are 33 different sizes, for a total of 66 DUTs (33 NMOS
and 33 PMOS). There are three different gate lengths (minimum, twice minimum and
three times minimum), and 11 different gate widths (from 0.50 gm to 3 gm in 0.25 gm
increments).
DUT
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Width
Lengt
DUT
Width
Lengt
DUT
Width
Lengt
[p[
h [pm
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
Q12
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
[
]jm
Q13
Q14
Q15
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Table 3-1: Sizes of test transistors, NMOS and PMOS.
3.1.2 Orientation
Variation in direction dependent fabrication processes can be captured by varying the
orientation of how the DUTs are laid out. The orientation test structures are identical
52
transistors laid out vertically and horizontally, as shown in Figure 3-2. Only the DUTs are
placed in different orientation; the rest of the tile, including the switches and control
circuitry, is always laid out with the same orientation (vertical). All orientation DUTs
have a gate length of 0.18 gm and gate width of 1 ptm. There are four different structures
in this category, two PMOS (one vertical and one horizontal) and two NMOS (one
vertical and one horizontal). The pair of identical vertical and horizontal tiles are laid out
side by side in the rows of the test chip to compare their behavior with minimum spatial
impact.
Vertical
Horizontal
Figure 3-2: Orientation FEOL test structures.
3.1.3 Polysilicon Spacing
Variations due to lithography proximity can be studied by varying the distance
between the polysilicon fingers of the gate of a transistor. The concept is shown in
Figure 3-3. The distance between the fingers in these three-fingered structures are
minimum spacing, 1.2x minimum, 1.5x minimum, and 3x minimum, similar to the
structures in [1]. The dimensions of each finger are 0.5 gm/0.18 gm. There are eight
structures in this category, four PMOS and four NMOS. The total drain to source
resistance in these structures is kept constant (i.e., the distance between the drain and
source contacts is kept constant), as shown in Figure 3-3, to minimize impact on output
currents.
53
Figure 3-3: Poly finger spacing FEOL test structures.
3.1.4 Number of Polysilicon Fingers
Transistors with different numbers of polysilicon fingers are laid out with the same
effective gate length, but with the gate distributed across a different number of
polysilicon fingers, as shown in Figure 3-4. These structures should have the same
nominal current, if we neglect the device stack effect. The distribution of the gate length
into different numbers of polysilicon fingers accentuates variation due to gate length
variation, since AL may be x-times present in x-fingered transistors.
Figure 3-4: Number of poly fingers FEOL test structures.
There are a total of 12 structures in this category, six PMOS and six NMOS. These 12
test structures are divided into four different groups. The first group are NMOS
transistors with gate widths of 0.50 gm and total gate lengths of 0.54 gm. There are three
test structures in this group: a single finger device (0.54 gm per finger), a two fingered
device (0.27 gm per finger), and a three fingered device (0.18 ptm per finger). The second
54
group has the same dimensions as the first group but with PMOS transistors. These two
groups are illustrated in the left of Figure 3-4.
The third group consists of NMOS transistors with gate widths of 0.50 tm and total
gate length of 0.72 gim. There are three test structures in this group: a single finger device
(0.72
gim
per finger), a two fingered device (0.36 gm per finger), and a four fingered
device (0.18 Rm per finger). The fourth group has the same dimensions as the third
group, but with PMOS transistors. Both of these groups are illustrated in the left of
Figure 3-4.
3.2
Back End of Line Structures
Back end of line (BEOL) variation can also be studied with the analog multiplexed
characteristics test chip. The BEOL analysis of this thesis focuses on capacitance
extraction and variation measurements.
Interconnect capacitance is mostly composed of three different capacitances: planar,
fringing, and coupling capacitances, as illustrated in Figure 3-5. This thesis focuses on
the extraction and analysis of the planar and coupling capacitances, and also the
crossover capacitance which is a combination of the fringing and plane to plane
capacitance.
2
T
1
2
T3
13
Figure 3-5: Interconnect capacitances - 1. Fringing, 2. Coupling, 3. Plane.
3.2.1 Charge Based Capacitive Measurement Methodology and Implementation
Previous work [1] noted that measurements of variation in interconnects require
55
-----------------
accurate procedures, as these are harder to detect than device variation. This thesis uses a
differential charge based capacitive measurement (CBCM) method [22], [23], [24], [25],
[28] to detect these variations. The CBCM test structure is illustrated in Figure 3-6. It is
integrated with switches so it can also be used with the scan chain approach. The back
end of line (BEOL) tiles are then connected in a "row" sub-block, like the FEOL tiles are,
except that these have a larger number of input signals, and therefore pads, to control
them because of the additional required gate voltages (four different gate voltages, as
opposed to one in the FEOL). The layout of this tile is shown in Figure 2-4 in Chapter 2.
Vii- Switchli
neti
Switchj- Vlj
V2i- Switch2i
A
Switch2j V2j
Source
Switch
Vii -
K-
V2i
___L.VL
Vlj
-JhK-h -
V2j
.JhJh
Step1
Step2
L--L
hV
Step3
Figure 3-6: CBCM structure with switches.
With the CBCM method, the capacitance between nodes i and
j
is charged and
discharged through the pseudo-inverters connected to the gate input signals during "Step
1" and "Step 2," as shown in Figure 3-6. In "Step 3," nodes i and
j
are at the same
potential, and one can measure the current and calculate the capacitance due to the
CBCM structure alone (without the interconnect load capacitance). The measurements of
step three can then be subtracted from the measurements of steps 1 and 2. The average
56
source currents in these steps provide information to calculate C1, as described in [23]
and [24], and as shown in (3.1):
C= IstepI + Istep2 - Istep3
2Frequency
VDD
(3.1)
Simulation of the CBCM structure gives measurements of sub-fF precision for test
capacitors (ideal capacitors connected to their terminals) of 10 to 100 fF, for frequencies
of 500 KHz. This data is shown in Table 3-2. Accuracy increases with increased speed,
but we limit our measurements to 500 KHz for ease of measurement equipment selection.
Test Cap
CBCM Measured
Capacitance (fW)
0
10
20
30
40
50
60
70
80
90
100
0.30
10.50
20.96
30.82
40.63
49.73
60.41
70.27
80.80
90.53
100.98
difference
(fF)
0.30
0.50
0.96
0.82
0.63
-0.27
0.41
0.27
0.80
0.53
0.98
Table 3-2: CBCM measurements capabilities.
The switches are the same as described in Section 2.6, except that here we need more
per test structure (five switches instead of the two needed for FEOL test structures).
Additionally, the RON in the source path because of the switch is not a problem, because
what is taken into consideration is the difference between the currents; therefore a switch
with a small RON connecting to ground is not needed here, allowing smaller switch
transistors to be used. BEOL rows must be separate from FEOL rows, as they require a
different setup of switches and of input pads. All of the switches in the BEOL tiles are the
same size, and its schematic and dimensions are shown in Figure 3-7 and Table 3-3,
57
respectively.
V1 i
Switch
)0.neti
V2i
Switch
netj
Switch IVij
Switch
V2j
Q2 Q3
Q1
en /en
en /en
Output/Ground
Switch
BEOL switch
en /en
BEOL tile with switches
Figure 3-7: BEOL switch schematic.
Transistor
Transistr
Q1
Q2
Q3
Size
Gate Length [pm]
Gate Width [Wm]
0.35
2
0.30
2
0.35
2
Table 3-3: BEOL switch transistors sizing.
The dimensions of the metal capacitances attached to the CBCM structure are chosen
so they are as large as possible but that could fit in the area of a tile, as illustrated in
Figure 3-8.
PkanP Tilk
Comb Tile
Grid Tile
Figure 3-8: Layouts of BEOL tiles.
58
3.2.2 Plane Structures
The plane test structures measure the capacitance between two metal planes, enabling
one to extract interlayer dielectric (ILD) thickness variation. The test structure consists of
two large metal plates, one on top of the other, as seen on Figure 3-9. A large plate of
metal-x is placed over another one of metal x-1; the x-l plate is made slightly larger in
case they misalign during the mask process. The test chip includes four of these
structures, with these combinations of metals: M1/M2, M2/M3, M3/M4, and M4/M5. All
of the top planes have dimensions of 14.62 gm (wide) by 35 gm (tall). All of the bottom
plates have dimensions of 16.62 jim (wide) by 37 gm (tall).
CBCM
Structure
Figure 3-9: BEOL plane structure.
3.2.3 Comb Structures
Comb structures enable one to detect variation in the spacing between the wires,
using a finger-like structure, as seen in Figure 3-10. The difference between capacitances
in different metal layers provides insight into the impact of variation in each metal layer.
To determine if the variation is more heavily due to the variation in the lateral spacing or
due to variation in the thickness of the wire, the structures are built with minimum width
and minimum space, 1.2x minimum width and minimum space, and minimum width and
1.2x minimum space. Each of these comb structures are laid out in Ml, M2, M3, M4, and
M5, for a total of 12 test structures. There are 28 fingers per structure, 14 attached to the
node i and the other 14 to the node j of the CBCM structure. Each finger is 35.5 jim long,
59
and it is exposed to the next finger for 34.5 gm, as illustrated in Figure 3-10.
Figure 3-10: BEOL comb structures.
3.2.4 Grid Structures
The grid test structures focus on crossover capacitances, or the capacitance between a
wire of one metal level over a wire of another metal level. The difference compared to
the plane test structures is that the metals here are fingers of minimum size and at
minimum distance, as shown in Figure 3-11, making the fringing capacitance from layer
to layer a bigger factor than in the plane to plane case. The capacitive loads are built as a
horizontally fingered metal layer under a vertical metal layer of higher level, all at
minimum width and spacing. Coupling capacitance within the layer is not an issue,
because the adjacent fingers of the same metal layer are at the same potential. The fingers
have the same dimensions as those in the comb test structures, described in Section 3.2.3.
There are four of these grid test structures: M1I/M2, M2/M3, M3/M4, and M4/M5.
Figure 3-11: Grid test structures.
3.3
Summary
This chapter has described the devices under test (DUTs) implemented in the test chip
for characterization and investigation of process induced variation. By making each
60
structure, or each family of structures, primarily sensitive to a particular variation source,
the pattern induced impact of these variations can be studied. Both front-end-of-line
(FEOL) and back-end-of-line (BEOL) structures have been described. Chapter 4 will
describe the measurement results of these test structures in fabricated chips.
61
62
Chapter 4
Results and Analysis for Layout-Dependent Test Structures
This chapter analyzes the front end of line (FEOL) test structures based on electrical
test data, focusing on structure functionality and variation due to layout practices.
Section 4.1 first discusses the functionality of all the test structures in the test chip to
determine which work as expected when tested. The statistical methodology used to
identify
chip-to-chip,
within-chip,
and structure-to-structure
frequency variation
components is presented in Section 4.2.
In Section 4.3 we then examine the resulting measurements for various sets or
families of structures in order to understand how structures within that family differ due
to designed layout practices. First, the orientation test structures analysis studies the
effect of layout orientation in the behavior of devices. The polysilicon spacing structures
analysis focuses on the impact on channel length due to the local effect of polysilicon
proximity (due to interaction between the different fingers of polysilicon in a device).
The number of polysilicon fingers test structures analysis investigates how the channel
length variation changes when different structures have the same total gate length but
using a different number of fingers. Finally, the chapter is summarized in Section 4.4.
4.1
Functionality
All FEOL and BEOL test structure designs have been tested successfully, as shown in
Figure 4-1. Testing was performed using the 35 packaged chips with signals controlled
through Labview and an NI PCI-6259 data acquisition card, and current measurements
using a Keithley 2400 SourceMeter, also connected through GPIB to Labview. The 2400
ammeter can measure currents from 10 pA to 1.055 A.
63
Gate Voltage Sweep for All FEOL DUTs
X 10.
1.6
1.4-
N=8-
/
1.2-
0.802
0
0
0.5
1
Gate Voltage [V]
1.5
2
Figure 4-1: Gate voltage sweeps at 1.8V VDS for all FEOL test structures, NMOS and PMOS, for
one row of a single test chip (728 structures total).
Each FEOL test row (720 tiles) takes approximately 30 minutes to measure for a
single bias point, mainly due to measurement hardware and software setup/measuring
times. Each tile only needs to be on for -50 milliseconds to gather a DC measurement;
however, we leave the tile on for 100 ms, being cautious to make sure that all voltages
and currents are settled in the feedback network. BEOL testing takes longer because the
CBCM current must be averaged through extended periods of time for accuracy. With
our setup each BEOL row (336 tiles) takes approximately 1.5 hours to measure.
4.1.1 ElectricalRepeatability
It is important to have only minimal error in the electrical repeatability, so that we can
trust that the source of variation seen is not due to measurement noise. FEOL test
structures were all tested in DC, with time constants for the feedback network much
64
larger than what simulation calculations indicated were needed. This helped ensure a
small measurement error, only 0.04% reproducibility and 0.02% repeatability errors for a
single test chip tested multiple times, and gives confidence that most of the data
measured is minimally affected by the measurement itself.
4.1.2 Leakage Currents
When measuring a specific FEOL DUT in a test row, there are other 719 "off' tiles in
the row that share the same output/ground line. The leakage current is measured by
gathering the current in the share ground line after the scan chain has gone through all the
test structures (after each DUT has been "on" once). The mean of the measured leakage
current is 2.1 nA, which matches the simulated results and should not affect the saturation
measurements. Sub-threshold measurements at very low voltages of currents near or
below 2 nA will be affected by this current, and are therefore not used in our analysis.
4.2
Variation Analysis
In this chapter, we focus on two key questions related to the observed variation in our
test structures. The first goal is to consider the observed total variation in each type of test
structure, and to decompose that variation into two components: "chip-to-chip" variation
giving an indication of across wafer effects, and "within-chip" variation due to the effect
of local or global layout environment on the test structure. We will see that some test
structures are more prone to vary across the wafer than others. Similarly, we will also see
that some test structures appear to be more sensitive to within-chip layout factors.
The second goal of the statistical analysis in this chapter is to consider particular
layout practices in more detail and identify their likely impact in the measured current.
To accomplish this, sets of structures designed to investigate each layout effect are
65
considered. In general, we will be interested in two characteristics of the resulting DUT
measurements: to what extent the mean of the transistor current has been affected, and to
what extent the variance of the transistor current has been impacted, as performed in
previous work [1].
4.2.1 Within Chip and Chip to Chip Components
As illustrated in Figure 4-2, there are two components of variation we would like to
understand and separate based on measurements of currents across multiple replicates
and multiple chips of a particular DUT. There is some spread in measured currents within
each chip for a particular test structure type - the within-chip variance (across the
replicates of that test structure within each chip, shown as a vertical set of points in the
figure). Second, there may also be variation or differences between the mean currents
(the line drawn within each chip group in the figures) from one chip to the next. We
summarize these components of variation and their computation below using the nested
variance components analysis method [29].
Chip 1 Chip 2
Figure 4-2: Representation
Chip 3
..
"
Chip N
of chip-to-chip versus within-chip variation.
66
4.2.1.1
Within Chip Variance
The within chip variance, Uac, refers to the variation of a specific test structure
within a chip, and can be determined by:
I
17C
r1
('i
1
2
)2
(4.1)
In equation (4.1), r stands for the number of replicates of a specific DUT design in a
chip, and I for the current measured in the device for a given bias condition. The
subscript x indicates the chip number, and Ix is the average of the r replicate DUT
currents within that test chip.
After calculating all the variances within each chip, and because all c chips have the
same number of replicates in them, the overall within chip variance can be calculated as
the average of the variances in each chip, as shown in equation (4.2).
2X
2
4.2.1.2
(4.2)
C IaWC
1
Chip to Chip Variance
The chip to chip variance must be calculated carefully so that our calculation is not
inflated by the within chip variance already calculated. The nested variance method
compensates for exactly this. The observed chip to chip variance qocc is calculated as
the variance across all chips of the mean current of a DUT in each chip, as shown in
equation (4.3), where
IAC
is the average of Ix across all c chips.
2
JOcc
=
1
(IL
C - Ii=1
-1
)2
- IAC
(4.3)
To estimate the actual chip to chip variance (acc ) we subtract the within chip
variance divided by the number of replicates to the observed chip to chip variance, as
67
shown in equation (4.4).
(ECC
4.2.1.3
2_
~
(4.4)
c
C
CC
Total Variance
will then include both the chip-to-chip and within-chip
The total variance a
variance components, resulting in equation (4.5). This is under the assumption that the
chip to chip and within chip variance sources are independent, e.g., due to across-wafer
equipment non-uniformity vs. within chip layout dependencies, respectively.
O72
2C
_02
(4.5)
T = JEcc - aWC
Finally, we note that the within-chip variation may be greater than or less than the
chip-to-chip variation - the sources of variation would physically be different and one or
the other could well be larger.
4.2.1.4 Aggregated Variance
We choose to distinguish between our estimated total variance (UT), and the
observed variance of all measurements of a particular test structure type across all chips.
We define the aggregated variance (oA ) as in (4.6).
2
UA
=
C1
(Ix
I
cr - 1 X=1 i=1
2
- Ic A
(4.6)
This is simply the measured variance across all replicates of a given DUT type, across
all chips, without the detailed decomposition into separate chip-to-chip and within chip
variance components. This aggregate variance is the simplest variation indicator based
directly on the data without variation structure assumptions.
4.2.2 Normalized Variation
To get a better qualitative feel for the observed variations between different test
68
structure types, we present a percent aggregate variation, V%, as a scaled ratio of the
aggregate standard deviation
UA
to the mean, IAC. The variations presented in this and
subsequent chapters are the standard deviation of each test structure type divided by the
overall current mean IAC for that test structure type, as shown in equation (4.7).
A
V%=
100%
(4.7)
I AC
4.2.3 Evaluation of Mean Differences
In many cases, we will be interested in determining how significant an observed mean
difference is between two or more samples. For the example shown earlier in Figure 4-2,
we might ask whether the mean difference is "real" - that is, how unlikely is it that we
would observe the indicated mean difference given the spread within each set of
measurements. We will use the analysis of variance, or ANOVA, formulation in the work
below [30], [31].
A two-way ANOVA analysis accounts for the difference in mean, per DUT type and
per chip. A two-way ANOVA implies that there are two factors at work; in our case they
are the DUT design type and chip number. The implicit model for the two-way ANOVA
is shown in (4.8).
y = YO + yf + yc + N(O,u 2 )
(4.8)
In equation (4.8) yo represents the overall mean of the current of a test structure type,
yj represents the deviations of each test structure type's current (from the mean current)
that are attributable to a specific design practice, y, represents the deviations of each test
structure type 's current (from the mean current) that are attributable to the specific chip
69
number, and N(O, a') accounts for random disturbances.
The two-way ANOVA analysis has the advantage of separating out an additive mean
shift due to the chip number from a mean shift due to layout factor of interest (e.g.
spacing between polysilicon fingers).
4.2.4 Evaluation of VarianceRatios
It is also important to understand if the spread or variance observed in two
populations are "the same" or significantly different. For example, we might want to
understand if the variance in chip 1 is different than in chip 2, or if the observed ratio of
variances is instead likely to occur simply by chance given the spread and number of
measurements taken within each chip. For this we compare the ratio of variances to an
inverse of the F cumulative distribution function for a given probability and degrees of
freedom.
4.3
Layout Dependent Variation Analysis
Some dependencies studied in [1] were again studied here to examine layout variation
effects at the transistor level. All results shown in this section are for saturation bias
conditions, as shown in Table 4-1.
VREF
NMOS
PMOS
(VDS equivalent) [VI
1.8
1.8
VGATE [
I
1.8
0
Table 4-1: Bias conditions for layout dependent variation analysis.
4.3.1 Orientation
Test structures with different orientation (vertical vs. horizontal) show a small but
consistent offset due to orientation, as seen in Figure 4-3. In these plots, the mean across
all 16 replicates of the W/L = 1/0.18 pm device, and across all chips (35 chips for the
NMOS and 31 chips for the PMOS) is shown; the error bar is the one standard deviation
70
across all devices (560 for NMOS and 496 for PMOS) of this size around that grand
mean. The results are tabulated in Table 4-2.
5.95
X10
Overall Orientation
NMOS
-4
N=560
5.9
2.45
W/L=1/0.18 um
5.85
a)
N=496
W/L=1/ 0.18um
2.4 -,_2.35
2
5.8
----- - --- - - - -- -
a)
PMOS
X 10-4
2.5 --
2.3 ---
) 2.25 -----
- - --- - - - - - -
0
5.75
0
U0
5.7 -- ----
--
- ---- - -- - - -
2.1
-- - - -- - - - -
5.65 --- -- -- -
5.6
V
2.05----2-
H
V
H
Figure 4-3: Orientation effect for NMOS and PMOS transistors.
Test Structure
Type
Average Current
Among Al Replicates
and Chips
IAC [mAI
NMOS Vertical
NMOS Horizontal
PMOS Vertical
PMOS Horizontal
0.575
0.584
0.228
0.219
Standard Deviation
Among All Replicates
and Chips
(A
[LAI
12.3
11.1
16.3
15.7
Table 4-2: Tabulated orientation effect for NMOS and PMOS transistors.
Interestingly, NMOS and PMOS transistors have the opposite dependency: NMOS
have higher currents when laid out horizontally in this particular test chip, and PMOS are
higher when laid out vertically, as seen in Figure 4-3.
The difference in means between the test structures are proven statistically significant
with the two-way ANOVA tests shown in Table 4-3 and Table 4-4. These tables refer to
the data plotted in Figure 4-3. In this case, and referring to the implicit model for the two71
way ANOVA shown in (4.10), y, represents the overall mean of the current of a test
structure type (NMOS,
PMOS, vertical or horizontal),
y, represents the current
deviations given the designed orientation (vertical or horizontal), and yc represents the
current deviations per chip. N(0, a 2 ) accounts for random disturbances.
(4.9)
y = YO + y, + yc + N(0,u 2 )
NMOS Vertical
Source
Orientation
Chips
Error
Total
And Horizontal
Prob>F
Mean Sq. F
d.f.
Sum Sq.
0
1 2.10E-08 332.6998
2.1OE-08
0
39.8306
34 2.52E-09
8.56E-08
6.85E-08 1084 6.32E-11
1.75E-07 1119
Table 4-3: Two-way ANOVA for NMOS with different orientation.
PMOS Vertical And Horizontal
Mean Sq.
d.f.
Sum Sq.
Source
1 2.15E-08
2.15E-08
Orientation
30 4.66E-09
1.40E-07
Chips
960 1.20E-10
1.15E-07
Error
991
2.76E-07
Total
F
179.9218
39.0038
Prob>F
0
0
Table 4-4: Two-way ANOVA for PMOS with different orientation
Another method to corroborate that the observed means are statistically different is
with Student's t-distribution a t-test. Equation (4.10) describes the estimation of a
confidence interval for the mean, where IAC is the calculated overall current mean per
type of test structure (for all chips and replicates), s is the pooled sample standard
deviation and n is the number of replicates (in our case, 560 for the NMOS and 496 for
the PMOS). We use a=0.05 for a 95% confidence interval.
S
S
S
'AC
- ta/~
'
/1
' AC
+ a2nI-T
(4.10)
The results of these confidence interval estimates are plotted in Figure 4-4, which
72
provides a graphical way to verify that the sampled means are different. The thicker,
smaller error-bars on top of the one standard deviation error-bars that were already
presented in Figure 4-3 represent the confidence interval of the mean, to 95% confidence,
given our sample size (560 for NMOS and 496 for PMOS). We will continue in the rest
of this chapter to highlight mean differences between test structures with different
layouts, using plots of both the sample standard deviation, and of the confidence interval
of the mean as a simple graphical test or indication of significance to complete ANOVA
calculations.
Overall Orientation
5.95
x10
4
x10 4
NMOS
2.5
2.45
N=560
5.9 -----------------------------2.4
W/L=1/0.18 um
2.35
5.85 ------- t -------------a,
2.3
N=496
W/L=1/0.18 um
-----------------
2.2 --
--------
--
---
2.25 -------
5.75 ------
--- -- --
---------
23 - - - - - - - - - - -
C~~~~~~~
-------------5.8---
0
0
PMOS
--
-----
0
5.7 -------- ----------- -- u 2.15
2.1
-----------
5.65 -----5.6
V
H
-
----
-----
2.05 2
- -- - ----
-----
- ---
V
H
Figure 4-4: Orientation effect for NMOS and PMOS transistors
with confidence intervals for the mean.
The offset in currents between the vertical and horizontal structures is seen both in the
averages across all chips and for each individual test chip. Figure 4-5 and Figure 4-6 plot
the average current per chip for the orientation test structures, and show an offset
between the vertical and horizontal test structure types for both the NMOS and PMOS
cases. The sampled data includes all replicates per FEOL row, with a sample size of eight
73
per data point plotted
6
C:
Orientation per Chip: NMOS Row 1
x10 -4
5.8
0 5.6L
U)
--
*---
-,A
-
Vertical
Horizontal
N=8
5.4
Chips
6
X1O
-4
Orientation per Chip: NMOS Row 3
5.8
-
0 5.6
0
-- - Vertical
-A
- Horizontal
U)
N=8
5.4
Chips
Figure 4-5: NMOS orientation effect on a chip by chip basis..
2.4
X10-4
Orientation per Chip: PMOS Row 1
N=8 -
2.3
2
0
U)
2.2
2.1
- - - Vertical
--A - Horizontal
2
Chips
2
3
x10
Orientation per Chip: PMOS Row 3
I
I
FwI-I-I
-- A
2.5 F
-
Id
I
ver tica
Hor izontal
N=8
0
!LA
U)
A
2
Chips
Figure 4-6: PMOS orientation effect on a chip by chip basis.
74
The consistency prompts us to look at each device and explore its behavior. In the
FEOL test rows, all vertical structures are placed right next to a horizontal structure (see
Appendix I for location information within row). We subtract the current mean of each
vertical structure to its neighbor horizontal structure, calling this our orientation delta.
There are 16 orientation deltas per chip, as there are 16 vertical and 16 horizontal test
structures per chip. The 16 orientation deltas per chip (eight deltas per FEOL row) are
averaged out and plotted in Figure 4-7 for the NMOS and Figure 4-8 for the PMOS. The
delta of the current between the horizontal and vertical test structures is relatively
consistent for all chips and for both NMOS and PMOS, as shown in Figure 4-7 and
Figure 4-8.
The consistent offset is seen in most structures placed right next to each other, and it
hints at a systematic variation during the fabrication process. Furthermore, the fact that
the offset is consistent but in opposite directions with NMOS and PMOS suggests that the
variation may be related to the stress in the substrate. It has been reported [32], [33] that
the electron and hole mobilities depend on the current flow direction relative to crystal
orientation because of an anisotropic property of the effective carrier mass with strain.
PMOS and NMOS transistors are affected in opposite ways by strain, as NMOS mobility
increases with biaxial tensile strain and PMOS mobility increases with uniaxial
compressive strain. The process we used is not purposely strained, but there may be some
residual strain from the making of the devices, from processes such as shallow trench
isolation (STI). Other possible sources of variation that may also affect the transistor's
behavior due to orientation are mask bias and ion implantation directionality.
75
NMOS Orientation Deltas for Both Rows
x10 5
=3 0
N=16
Chips
Row 1
X 10-5
2_
2
X10
-5
Row 2
1
C
C
C
0
U)
0
a)
N=8
-1
N=8
0
-1
Chips
Chips
Figure 4-7: Current difference between adjacent NMOS vertical-horizontal test structures.
0
U)
x 10-5
PMOS Orientation Deltas for Both Rows
-0.5
C
C
-1
U)
N= 16
0
-1.5
Chips
5
0
x 10-
Row 1
Row 2
-11pu'
I
-0.5
-0.5
(D
-1
x10 5
0
PFri'
I'll1
-1.5
Chips
C:
N=8
N=8
0
-1.5
Chips
Figure 4-8: Current difference between adjacent PMOS vertical-horizontal test structures.
76
.
..........
------------
4.3.1.1
Variance Components and Variation
Table 4-5 breaks down the sources of variation for the orientation test structures. The
aggregate variation in these structures is approximately 2% for the NMOS and 7% for the
PMOS, as shown in the last column of the table. The variation for all the structures was
split almost evenly between within chip and chip to chip, with both vertical structures
having a slightly larger chip to chip component.
Within
Chip
a*
V
Varation
-100%
[(IiA)2}
[(PA)2]
57.9
97.1
155
37.4%
62.6%
2.15%
62.6
62.4
125
50.1%
49.9%
1.90%
122
150
272
44.9%
55.1%
7.16%
122
129
251
48.6%
51.4%
7.18%
T
Vertical
PMOS
Horizontal
Chip to
Chip %
[(MA)2]
ECC
Vertical
NMOS
Horizontal
PMOS
Within
Chip %
W"r
.100%
OT
WC
NMOS
Estimated Estimated
Total
Chip-Chip
- 1 00%
IAC
T
Table 4-5: Variances and variation for orientation test structures.
4.3.2 Polysilicon Spacing
Structures with the same number of polysilicon fingers but with different spacing
between the fingers show a mean shift, but do not show much change in variation for
either NMOS and PMOS devices, as seen in Figure 4-9. In these plots, the mean across
all 16 replicates of the W/L =0.5/0.54 gm devices, and across all chips (35 chips for the
NMOS and 31 chips for the PMOS) is shown; the error bar is the one standard deviation
across all devices (560 for NMOS and 496 for PMOS) of this size around that grand
mean. These results are tabulated in Table 4-6.
The thicker, smaller error-bars on top of the one standard deviation error-bars
represent the confidence interval for the mean, at 95% confidence, given our sample size
77
(560 for NMOS and 496 for PMOS).
1.66-
X10
-4
Polysilicon Finger Spacing
PMOS
NMOS
1f 5
4.5
N=560
W/L=0.5/0.54
______ ___
1.62 --------------
0
CO)
4.2
4.1
-------------------
1.58
a)
4.3 --- - ------
----------------------
.0
0)
=3
0
-----------
1.56
N=496
W/L=0.5/0.54
-- -- - - - - -
4.4
1.64
1.6
x
--------- - -
-- - -
- --
- -----
-------- -
4
3.9
1.54
CO)
1.52 -------------- -
----
--~---
1.5 F----
--------
------------
3.7
3.6
1.48
1x
3.5
1.2x1.5x 3x
1x
1.2x1.5x 3x
Spacing
Spacing
Figure 4-9: Poly finger spacing effect for NMOS (left) and PMOS (right).
Test Structure Type
Average Current
Among all Replicates
d CChips
[mAj
0.159
0.156
0.155
0.153
0.0402
0.0392
0.0388
0.0384
IAC
NMOS
NMOS
NMOS
NMOS
PMOS
PMOS
PMOS
PMOS
Ix Spacing
1.2x Spacing
1.5x Spacing
3x Spacing
Ix Spacing
1.2x Spacing
1.5x Spacing
3x Spacing
Standard Deviation
Among al Replicates
CA
[pA_
3.60
3.56
3.51
3.49
3.22
3.10
3.09
3.13
Table 4-6: Tabulated poly spacing effect for NMOS and PMOS transistors.
78
A strong trend is observed in Figure 4-9: larger spacing or separation between poly
fingers leads to lower currents, at both NMOS and PMOS test structures. Table 4-7 and
Table 4-8 demonstrate by two-way ANOVA that the mean differences between the
different polysilicon finger spacing is statistically significant, for both NMOS and PMOS
transistors. These tables refer to the data plotted in Figure 4-9. In this case, and referring
to the implicit model for the two-way ANOVA shown in (4.12), y, represents the overall
mean of the current of a test structure type (NMOS or PMOS with spacing of minimum
size, 1.2x minimum size, etc.), y, represents the current deviations given separate spacing
between the fingers due to design practice, and y, represents the current deviations per
chip. N(0, U 2 ) accounts for random disturbances.
y
=
yO + ys + yc + N(0,.
NMOS Poly Spacing
Sum Sq.
Source
1.18E-08
Spacing
1.60E-08
Chips
1.20E-08
Error
3.98E-08
Total
2
(4.11)
)
Prob>F
Mean Sq. F
0
3 3.92E-09 717.3836
0
85.9738
34 4.70E-10
2202 5.47E-12
2239
d.f.
Table 4-7: Two-way ANOVA for NMOS with different finger spacing.
PMOS Poly Spacing
Mean Sq. F
d.f.
Sum Sq.
Source
3 2.77E-10 57.8831
8.31E-10
Spacing
70.625
30 3.38E-10
1.01E-08
Chips
9.33E-09 1950 4.79E-12
Error
2.03E-08 1983
Total
Prob>F
0
0
Table 4-8: Two-way ANOVA for PMOS with different finger spacing.
The trend suggests that the channel length is somewhat reduced (leading to increased
saturation currents) as we pack the transistor fingers more closely together, consistent
with a lithographic or etch proximity effect that shortens or narrows these features as they
79
7:7 %
approach each other.
An additional theory is that the "stack effect" may be at work, in which voltage drop
due to the diffusion layer resistance between the fingers has an adverse effect on the
transistor behavior. What this means is that the resistance between the fingers will change
the source voltage of the inner nodes, and this will change the VBS voltage of each
transistor, which can lower the current for both NMOS and PMOS. However, for a
diffusion layer sheet resistance of 5 Q/square, the largest resistance between nodes for the
3x minimum spacing structure would be under 20 Q, and simulation results show that
with such a resistance one would not see a change larger than 0.5% between the output
currents. In Figure 4-9 we see a change of 1.6%-2.5% in the measured data, which is
larger than we expect to see with the stack effect only.
4.3.2.1
Variance Components and Variation
Within Estimated Estimated
Total
Chip-Chip
Chip
Within
Chip %
(T~clic--100%
[(pA)2]
NMOS .
I x Spacing
NMOS
1.2x Spacing
NMOS .
1.5x Spacing
NMOS .
3x Spacing
PMOS .
Ix Spacing
PMOS .
1.2x Spacing
PMOS .
1.5x Spacing
PMOS .
Chip to
Chip %
--
-100%
Varation
ILC
[(pA)2]
6.11
[(A)2]
7.04
13.15
45.1%
54.9%
2.26%
5.21
7.67
12.88
39.5%
60.6%
2.28%
5.1
7.41
12.51
39.7%
60.3%
2.26%
5.22
7.16
12.38
41.1%
58.9%
2.28%
5.22
5.33
10.55
48.0%
52.0%
8.02%
4.96
4.81
9.77
49.2%
50.8%
7.91%
4.72
4.98
9.7
47.2%
52.8%
7.96%
5.07
4.86
9.93
49.5%
50.5%
8.14%
Q2
SpacVrg Tb3x
Table 4-9: Variances and variation for polysilicon spacing test structures.
80
Table 4-9 breaks down the sources of variation for the polysilicon spacing test
structures. The variation in these structures is approximately 2.3% for the NMOS and 8%
for the PMOS, as shown in the last column of the table. The variation for all the
structures is slightly more heavily due to chip to chip variation. The fact that the split is
close to even suggests that both level process variation, perhaps due to film thickness or
related variation, and die-level effects due to lithographic or etch proximity effect, are
important.
4.3.3 Number of Polysilicon Fingers
NMOS structures with same drawn gate length but with the gate split among a
different number of polysilicon fingers show a strong dependency on variation due to the
number of fingers, as seen in Figure 4-10. The top plots in Figure 4-10 show the analysis
for NMOS structures with equivalent gate length of 0.54 gim. These gate lengths are
divided into one-0.54 gim finger, two-0.27
gim
fingers and three-0.18 gm fingers. The
bottom plots show the variation for a structure with equivalent gate length of 0.72 im.
These gate lengths are divided into one-0.72 gm finger, two-0.36 pim fingers and four0.18 gim fingers, as explained in more detail in Section 3.1.4.
On the left hand side of Figure 4-10 we plot the current means of the NMOS test
structures with different number of fingers but equivalent gate length (1, 2 and 3 fingers
for the top plot, with W/Lequivaient=0.5/0.54gim, and 1, 2 and 4 fingers for the bottom plot,
with W/Lequivalent=0.5/0. 7 2 gim). The current means are calculated across all 16 replicates
of each test structure type and across all 35 chips, for a total of 560 samples. The error
bar is the one standard deviation around that grand mean.
On the right hand side of Figure 4-10 we plot the variation of each test structure type.
81
The variation is calculated by dividing the aggregated standard deviation of all 560
devices (with a specific number of fingers and equivalent gate length) by their overall
mean, or
-IAC
100%. The error-bars on top of the variation bar plots represent the
normalized confidence variance interval. The interval formula for the estimate of
variance is shown in (4.12), where n is the number of replicates (560 in this case) and s2
is the pooled sample variance. We use a=0.05 for 95% confidence interval in the Chisquare distribution.
(n- 1)s
2
2
-
%a/2,n-1
-
2(n
2
A
(
)s2
2
(4.12)
X-a/2,n-1
The bar plots show how variation increases steadily as the numbers of fingers
increase. Figure 4-11 shows the same analysis for the PMOS transistors, with analysis of
all 16 replicates of each test structure type and across 31 chips, for a total of 496 samples.
However, even though variation is larger for the PMOS transistors, their variation deltas
are much smaller. The overall means and standard deviations for the NMOS and PMOS
transistors of different number of fingers are tabulated in Table 4-10.
Test Structure Type
Type
Leq ivaint # of Fingers
1
NMOS 0.54 gm
2
3
1
NMOS
0.72 gm
2
4
1
PMOS
0.54 gm
2
3
1
PMOS
0.72 gm
2
4
Average Current
IAC [mA]
0.143
0.148
0.159
0.115
0.114
0.127
0.0360
0.0371
0.0400
0.0276
0.0269
0.0302
Standard Deviation
'TA
[pA
2.13
2.57
3.47
1.69
1.78
2.74
2.68
2.76
3.14
2.06
2.03
2.44
Table 4-10: Tabulated poly spacing effect for NMOS and PMOS transistors.
82
-777-77=---
N=560
W L=_Th
1.6
0
1.4
1
1.3
_4_.___
_ _
0.01 F--
0
3
2
1
2
3
Number of Fingers
-4
0.03
2.16%
C
0.02
1.2
1.47%1.56%
1
0.01
0 1.15
C/)
-
1.74% 0.02 F 1.49%+
-AA
N=560
W/L=-0.5/0.72
1.25
-
2.18%
Number of Fingers
Xl1O
-
0.03
EU
Cl)
--
C
CO
1.5
W
-
NMOS of Different Number of Fingers
-4
x1O
1.7
;;;-,
- -- - ---
1.1
0
2
4
1
Number of Fingers
1
2
4
Number of Fingers
Figure 4-10: Mean(left) and normalized variation (right) in saturation current for NMOS transistors
with different number of polysilicon fingers. Statistics for N=560 DUTs consisting of 16 replicates per
chip, for 35 chips.
4.5
xl1O
PMOS of Different Number of Fingers
-5
S4
0
C
CO
--
7.%744-%7.85%
0.05
I
-
3.5
E
0)
3
65)
0.1
N=496
-W/L--0.5/0.54
----
0
2
3
1
Number of Fingers
3.5
x10
C
3
1
2
3
Number of Fingers
-5
-
N=496
W/L=0.5/0.72
-
0.1
+
(U
cc;
---
2.5 - -
7.46%7.52%8.08%
C
0.05
E
M)
0
W/
2--
4
1
2
Number of Fingers
0
4
2
1
Number of Fingers
Figure 4-11: Mean(left) and normalized variation (right) in saturation current for for PMOS
transistors with different number of polysilicon fingers. Statistics for N=496 DUTs consisting of 16
replicates per chip, for 31 chips.
83
-.-
. -
-QM
If we consider the ratio of the overall variance of the NMOS three-fingered, minimum
length structure to the variance of the single finger, 3x minimum length structure, we get
r = (4.75e-12/1.26e-1 1)
2
= 7.01. The inverse of the cumulative distribution function (cdf)
for F gives a critical ratio corresponding to the largest ratio of variances one would
expect to observe with a given probability, and for specific degrees of freedom in the
numerator and denominator variances. In this case we choose a 95% probability, and the
nominator and denominator degrees of freedom are the number of the specific type of test
structure (for all chips) minus one. If we compare the ratio 7.01 to FO. 9 5, 559,
559=
1.15 (in
this case, we have 16 of these structures in each chip, times 35 chips), we see that the
observed expansion in variance is indeed significant at the 95% confidence level. We
perform similar tests for the other types of structures, NMOS and PMOS, and tabulate the
results in Table 4-11 and Table 4-12.
NMOS
NMOS
0.54 jim drawn
gate length
Number
Fingersof
1
2
rr
Estimated
Total (Y '95s9,s
4.75E-12
6.91E-12 7.01
structure
3
1.26E- 11
0.72 jim drawn
gate length
1
2
2.97E-12
3.32E-12
structure
4
7.82E-12
1.15
1.15
6.94
Table 4-11:Variance ratios of NMOS multiple fingers structures.
Number of
Fingers
Estimated
Total c2
0.54 jm drawn
gate length
1
2
1.09E-1 1
1.01E-11
structure
3
9.99E-12
0.72 jm drawn
gate length
1
2
4.44E-12
4.31E-12
structure
4
6.23E-12
PMOS
Table 4-12: Variance ratios of PMOS multiple
r
F_
1.89
1.16
1.97
1.16
fingers structures.
84
Referring to Table 4-11 and Table 4-12, NMOS test structures with equivalent gate
lengths of 0.54 jim and 0.72 jim show strongly that there is a significant change in
variance between the different numbers of fingers. PMOS test structures also show that
their variances are different to 95% confidence, but the ratio is not as large as the NMOS.
A possible explanation for why the transistors show larger variation given a larger
number of fingers is that the effective gate length can change with variation, as ALeff can
be three times larger in a three finger device than in a single finger device, as partially
illustrated in the simplified MOSFET cross section [34] shown in Figure 4-12. This three
fold increase in opportunity for variation suggests that variance may be proportional to
number of fingers.
Potential AL
D
Z
GS
Eff ective
Gate Length
P
Figure 4-12: MOSFET cross section.
However, the factor that seems to dominate the variation in our test structures with
different number of fingers is the size of the poly fingers. The normalized variation of the
NMOS test structures with the smallest sized fingers (0.18 jim long) show almost
identical variation for the three-finger (2.18%) and four-finger (2.16%) structures, as
shown in Figure 4-10. This means that even though the four-finger test structure is
submitted to additional AL when compared to the three-finger test structure, it did not
show more variation, but it shows much larger variation than its counterpart test
85
structures with larger fingers, regardless of the equivalent gate length. This highlights the
need of studying variation due to transistor sizing, which we focus on in Chapter 5.
4.3.3.1
Variance Components and Variation
Similar to the analysis of the other test structures, Table 4-13 shows the breakdown of
the sources of variation for the test structures with split gate lengths. As stated earlier, the
variation in these structures increases as the size of fingers decrease, for both PMOS and
NMOS, but more markedly for NMOS. The variation for all the structures is split almost
evenly between chip to chip and within chip.
Within
Chip
Or2
L
m
I
C
[A)21
[qLA
Estimated
Within
hip-
Total
Chip %
2[(A)
1i L
[(A2;
Chi
c
0.72
NMOS
1
2
3
1
2
4
2.26
3.64
5.82
1.18
1.41
3.12
2.34
3.04
6.38
1.71
1.82
4.50
4.75
6.91
12.6
2.97
3.32
7.82
0.54
PMOS
1
2
3
4.05
4.15
5.01
3.21
3.59
5.02
7.51
8.00
10.3
0.72
PMOS
1
2
4
2.41
2.28
2.96
1.88
1.89
3.08
4.44
4.31
6.23
0.54
NMOS
-100%
T-100%
14&491I
Chip to
Chip %
T
47.7%
52.7%
46.3%
39.9%
42.5%
39.9%
53.9%
51.9%
48.5%
54.2%
52.9%
47.5%
Variation
.-100%
1AC
C
52.3%
47.3%
53.7%
60.1%
57.5%
60.1%
46.1%
48.1%
51.5%
45.8%
47.1%
52.5%
1.49%
1.74%
2.18%
1.47%
1.56%
2.16%
7.43%
7.44%
7.85%
7.46%
7.52%
8.08%
Table 4-13: Variances and variation for polysilicon-fingers test structures.
4.4
Summary
All FEOL test structures are successfully measured, with high electrical repeatability
(0.02% error), and leakage currents from the "off' tiles of 2 nA per FEOL row, as
expected from simulation. Structures designed to have layout dependent variation are
analyzed, and to make sure that the means of different structures are different we perform
86
ANOVA on them. We use a nested variance calculation method to separate the variance
due to within chip and between chip sources. With this method we conclude that most
layout-dependent structures have similar magnitudes of variance components due to
within chip versus between chips. Structures with different orientation present an offset
that is consistent between chips and between most structures laid out next to each other.
Interestingly, NMOS and PMOS are affected inversely with orientation, probably
because they are also affected inversely by residual strain. Structures with different
spacing between fingers show a mean shift consistent with a lithographic effect.
Structures with different number of fingers increase their variability as the number of
fingers increase and the size of individual fingers decrease. Our findings are consistent
with the ones found in our previous work [1] using a ring oscillator based test structure.
Chapter 5 studies the transistors at different bias conditions, gathering I-V curves,
something that our previous test chip was incapable of.
87
88
Chapter 5
Results and Analysis of Test Structures of Transistors of
Different Sizes
A key feature of our test chip is its ability to measure a large range of currents across
a range of structure types, and with enough replication of structures to gather variation
statistics. The test chip includes NMOS and PMOS transistors of three different gate
lengths (0.18 tm, 0.36 Itm, 0.54 itm) and 11 different gate widths (from 0.50 ptm to
3.0 [tm in 0.25 [tm intervals), for a total of 33 unique NMOS DUTs and 33 unique PMOS
DUTs, as explained in more detail in Section 3.1.1.
In this chapter we will first discuss in Section 5.1 the functionality of the test chip in
terms of voltage sweeps, and pinpoint its limitations. Section 5.2 studies the transistors in
saturation, while Section 5.3 studies the transistor response to voltage sweeps, including
threshold voltage extraction and analysis. Section 5.4 summarizes the findings presented
in the chapter.
5.1
Functionality
All of the transistors of different sizes are subjected to both reference voltage
(theoretically equivalent to VDS, via a feedback network) and gate voltage sweeps. An
example of a measured device is shown in Figure 5-1, where we see that the
measurements closely resemble transistor curves up to small values of VDS, when our
system reaches its limits as discussed in Section 2.7. In this plot we show a drain voltage
sweep at different gate bias points for an NMOS transistor of dimensions of
0.50 gm/0. 18 pm channel width and length.
89
VDS Sweep, NMOS 0.50u/0.18u
x 10-4
3.5
32.5-
2(1.5-
0.5 0
-0.5
0
VREF
Figure 5-1:
VDS
0.5
(controls
VDS
1.5
1
[V]
feedback)
voltage through
2
sweep for VGS ranging from 0-1.8V in 0.1V intervals.
Figure 5-2 shows the semi-log plot of the measured I-V gathered curves for a VDS
sweep of the same device, an NMOS transistor of 0.50 [tm/0.18 gm channel width and
length, at different gate voltages. As discussed in Section 2.7, our design does not gather
data under 2 nA because of the leakage of the "off' tiles in the row, but we are able to
measure currents above that point. Our output swing from the feedback network is
limited more than expected in simulation (refer to Section 2.7), and our system reaches a
limit in regulated VDS supply at a minimum of about 0.2 V.
We are able to gather measurements for VREF
Of
100 mV if we lower the opamp's
ground to -100 mV, as shown in Figure 5-3. We believe that this is due to the bias of the
output buffer, which limits the output swing of the output buffer. By lowering the ground
voltage, Q9 from Figure 2-10 in Chapter 2 can go lower in voltage, hence allowing
measurements at 100 mV, vs. the 200 mV limit observed before in Figure 5-2.
90
10
-4 -------
10
10-4
10
VDS
Sweep, NMOS 0.50u/0.18u
--
-- --
- - - - - - - - ---
--
~- -- -_------------
-
--
-
--
---
- -
-
-V
-- -_Gate=O
-0.6-1.8V
"
8
-5
Gate=O.5V
10
o---------
VGate=.4V
V
0
,
10
10I
7 ---8-
1o
0
0.2
0.4
VREF
VGate=0, .V
Gate=O.3V
0VGate=O.2V
10
0.6
0.8
1
1.2
1.4
1.6
1.8
(controls VDS voltage through feedback) [V]
- ranging from 0 to 1.8 V in
- a VDS sweep for VGS
- of
1 9 -Figure
5-2:- Semi-log
plot
showing the limitation of our measurements.
0.1V intervals,
VDS Sweep, NMOS O.50u/O.18Bu
10--
10
-
- ----
VGateO*2
10
S16
V
10
-teO5V
Gate=O0.4V
10
1
10
0.1
Figure
VREF
(controls VDS voltage through feedback) [V]
5-3: Semi-log plot of a VDs sweep for VGS ranging from 0 to 1.8 V in 0.1V intervals.
The opamp's ground voltage is set at -100 mY.
91
We also observe a small inconsistency in the currents at approximately VDS= 0.7 V at
low VGS. This seems to be due to the "off' PMOS transistors, which share the same
"ground" off gate line with the NMOS (see switch description in Section 2.6). At ground
(0 V), the gate of the PMOS transistors would be "on," but the device is still off because
its source (through a switch) is at the same potential as its drain (supplied by the opamp).
However, even a very small offset between the drain and source of the "off' PMOS can
make it conduct current. This current is not connected to the output current we measure,
but if the offset makes the drain voltage to be at a slightly lower potential than the source
voltage, then the current can flow into the opamp, and it can slightly offset its output
voltage, particularly at low voltages. This problem does not present itself at higher
currents. It is noticed only when VDS is small (under 0.7 V), and even there it is not very
pronounced for currents over 10 nA. To address this issue, in Section 8.3 we propose to
have a separate "off' gate line for the NMOS and PMOS in future implementations.
Despite these limitations, Figure 5-4 illustrates how closely our measured data
matches with that of simulation at large drain voltages. In this plot, VDS is set at 1.8 V.
This graph matches closely with simulated data until the output currents approach the
leakage currents of the off tiles (2 nA). Most of our variation studies reported in this
chapter use these VGS sweeps. The IourVDS curves are valid for most values
VGS,
Of VDS
and
and additional device parameter extractions are possible using these curves.
92
10
10
10
C
Vgs Sweep for 1.8V Vds, NMOS 0.50u/0.1 8u
-
Simulated
-Measured
-4
-5
-
- ----
- --
-6
-- - - -------- - - -- - --- -- - -
10
2 10
0
(.)
--
-------------
---- ----- - -- - -
-7
-8
-10
10
10
Vgs
Figure 5-4: Comparison between simulated and measured data for a VDS of 1.8 V, ranging from
0 to 1.8 V in 0.1 V intervals, for eight replicates of one type of transistor in one chip (N=8).
5.2
Transistors of Different Sizes at Saturation
The NMOS DUTs at bias voltages of VDD = VGATh = 1.8V show a larger variation in
devices with smaller gate length and gate width features, as seen in Figure 5-5. The bar
graph shows the normalized variation oA /Ac
value of the transistor currents, i.e., the
standard deviation of the DUT set divided by the mean for each type of transistor. These
measurements are taken for the eight replicates of the DUT type in each chip, for all 35
packaged chips, hence the total DUT in each case consists of N=280. For each channel
length of 0.18, 0.36 and 0.54 tm, statistics for devices with widths from 0.5 to 3 tm in
0.25 [tm increments are shown (corresponding to the partial annotations in the figure).
93
In Figure 5-5 there is a clear dependency of variation on the size of transistors. The
larger relative variation is seen not only for smaller gate lengths, but also for smaller gate
widths. A similar, although noisier pattern, is also found for PMOS transistors, as shown
in Figure 5-6.
Normalized NMOS Variation per Size
0.0180.0160.0140.0120
0
C
C
0.010.008-
0.006E
C/5 0.0040.0020
L=0.18u
L=0.36u
L=0.54u
W=0.50u-3.Ou
W=0.50u-3.Ou
W=0.50u-3.Ou
Figure 5-5: Variation in NMOS currents at VDS=1.8V and VGS=1.8V, N=280 (8 replicates in 35 chips).
Normalized PMOS Variation per Size
0.025
C:
-
0.02-
0
U) 0.0150
C)
CO
()
0.01 F
0)
E5
0.005 F
0
L=0.18u
W=0.50u-3.Ou
L=0.36u
W=0.50u-3.Ou
L=0.54u
W=0.50u-3.Ou
Figure 5-6: Variation in PMOS currents at VDS=1.8V and VGS=O V, N=248 (8 replicates in 31 chips).
94
The measurements for the PMOS devices are taken for the eight replicates in 31
chips, hence N=248. The entire set of 35 chips is not available for this study, as some
chips were either damaged in the testing process or were rejected as outliers.
The variation seen in both NMOS and PMOS transistors follow Pelgrom's model [35]
for dependence in total channel area, as seen in Figure 5-7 and Figure 5-8. The fit of the
NMOS transistors is closer to the ideal slope of 1 than the PMOS. The PMOS
measurements are very linear with respect to channel area, but their extrapolation to
infinite area (zero on the x axis) does not converge to zero variation. With the x
coordinate set to zero (or infinite area), the linear fit for the NMOS devices is R2 = 0.96,
and R 2 = 0.83 for the PMOS devices.
Linearity of NMOS Transistor Variation According to Size
0.020 -
0.018
-I
SI
I
2
=0.96
0.016 -=R
S0.014
E 0.0120.008 S0.006
0.002 -
-
-
0.006
~t
I
I
I
I
I
0.000
0
1
2
3
4
1/Square Root of Area
Figure 5-7: Relative current variation in NMOS transistors as a function of device area.
95
LineariF y of PMOS Transistor Variation According to Size
-, - - -,
-, , - -,
- ----0.030 7
I
-I-
I
- 7
I
-1 T
-
0.025
i
0|
-7
I
I
I
,R2=
R2=0.83
'0
(D
0.020
Xa ~0.015
I
I
I
I
- -1T
-
I1
1 |
-
I
-
-
I
I
-
I7
F
1-
Ir
- II -
TI-I-
-
-
10.010
AAIC
----T
0.005 -
T
Ci000A
.UUU
-
I
F
I
0
I
|
1
T
I
I -
-I
T
I
I
I
2
3
I
I
4
1/Square Root of Area
Figure 5-8: Relative current variation in PMOS transistors as a function of device area.
The variation values and variance breakdowns (chip to chip and within chip
components as percentage of the total) are shown in Table 5-1 for the NMOS transistors
and in Table 5-2 for the PMOS.
NMOS structures showed aggregate
uA/IAC
variation ranging from 2.4% for the
smallest test structure to 0.89% for the largest. The variation in the PMOS is larger,
ranging from 7.3% to 6.9%. The NMOS devices with gate lengths of 0.18 pm show, for
the most part, a larger variation component due to within chip variation. As most
structures become larger, especially the PMOS, the relative proportion of within chip and
chip to chip variation start to become more even. However, when we look at all of the
structures as a whole, the within chip variation in the NMOS is 27.4% and in the PMOS
it is 42.9% of the total variation oU .
96
.- -
Gate
Within
Chip
-.
- Z.1-1
--
---
-
-
-,
-" -
---
Estimated Estimated
Total
Chip-Chip
-
-'.
-
- -- M
,-
Within
Chip %
S-ECC100%
.
Chip to
Chip%
.100%
t
IA
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.54
0.54
0.54
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
27.5
43.4
51.7
78.0
82.1
111
127
145
185
212
199
5.30
7.95
9.52
13.8
17.4
20.1
24.6
29.2
32.9
39.2
43.0
2.16
3.19
4.38
26.3
70.4
117
162
236
318
382
451
545
653
738
4.00
7.54
11.3
15.9
23.9
26.7
29.9
40.3
45.5
47.9
63.2
2.68
4.42
6.02
55.5
117
172
245
323
436
516
605
742
878
949
9.63
16.0
21.4
30.5
42.4
48.1
56.0
71.3
80.5
89.5
109
4.97
7.81
10.7
49.5%
37.3%
30.0%
31.9%
25.4%
25.6%
24.6%
24.0%
25.0%
24.1%
20.9%
55.1%
49.7%
44.5%
45.1%
41.1%
41.9%
43.8%
40.9%
40.9%
43.8%
39.5%
43.4%
40.8%
41.1%
50.6%
62.7%
70.0%
68.2%
74.6%
74.5%
75.5%
76.0%
75.0%
75.9%
79.1%
44.9%
50.3%
55.5%
54.9%
58.9%
58.2%
56.2%
59.1%
59.1%
56.2%
60.5%
56.6%
59.2%
58.9%
2.38%
2.42%
2.25%
2.19%
2.11%
2.13%
2.04%
1.98%
1.99%
1.99%
1.91%
1.65%
1.48%
1.31%
1.27%
1.25%
1.15%
1.09%
1.10%
1.06%
1.02%
1.03%
1.60%
1.39%
1.23%
0.54
1.25
6.61
7.28
14.3
46.2%
53.8%
1.15%
58.9%
57.4%
1.05%
1.01%
0.54
0.54
1.50
1.75
7.01
9.08
9.60
11.7
17.0
21.3
41.1%
42.6%
0.54
2.00
11.0
15.1
26.8
41.1%
58.9%
1.00%
0.54
2.25
13.3
18.1
32.3
41.3%
58.7%
0.98%
0.54
2.50
13.8
19.3
34.0
40.6%
59.4%
0.90%
0.54
0.54
2.75
3.00
15.1
18.3
19.9
27.0
36.0
46.4
42.0%
39.5%
58.0%
60.5%
0.85%
0.89%
1 8
Table 5-1: Variances and variation in saturation current, VDS=VGS= . V, for NMOS transistors of
different sizes, N=560.
97
Gate
Within
Chip
Estimated
Chip-Chip
Estimated
Total
Within
Chip %
100%
W
[11m]
L
[11
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
]
2
36.0
73.8
131
184
244
350
453
515
626
753
846
9.46
19.4
29.7
48.1
65.0
87.1
112
143
178
211
235
4.66
9.11
15.6
23.7
32.4
43.2
55.8
68.8
85.8
103
121
2
40.9
85.2
154
233
331
468
591
758
906
1120
1300
7.86
15.6
26.0
40.6
58.1
80.5
103
129
158
188
226
3.47
6.92
12.1
18.2
27.7
36.5
46.2
58.4
71.6
88.6
104
79.1
164
293
429
590
840
1070
1310
1570
1920
2200
17.9
36.2
57.6
91.7
127
173
222.0
281
348
412
475
8.42
16.6
28.6
43.5
62.1
82.4
105
132
163.0
198.0
232
Chip to
Chip %
100%
Variation
IAC
YT
45.5%
45.1%
44.7%
43.0%
41.4%
41.7%
42.3%
39.5%
39.8%
39.2%
38.5%
52.8%
53.5%
51.6%
52.4%
51.1%
50.3%
50.4%
51.0%
51.3%
51.3%
49.3%
55.3%
54.9%
54.3%
54.6%
52.1%
52.4%
52.9%
52.3%
52.7%
52.0%
52.1%
54.5%
54.9%
55.3%
57.1%
58.6%
58.3%
57.8%
60.5%
60.2%
60.8%
61.5%
47.2%
46.5%
48.4%
47.6%
48.9%
49.7%
49.6%
49.0%
48.7%
48.7%
50.7%
44.7%
45.1%
45.7%
45.4%
47.9%
47.6%
47.1%
47.7%
47.3%
48.0%
47.9%
7.30%
7.16%
7.27%
7.03%
6.92%
7.02%
6.95%
6.82%
6.71%
6.75%
6.64%
7.12%
7.04%
6.82%
6.91%
6.82%
6.80%
6.76%
6.74%
6.75%
6.65%
6.57%
7.18%
7.04%
7.14%
7.07%
7.11%
7.00%
6.96%
6.88%
6.89%
6.89%
6.85%
Table 5-2: Variances and variation in saturation current, VDs=1.8 V and VGs=O V, for NMOS
transistors of different sizes, N=496.
98
Transistorsof Different Sizes with Voltage Sweeps
5.3
Each DUT of the "transistors of different sizes" category is measured at different bias
voltages to characterize variation dependencies. Figure 5-9 shows an example set of
current versus
VGATE
curves, at different reference voltage bias conditions. These
measurements can be carried out across the large set of structures with different device
sizes, and can reveal interesting information about device variations.
x 10-4
VGS Sweep, NMOS 0.50u/0.18u
VDS=1.8V
32.5
/
VDS=0.5V
22
1.50
VDS=0.1V
VD=O
1.5
0.501
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VGS [V]
Figure 5-9: VGATE sweep for transistor in scan chain at VDs of 0.1 V to 1.8 V,
and opamp ground set at -100mV.
5.3.1 Transistorsof Different Sizes with Gate Voltage Sweeps
Figure 5-10 plots the overall variation in output current across all device replicates in
a single chip, for transistors designed at a given gate length. The bias conditions are 1.8 V
for VDD and a voltage sweep of VGATE values. The figure clearly illustrates how variation
in sub-threshold is substantially greater in devices with smaller gate lengths. Figure 5-10
99
shows the normalized variation in output current at different gate voltages for NMOS
transistors of different sizes, calculated as the square root of the aggregate variance per
gate length divided by the aggregated mean per gate length,
UA/IAC
. The plot covers
different gate voltages (from 0 V to 1.8 V) at 0.01 V intervals, with drain voltages set at
1.8 V.
Current Variation for all NMOS Structures
0.25
I
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0)
I
I
I
I
I
I
I
I
I
i
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
r
I
I
I
I
I
0.15F
I
I
I
r
*-~Iength=O.18u--f
0.2
I
I
I
I
I
I
-
r
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
r
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Iength=0.36u
I
I
I
I
E
>) 0.1
I
I
I
I
0
0
0.2
0.4
I
0.6
0.8
I
I
I
I
I
I
I
I
0.05
I
I
I
I
ength=0.54u
1
1.2
1.4
I
I
I
I
I
I
I
I
I
I
1.6
1.8
2
Gate Voltage
Figure 5-10: Normalized variation (a/p) of the output current at different VGATE values, for devices
with different channel lengths. Measurements of one test chip, N=176 (16 replicates of 11 different
gate widths at a fixed gate length).
The current equations for both the sub-threshold and saturation regimes for a large
VDS voltage, as provided by [36] and [37] respectively, are:
VGS -VT
ISub =
ION =
Joe s
K(VGS
-VT)'
(5.1)
(5.2)
100
The sub-threshold slope behavior [38] indicates that in this region, ideally, there can
be up to a lIx increase in currents for a 60 mV increase in voltage. This slope is the
steepest when the device is deep into the sub-threshold region, and therefore the most
variation can be found there. Because this is the maximum point of the slope, the
variation is expected to decrease as
VGATE
decreases, as the currents of the MOS
transistor become very small as the transistor turns off [26]. However, our measured data
peaked earlier and decreased faster and more than expected from simulation, as seen in
Figure 5-11.
Simulated Transistor 0.50um/0.18um
0.45
0.4 ----------------------------------------
2C 0.35 ---------------------0 0.5 ------------00.5----------
--------
---------------------------------------
--
--
-
Cl)
iL--------------
L--------------
.2b-------L--------------
0'
0
E
CD
0 .1 - - - - - - -
----
0 .05
0
0
- -
- - - - -- - - - -r
---
- -
0.5
- - -- - - -
- - - - - - - -7 - - - - - - -
1
Gate Voltage
1.5
2
Figure 5-11: Variation of a simulated transistor. The variance is calculated from the curve of a
transistor in a typical simulation corner and another transistor with a 5% variation in VT.
Figure 5-11 shows the simulation of an NMOS transistor with dimensions of
0.50 ptm/0. 18 tm. The transistor is simulated with a typical model (acquiring the range of
101
currents called Ii), and then with a modified model with 5% variation in VT(acquiring the
range of currents called I2). We then determine the standard deviation of these I] and I2
currents with respect to each other, at each gate voltage. In Figure 5-11 we plot this
standard deviation divided by the mean current at each gate voltage. For this simulation
experiment, the sub-threshold variation peaks at -0.1 VGSThe discrepancy between the simulated and measured data is due to the very low
currents measured at less than 0.3 V of gate voltage. These currents are on the order of a
few nA and below. Because the system's leakage currents are approximately 2 nA (see
Section 4.1.2), we are unable to measure currents lower than this, and hence our variation
analysis hits its limit. The peak of the variation was likely higher than that seen in
Figure 5-10, because the peak likely occurs at gate voltages under 0.3 V.
Regardless of the limitation of the measurement, Figure 5-10 clearly shows that
smaller length devices have much larger relative variation than larger devices. It also
shows much larger relative variation in sub-threshold, likely due to current exponential
dependence on VT, as suggested in [26]. Equation (5.3) shows the derivative of the subthreshold current with respect to VT.
ai
Sub _
TV
-e
VGS~ VT
GS
(5.3)
s
In equation (5.3) it is evident that as gate voltages decrease, the current can be more
affected due to variations in VT, which agrees with our findings in the sub-threshold
region. This shows the high impact of VT variation, which we study in the next section.
5.3.2 Threshold Voltage VariationAnalysis
Threshold voltage variation is of increasing concern in advanced technologies [39], as
its continual scaling requirements pose several technology and circuit design challenges.
102
For this analysis, threshold voltages (Vr) are obtained using the linear extrapolation
method in the saturation region [25] with the alpha power-law MOS model [37], [40].
5.3.2.1
NMOS Threshold Voltage
All the NMOS devices of different sizes have their threshold voltage calculated with
the linear extrapolation method, as mentioned above. For this study, the parameter x is
set to 1.32 for 0.18 gm gate lengths, 1.62 for 0.36 gm gate lengths and 1.69 for 0.54 gm
gate lengths, by fitting them to the measured data. VT voltages are calculated to be 0.53 V
for the smallest NMOS devices and 0.49 V for the largest, which agrees with values for
this technology (0.18 gm CMOS Logic), according to the manufacturer's test data for a
logic process (typical library).
11
0.55
~VIdIMl
.,lIJ
m.. Al
Ml
~afr~V
- ---------- OTS
A%
0
O0
0.54
0.53
INI
0.52
CO,
0i
7-
-------
0.51
-
L=0.18u
0.5
-
I
---
W=O.SOu-3.Ou -
-W'
L=0.54u
50u
0.49
L=0.36u
W=0.50u-3.Ou
AR
Different NMOS Transistors
Figure 5-12: NMOS
VT
error-bar plots, ±1-a bars shown. N=480.
Figure 5-12 plots the calculated threshold voltage. In this plot, the mean across all 16
replicates of the NMOS devices of different sizes, and across 30 chips is shown. The
103
error bar is the one standard deviation across all 480 devices per size around the
aggregated mean. These results are tabulated in Table 5-3.
Gate
W
L
Average VT
VAC [V]
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.529
0.532
0.532
0.532
0.529
0.527
0.525
0.524
0.522
0.521
0.519
0.498
0.501
0.502
0.502
0.501
0.500
0.498
0.498
0.496
0.495
0.494
0.488
0.493
0.494
0.494
0.493
0.492
0.491
0.490
0.489
0.488
0.487
Table
5-3: Tabulated NMOS
Standard Deviation
12.0
9.36
9.05
7.94
6.97
6.68
6.67
6.02
5.27
5.45
5.00
7.40
5.65
5.03
4.57
4.29
3.97
3.79
3.30
3.33
3.45
3.05
5.33
4.71
3.97
3.61
3.14
3.13
3.05
2.85
2.77
2.65
2.55
o [MV)
VT calculation for devices of different sizes.
104
Threshold voltages follow a pattern of decreasing for larger gate widths for a given
gate length, in agreement with simulations and with the reverse short channel effect
(RSCE) [34].
Table 5-4 shows by a three-way ANOVA that the difference in VT between devices
of different gate widths and gate lengths are statistically significant. The three-way
ANOVA accounts for the difference in mean per DUT gate length, gate width, and also
per chip. A three-way ANOVA implies that there are three factors at work; in our case
they are the DUT designed gate length, the DUT designed gate width, and the chip
number. The implicit model for the three-way ANOVA is shown in (5.4).
V =V,+VL +V
+ V, + N(O,u2 )
(5.4)
In the model shown in (5.4), V, represents the overall mean of the threshold voltage
of a test structure type, VL represents the threshold voltage deviations given the designed
gate length, Vw represents the threshold voltage deviations given the designed gate width,
and V, represents the threshold voltage deviations per chip. N(0,U ) accounts for
random disturbances. The test shows that the differences in VT mean are significant.
NMOS Threshold Voltage
Sum Sq.
Source
1.1265
Chip
0.1483
Gate Width
3.746
Gate Length
Error
0.8218
5.8425
Total
d.f.
29
10
2
15798
15839
Prob>F
Mean Sq. F
0
0.0388 746.7216
0
0.0148
285.002
0
1.873 3.60E+04
5.20E-05
Table 5-4: Three-way ANOVA for NMOS threshold voltage.
Our measurements also show that variation
-A/7AC
is larger in smaller devices for
both gate length and width, as seen in Figure 5-13. The measurements shown are for
105
NMOS transistors in both FEOL rows (16 replicates per device) in 30 test chips, hence
N = 480. The variation is illustrated in Figure 5-13. Figure 5-14 shows the linear
correlation of relative variation to the square root of the area, following Pelgrom's model
[35], [41].
Normalized Variation Vt NMOS
0.025
0.02 - -- -
- - - - -8 -
- -
- -
0 .0 15 -
- - -
- |
I|
-
- -
-- - - -- -
-- -
-- -
- -
I
I
------
- - - --
-
S 0.01 E
0.005 -MEEEE
0
L=0.54u
W=0.50u-3.Ou
L=0.36u
W=0.50u-3.Ou
L=O. 18u
W=0.50u-3.Ou
Figure 5-13: Variation in NMOS threshold voltage.
Linearity of NMOS Threshold Voltage
Variation According to Size
1A E-02
1.2E-02
-
-
-I
I
-
-
-
02=0.
, 1.OE-02
--
8.OE-03lo
-
6.OE-03-4.OE-03
--
-
,
-
-
-
-
-
-
2.OE-03-O.OE+00
0
0.5
1
1.5
2
2.5
3
3.5
1NArea [gm-1]
Figure
5-14: Linearity of NMOS threshold voltage according to size.
106
MMw_ ___Qww
Within
Chip
Gate
W
L
[g[
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Estimated Estimated
Total
Chip-Chip
2CC
UEC
V]n
150
104
93.8
75.8
64.2
59.0
63.6
47.7
41.9
45.6
36.8
67.6
46.1
37.3
37.4
29.9
27.4
27.5
25.0
25.0
25.1
25.6
44.8
33.8
27.9
22.9
23.9
24.1
22.1
21.5
21.2
20.5
19.0
[2 V]
217
216
252
221
217
232
226
209
208
204
203
51.4
53.8
56.4
58.7
60.3
60.4
55.4
62.8
59.1
59.5
63.4
44.6
48.8
50.9
51.1
48.4
57.5
54.7
56.0
56.4
51.9
53.7
T
V]2
367
319
346
296
282
291
290
257
249
250
240
119
99.9
93.7
96.1
90.2
87.9
82.9
87.8
84.1
84.5
89.0
89.4
82.6
78.8
74.0
72.3
81.6
76.8
77.5
77.6
72.4
72.7
Within
Chip %
Chip to
Chip %
-10%
-YE.100%
40.8%
32.5%
27.1%
25.6%
22.8%
20.2%
22.0%
18.6%
16.8%
18.2%
15.3%
56.8%
46.1%
39.8%
39.0%
33.2%
31.2%
33.2%
28.5%
29.7%
29.7%
28.8%
50.1%
40.9%
35.4%
31.0%
33.1%
29.5%
28.8%
27.8%
27.3%
28.3%
26.1%
59.2%
67.5%
72.9%
74.4%
77.2%
79.8%
78.0%
81.4%
83.2%
81.8%
84.7%
43.2%
53.9%
60.2%
61.1%
66.8%
68.8%
66.8%
71.5%
70.3%
70.4%
71.2%
49.9%
59.1%
64.6%
69.0%
67.0%
70.5%
71.2%
72.3%
72.7%
71.7%
73.9%
OCy
.
Vaation
VAC
.Ecc
100
2.29%
1.77%
1.69%
1.50%
1.33%
1.28%
1.27%
1.15%
1.01%
1.04%
0.96%
1.48%
1.13%
1.00%
0.92%
0.86%
0.78%
0.76%
0.66%
0.67%
0.69%
0.62%
1.09%
0.95%
0.80%
0.73%
0.64%
0.63%
0.62%
0.58%
0.56%
0.55%
0.53%
Table 5-5: Variances and variation for VT in NMOS transistors of different sizes. N=480.
107
The variation values and variance breakdowns (between chip to chip and within chip)
for the NMOS VT measurements are shown in Table 5-5. For almost all structures (except
for the smallest NMOS, which was the one showing the most variation) the chip to chip
component is the largest contributor to the overall variance. On average 64% of the
variation seen in the VT structures is due to the chip to chip component, suggesting that it
has a large spatial trend within the wafer. However, a large within chip level in VT is also
present.
5.3.2.2
PMOS Threshold Voltage
The PMOS test structures of different sizes also have their threshold voltage
calculated with the linear extrapolation method, as stated in Section 5.3.2. For this study
the parameter c is set to 2 for all gate lengths, based on a fit to our measured data. The
absolute values of threshold voltages are calculated to be 0.57 V for the smallest NMOS
devices and 0.54 V for the largest, which is slightly larger than the expected values for
this technology (0.53 V for a typical library in 0.18 tm CMOS logic), but still within the
10% range of the provided manufacturer's corners. The threshold voltages results are
plotted in Figure 5-15. In this plot, the mean across all 16 replicates of the PMOS devices
of different sizes, and across 26 chips is shown. The error bar is the one standard
deviation across all 416 devices per size around that grand mean. These results are
tabulated in Table 5-3.
108
Threshold Voltage PMOS
0.6
0.59
L=0.18u
W=0.50u-3.Ou
0.58
0)
0)
0.57
0
~0
0.56
L=0.54u
-5
C,)
0)
-C
0.55
I-
0.54
---
-----------q
----
-----
W=0.50u-3.Ou
-po--
p;--
0.53
0.52
L=0.36u
W=0.50u-3.Ou
Different PMOS Transistors
Figure 5-15: PMOS VT error-bar plots, ±1-(y bars shown. N=416.
109
Gate
Average
VT
Standard Deviation
W
L
VAC [VI
UA [mV]
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.573
0.575
0.577
0.577
0.578
0.577
0.577
0.577
0.577
0.577
0.577
0.538
0.542
0.543
0.544
0.545
0.545
0.546
0.546
0.547
0.547
0.548
0.530
0.533
0.535
0.536
0.537
0.538
0.539
0.539
0.539
0.540
0.541
14.0
12.7
11.4
11.0
10.2
9.97
9.78
8.92
8.64
8.62
8.90
8.77
8.57
7.73
7.65
7.01
7.14
6.66
6.59
6.50
6.33
6.11
7.45
6.78
6.48
6.08
6.27
5.89
5.71
5.51
5.61
5.41
5.29
Table
5-6: Tabulated PMOS
VT calculation
for devices of different sizes.
110
Threshold voltages follow a pattern that agrees with regular transistor simulations.
Table 5-7 shows by a three-way ANOVA that the difference in VT between devices of
different gate widths and gate lengths is statistically significant. This analysis is similar to
the three-way ANOVA explained in Section 5.3.2.1. The implicit model for the threeway ANOVA is the same as in the NMOS study, as previously given in equation (5.4).
PMOS Threshold Voltage
Source
Sum Sq.
Chip
0.9779
Gate Width
0.0751
Gate Length
4.0109
1.47
Error
Total
6.5339
d.f.
Mean Sq.
25
0.0391
10
0.0075
2
2.0055
13690 1.07E-04
13727
F
364.3013
69.9255
1.87E+04
Prob>F
0
0
0
Table 5-7: Three-way ANOVA for NMOS threshold voltage.
Our measurements also show that variation
uA /IAC
is larger in smaller devices in
both gate length and width, as seen in Figure 5-16, but the trend is not as consistent as
with the NMOS devices. The Pelgrom [35] [41] relation fit, shown in Figure 5-17, is also
not as good as with the NMOS. The relationship between variation and square root of
area is in fact quite linear (R2= 0.90), but with an offset of 0.005 in the y axis, due to
measured variation that is independent of size. The R 2 for the fit when the y intercept is
set to zero is only 0.66. An offset, although smaller, is also seen in the PMOS saturation
study shown in Section 5.2.
111
Normalized Variation Vt PMOS
0.025
0
F
F
F
F-F-F-
- -----
- ------ L---
-
- - --
$- -
0.02
F
FFC)
F
0.015
0
-C
C:
0.01
E
M)
Fn)
0.005
0
L=0.54u
W=0.50u-3.Ou
L=0.36u
W=0.50u-3.Ou
L=0.18u
W=0.50u-3.Ou
Figure 5-16: Variation in PMOS threshold voltage.
Linearity of PMOS Threshold Voltage
Variation According to Size
1.8E-02 T 1.6E-02
-F
1~
T
--
T
-
-
-
-L
1.4E-02
R2=0.66
-
1.2E-02
1.OE-02 FU 8.OE-03 6.OE-03 4.OE-03 2.OE-03-
-
T- --
-fI -- -|F
'
- -
r
-F1
-
--
7
F
i T
-
1
- I7T
F
l
I ---- - I +
- -I- - ---I I
I --- 1
_______________|
0.OE+00
0
0.5
1
1.5
2
2.5
3
3.5
1NArea [gm-1]
Figure 5-17: Linearity of PMOS threshold voltage according to size.
112
Gate Within
Chip
-
Estimated
Chip-Chip
Estimated
Total
Within
Chip %
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.18
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.36
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.54
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
Table
UT
yy
[
231
185
164
166
134
135
134
112
113
108
109
104
106
97.2
90.7
80.6
82.9
78.4
76.6
75.1
75.5
67.0
85.6
78.2
72.6
70.4
71.7
63.7
65.5
61.5
63.6
61.4
58.5
132
111
151
158
161
163
162
178
166
175
168
48.6
52.0
46.6
45.0
52.7
49.9
56.8
47.6
54.3
50.1
52.2
35.6
34.4
39.9
39.6
37.2
37.7
35.6
39.5
36.1
35.8
35.4
363
296
315
324
295
298
297
289
279
283
277
152
158
144
136
133
133
135
124
129
126
119
121
113
113
110
109
101
101
101
99.6
97.2
93.9
63.6%
62.4%
52.2%
51.2%
45.4%
45.4%
45.3%
38.6%
40.7%
38.1%
39.4%
68.1%
67.2%
67.6%
66.8%
60.5%
62.5%
58.0%
61.7%
58.1%
60.1%
56.2%
70.6%
69.5%
64.6%
64.0%
65.9%
62.8%
64.8%
60.9%
63.8%
63.2%
62.3%
%
1.
.100%
L
[Wn] [pn]
Chi
Chip %
UT
Vatai
V AC
%
O
36.4%
37.6%
47.8%
48.8%
54.6%
54.6%
54.7%
61.5%
59.3%
61.9%
60.6%
31.9%
32.9%
32.4%
33.2%
39.5%
37.6%
42.0%
38.3%
41.9%
39.9%
43.8%
29.4%
30.5%
35.5%
36.0%
34.2%
37.2%
35.3%
39.1%
36.2%
36.8%
37.7%
2.44%
2.20%
1.98%
1.92%
1.76%
1.73%
1.69%
1.54%
1.50%
1.49%
1.54%
1.63%
1.58%
1.42%
1.41%
1.29%
1.31%
1.22%
1.21%
1.19%
1.16%
1.12%
1.41%
1.27%
1.21%
1.13%
1.17%
1.09%
1.06%
1.02%
1.04%
1.00%
0.98%
5-8: Variances and variation for VT in PMOS transistors of different sizes. N=416.
113
The variation values and variance breakdowns (between chip to chip and within chip)
for the PMOS VT measurements are shown in Table 5-8. For most structures, the within
chip component is the largest contributor to the overall variance, but the within and chip
to chip components are not very far apart. On average 58 % of the variation seen in the
PMOS VT structures is due to the within chip component, suggesting that neither inter or
intra die variation is dominant in this study.
5.4
Summary
FEOL test structures that consist of transistors of different sizes are tested over a
range of bias voltages, producing measurements for reference voltage values (drain
voltage of DUTs) down to 0.2 V for the regular setup, and currents as low as 2 nA. At
currents under 2 nA the measured currents are the leakage currents of the "off' tiles. If
the ground of the operational amplifier is lowered to -0.1V, then we can gather currents
for VREF down to 100 mV.
The gate voltages sweep closely match simulation for VDS of 1.8V, and with those
curves we show analysis of variation due to sizing, and threshold voltage extraction and
variation. The variation of both NMOS and PMOS transistors follows a Pelgrom model,
adding confidence in our findings. The variation in the threshold voltage for the NMOS
transistors also fits Pelgrom's model, but the PMOS devices do not have a very close fit.
The variance seems to split almost evenly between inter and intra die variation for
threshold voltage, with a slightly higher intra die component for the current variation.
This concludes the analysis of the FEOL test structures, and Chapter 6 discusses the
testing and results of the BEOL test structures.
114
Chapter 6
Results and Analysis of Interconnect Test Structures
The goal in the testing and analysis of the interconnect or back end of line (BEOL)
structures is to be able to systematically and efficiently extract capacitance values using a
scan chain, and to understand changes in capacitance due to process induced variation in
the interconnect structures used for the capacitive load. This analysis is important for
modem circuit design, in which the interconnect variations are no longer negligible;
although interconnect variations tend to have a smaller impact than the device variations
on circuit performance, the relative impact of interconnect variation in future
technologies is expected to increase [21].
In this chapter we first look at how the measurements are calculated in Section 6.1.
The three types of structures that are considered in this study, each of which is dominated
by a different component of capacitance, are the coupling capacitance load, plane to
plane capacitance load and a grid (or overlap) capacitance load, all measured using a
CBCM approach, and an overview of the calculated capacitances is presented in
Section 6.2. Each of these interconnect parasitic loads is tested in metals 1, 2, 3, 4 and 5
(metal 6 was reserved for signals). The findings of testing these structures are presented
in Sections 6.3 (for the coupling capacitance), 6.4 (for the pane to plane capacitance), and
6.5 (for the crossover capacitance). We summarize the analysis of the interconnect test
structures in Section 6.6.
6.1
Measurement Method Review and Adjustments
Interconnect capacitances are measured using a modified differential CBCM method
[23], [24], [25], integrated with switches so it can also be used with the scan chain
115
approach, as illustrated in Figure 3-6 in Chapter 3.
As explained in more detail in Section 3.2, with this method, the capacitance between
two nodes of interest is charged and discharged through the pseudo-inverters connected
to the gate input signals during "Step I " and "Step 2," as shown in Figure 3-6. The
average source currents in these steps provide information to calculate C1 as described in
[23] and [24]. In "Step 3," the two nodes of the capacitor of interest are kept at the same
potential, and one can measure the current and calculate the capacitance due to the
CBCM structure alone (without the interconnect load capacitance), which can then be
subtracted from the measurements of steps 1 and 2.
However, reviewing out testing results we find that the blank capacitance test
structures in the scan chain, or structures that have no capacitance connected to the
CBCM structure, measure a non-zero capacitance value. "Step 3" should subtract
whatever capacitance is present at these blank test structures, and its measured
capacitance value should be zero. This offset may to be due to the limitations of our
testing setup, where the particular board used to connect the signals seems to induce a
measurement offset.
To correct this offset we subtract the value of the blank test structure to the other
capacitance values calculated in each chip. We therefore determine the interconnect
capacitances using equation (6.1).
C
IstepI + Istep2 - Istep3
V DD *Frequency
-
B
(6.1)
2
The constant B is the average capacitance calculated at the blank test structures in
each chip, which accounts for the additional fixed error in capacitance extraction that
may be included in the measurement. This fitting leads to capacitance values close to
116
what were expected by the layout extraction tools, as will be shown in Section 6.2.
The use of the fitting factor comes at the expense of being unable to do the variance
component separation and conclude if the observed variation is mostly due to its within
chip or chip to chip component. This is because we subtract the value of the blank
capacitance B for each chip, and with it we subtract off part of the chip to chip variance
component. This subtraction allows us to understand structure to structure, and within
chip variations, but comes at the cost that we lose chip to chip variation, and so the
variance decomposition into these two components is not possible.
6.1.] ElectricalRepeatability
As already addressed in Section 4.1.1, it is important to have only small errors in the
electrical repeatability so that we can trust that the source of variation seen is not a
measurement error, particularly in the interconnect structures that are measured at a
relatively high frequency (500 KHz). BEOL test structures give a measurement error of
only 0.08% for a single test chip, tested multiple times using "Step 1" biasing, providing
confidence that the data measured is indicative of structure difference rather than
electrical measurement noise.
6.2
Overview of Measured Capacitances Results
All BEOL test structures are successfully tested, as partially illustrated in Figure 6-1.
In this plot, the mean across all 16 replicates of a row of the different BEOL test
structures, and across 35 chips is shown. The error bar is the one standard deviation
across all 560 devices per size around the aggregated mean.
117
Interconnect Capacitances per Type
110
N=560
100
-
--
--- 6 --
----
-T ------
-
-- - -
- -- 7
90
--
80
a)
0D
70
-- -
-
-7 - ---- -T ------ 7-
-
Comb
fl-I T
-- - - -- -- - -- - - --- ------
0
- -
-------
60
050
40
-- -
- - - -- -
- - - - - --
Plane
--- ---------
Grid
30
nf
Figure 6-1: Measurements of interconnect test structures.
Trends shown in Figure 6-1 are as expected. The "comb" structure capacitances,
which focus on within metal layer coupling capacitance at minimum spacing, are much
higher than those of the layer to layer plane or grid structures. We also see that the metal
1 coupling capacitance is higher than in other metal layers, as expected, because the wires
are closer together (the minimum allowed spacing is smaller) in this first layer metal
layer. The "plane" capacitance concentrates on layer to layer capacitance, and is
consistent with expected values given plate size (62 gm by 35 gim) and respective metal
layer dielectric thicknesses. The "grid" test structures concentrate on the crossover
capacitance, which is greatly impacted by both the layer to layer and fringing capacitance
components.
118
Test
Structure
Combs
Plane-Plane
Grid
Metals Used
Ml
M2
M3
M4
M5
M2-M1
M3-M2
M4-M3
M5-M4
M2-M1
M3-M2
M4-M3
M5-M4
Extracted Capacitance
from Diva [fF]
98.82
87.65
88.08
88.29
88.49
24.50
24.45
24.49
24.48
66.88
60.82
60.48
59.88
Measured
Capacitance [fF]
102.68
96.52
96.22
96.06
97.23
27.05
26.06
27.34
27.45
24.66
24.07
25.06
25.25
Table 6-1: Comparison between extracted by simulation and measured capacitances. N=560.
Table 6-1 compares our measured data with the data extracted from the Diva layout
extractor for this technology. The measurements of the combs and plane to plane
capacitances are close to the extracted values, giving us confidence in our measurements.
Measurements for the grid structures are substantially different than the extracted value,
apparently because of an extraction error by the automated simulation-based extraction
tool, which is explained in more detail in Section 6.5.
6.3
Comb Capacitances Results and Analysis
The test structures that focus on the coupling capacitances, referred to as comb test
structures, have the highest measured capacitances, as expected from the extraction. We
are able to measure the difference in capacitance for all metal layers. The calculated
values from the measurements are near, although larger by approximately 9%, to those
predicted by the automated simulation-based extraction tool, as seen in Table 6-1.
The difference in means between the different comb test structures are statistically
significant based on the two-way ANOVA tests shown in Table 6-2. In this case, and
referring to the implicit model for the two-way ANOVA shown in (6.2), y, represents
119
the overall mean of the calculated capacitance of a comb test structure type, ym represents
the capacitance deviations given the designed metal layer (metal 1, 2, 3, 4 and 5), and y,
represents the capacitance deviations per chip for all 35 chips. N(O, a2) accounts for
random disturbances.
y = YO + y, + yc + N(O,a
2
(6.2)
)
We note that, while the subtraction of the blank structure capacitance B for each chip
removes much of the chip to chip variation, the two-way ANOVA indicates that a small
but statistically significant chip to chip variation in the comb and other capacitance test
structure values still remains. As discussed in Section 9.2.3, future work might consider
improvements to the CBCM structure to remove the need for this B correction, enabling
more detailed analysis of chip to chip spatial trends.
Comb Capacitances
Sum Sq.
Source
Metal
1.75E-26
Chip
2.67E-26
3.79E-26
Error
Total
8.21E-26
Mean Sq.
4 4.38E-27
34 7.85E-28
2761 1.37E-29
2799 1
d.f.
F
319.3364
57.2375
Prob>F
0
0
1
Table 6-2: Two-way ANOVA for comb capacitances made with different metal layers.
6.3.1 VariationAnalysis Between FingerSpacing and Thickness
We test the comb test structures with different spacing between the fingers and
different wire widths, as explained in Section 3.2.3. Table 6-3 shows that the variation
does not change much in our test structures as a function of line spacing or wire width.
Furthermore, Table 6-4 shows that the difference in the variance between the structures is
not statistically significant, when we look at the aggregate variance ratio r between the
test structure type with larger spacing between the lines and minimum line width vs. the
120
test structure type with larger line width but minimum spacing. We could not determine
with our data if variation was more heavily due to spacing or wire width. Future work
could revise the experiment and use a larger range of spacing and/or widths of the metals.
Metal
Layer
Variation in Metals
of Minimum Width
And Spacing
=
Variation in Metals
of Minimum Width
and 1.2x Spacing
100%
100%
.100%
CAC
CAC
CAC
4.85%
4.51%
4.67%
4.79%
4.78%
5.25%
5.43%
4.93%
4.76%
5.68%
5.32%
4.72%
4.72%
4.79%
4.94%
1
2
3
4
5
Variation in Metals
of Minimum Spacing
and 1.2x Wider
Table 6-3: Variation (1-sigma/mean) in comb test structures.
22
Ml
M2
M3
M4
M5
Minimum
Width
And
Spacing
0.2985
0.2072
0.2066
0.2114
0.2308
Minimum
Width
and 1.2x
Spacing
0.2159
0.2159
0.1790
0.1675
0.2345
MinItnum
Spacing
and 1.2x
Wider
0.2614
0.2024
0.2142
0.2284
0.2293
r between
s and w
0.68
1.14
0.70
0.54
1.04
Fo.9,5w, 2
1.19
Table 6-4: Variance ratios of coupling test structures.
6.4
Plane to Plane Capacitances Results and Analysis
Plane test structures were successfully measured, and their measurements are also
near although somewhat larger than those predicted by our automated simulation-based
extraction tool, as shown in Table 6-1. The difference between the measured capacitance
of the different metal layers is small, but it is statistically significant as indicated by the
two-way ANOVA in Table 6-5.
121
Comb Capacitances
Sum Sq.
Source
6.71E-28
Metal
2.69E-27
Chip
2.79E-26
Error
3.13E-26
Total
d.f.
3
34
2202
2239
Mean Sq. F
17.6498
2.24E-28
6.2497
7.92E-29
1.27E-29
Prob>F
2.54E-11
0
Table 6-5: Two-way ANOVA for plane to plane test structures.
Similar to the two-way ANOVA for the comb test structures, in the implicit model for
the two-way ANOVA shown in (6.3) y, represents the overall mean of the calculated
capacitance of a plane test structure type, yrepresents the capacitance deviations given
the designed metal layer (metal 1-2, metal 2-3, metal 3-4, and metal 4-5), and y,
represents the deviations per chip for all 35 chips. N(0,u2 ) accounts for random
disturbances.
y
6.5
=
YO + ym + yc + N(0,a 2 )
(6.3)
Grid Capacitances Results and Analysis
In contrast to the coupling and plane capacitances, the measurements obtained from
the grid capacitances differ greatly from the extractions from the automated simulationbased extraction tool using our design kit (0.18 im CMOS Logic). To investigate the
automated simulation-based extraction tool process, we studied the simulation of the two
capacitive loads shown in Figure 6-2. The capacitive load labeled (a) features a crossover
capacitance with fingers that are 30 times further apart than the fingers in the capacitive
load labeled (b). These are minimum width wires, and therefore have a strong fringing
component. The metal lines are metal 2 (yellow) and metal 1 (blue). The metal 1 line is
labeled as node j, while the metal line 2 is labeled as node i.
122
Node i
(a)
Node j
(b)
Figure 6-2: Capacitive loads to study automated simulation-based extraction tool crossover
capacitance extraction.
The extractor calculates the Cij of structure "a" and Cij of structure "b" to be identical
(64.6 aF). It also calculates half of this value for a single crossover (32.3 aF). This is
incorrect according to Wong et al. [42], because the fringing component of the overlap
capacitance is reduced when lines are closer together, as the flux from Ml and M2 is
reduced with less spacing.
Using Wong's [42] closed loop equations for the crossover capacitance between nets i
and j (not to substrate), we can estimate the total capacitance expected for our crossover
structure for metals 1 and 2 to be 7.5 aF, using the thickness of the wires and between
123
metal layers from the design kit. The calculations are shown in Appendix II. We have a
total of 76x25 crossover capacitances, and an additional 8 fF capacitance in a connector
line, for a total of 22.5 fF for our metal 1 to metal 2 grid test structure, which is much
closer to our measurement than the 66.88 fF extracted by the automated simulation-based
extraction tool. The extraction tool's measurement can be estimated by its one-crossover
capacitance (32 aF), multiplied by 76x25 crossover capacitances and an additional 8 fF
capacitance in the connector line, for an approximate total of 68 fF.
Based on these results, it appears that the simulation-based extraction tool suffers
from an extractor error in this (admittedly) unusual tightly packed wire geometry. This
study shows the value of having accurate capacitance measurements on chip, to enable
detection of miscalculations by automated extractors, particularly if the capacitance
geometry or structure is not a commonly generated one. It is not common to have
minimum length wires of the same potential at minimum spacing from each other, but as
technology advances this practice may become more common, in uses such as regular
interconnect fabrics [43]. It should be noted that this is an older design kit that is no
longer supported by the manufacturer, and that this problem might have been fixed in
more recent design kits.
The difference between the measured grid capacitance of the different metal layers is
small, but it is statistically significant as indicated by the two-way ANOVA in Table 6-6.
Similarly to the two-way ANOVA for the comb and plane test structures, in the implicit
model for the two-way ANOVA shown in (6.4), y, represents the overall mean of the
calculated capacitance of a grid test structure type, y, represents the capacitance
deviations given the designed metal layer (metal 1-2, metal 2-3, metal 3-4, and metal
124
4-5), and y, represents the current deviations per chip for all 35 chips. N(0,
2
)
accounts for random disturbances.
y =YO + y, + yc + N(0, a 2 )
_
Comb Capacitances_
Source
Sum Sq.
d.f.
6.71E-28 3
Metal
Chip
2.69E-27 34
Error
2.79E-26 2202
Total
3.13E-26 2239
_
(6.4)
_
Mean Sq.
2.24E-28
7.92E-29
1.27E-29
F
17.6498
6.2497
Prob>F
2.54E-11
0
Table 6-6: Two-way ANOVA for grid test structures.
6.6
Summary
The BEOL test structures were successfully tested, and we were able to map trends
and measure interconnect capacitances in an effective and multiplexed way. We were
unable, however, to pinpoint which source of variation, spacing or metal width, was more
prevalent for the variation in the capacitances that accentuate coupling. All measurements
are tested using a two-way ANOVA, and all of the different means reported are
statistically different. However, the mean differences within structure types or from layer
to layer are generally quite small. All test structures except for the grid measured values
that are close to those expected from an automated extractor. The grid structure is seen to
be miscalculated in the automated extractor, and hand calculations give us confidence in
our measured data. This concludes the testing and analysis of individual test structures;
Chapter 7 studies the spatial behavior across the wafer and within a die of various device
and interconnect test structures.
125
126
Chapter 7 Spatial Analysis
The wafer spatial location of each of our chips is tracked during manufacture. This,
along with the within-chip location from the layout, provides data to perform chip-to-chip
and within-chip spatial analysis. This chapter focuses on analyzing the variations due to
spatial location at the wafer and die level. First, the wafer level trends based on patterns
in the chip-to-chip variation are examined in Section 7.1. Next, in Section 7.2 within-chip
trends are considered for a number of different test structures. Finally, Section 7.3
summarizes the results of the spatial analyses conducted.
4.5
6
7
6
9
07
Figure 7-1: Location of test dies within the wafer. Shaded squares indicate the dies available for
spatial measurement and analysis.
7.1
Chip to Chip Spatial Analysis
Spatial analysis throughout the wafer is possible for our 35 packaged chips, given the
spatial location of each die within the single wafer used for all packaged chips, as shown
in Figure 7-1. The means and normalized standard deviations for each chip of the most
replicated structure, the 3-finger single spaced NMOS transistor, are shown in Figure 7-2.
In this case the statistics are calculated with a set of size N = 32 (16 replicates in each of
two rows on the chip), and the bias condition are in saturation (VDS = VGS = 1.8 V).
127
MR- ---
Chip Means for
- --
- -
Chip Std for
3-Finger NMOS
3-Finger NMOS
164
x 10-6
3
1.62
2.8
1.58
2.4
1.56
2.2
*1.62.
A
2
r1.54
1.8
1.52
Currents
Std of Currents
Figure 7-2: Spatial mean currents (left) and normalized standard deviations (right)
per chip across wafer for NMOS 3-finger structure. N=32.
The trend is not particularly clear across the wafer, but we observe that some of the
higher current dies show less within chip variation for this particular test structure. To
investigate if there is correlation we use equation (7.1), where we have two sets of data: X
refers to the set of data of the mean currents in a chip and Y refers to the set of data of the
standard deviation of the currents in a chip. In (7.1), x is the mean of the population X, y
is the mean of the population Y, x, and yj are the values of the samples X and Y for
chip i, sx and s, are the observed standard deviations for the samples X and Y, and n is
the number of chips.
n
- x)(y_ - y)
I(xi
r=
(
(7.1)
x 100%
(n - 1) sx s
This correlation between the mean currents and their standard deviations for the 3finger single spaced NMOS transistor is not strong, only -24%. That is to say, although
there are some spatial trends in both mean and within chip variation in Figure 7-2, the
mean and variation are not strongly correlated with each other. The overall variation for
the chip to chip means across the wafer is 1.65%.
Figure 7-3 shows the spatial location for the combination of all "NMOS of different
128
:!
-- -- W4
~
-~-~
sizes" test structures combined. There are 33 different structures in this category with
gate lengths from 0.18 gim, 0.36 pm and 0.54 gm, and gate widths of 0.5 gm to 3 gm (in
increments of 0.25 gm), as explained in more detail in Section 3.1.1. There are 16
replicates for each one of the 33 different NMOS test structures in a chip, for a total of
528 samples per chip. The bias conditions are in saturation (VDS
= VGS =
1.8 V). These
plots show a correlation between the current means and the standard deviations per chip
of -26%, again indicating only a weak relationship between within chip variation and
chip mean.
The trend in Figure 7-3 shows that most high current structures are in the north-east
portion of the wafer, and most low current structures are found towards the center of the
wafer. We find a normalized variation of 1.3% in the mean of the different dies.
Chip to Chip Means for all
Chip to Chip Std
-
NMOS Sizes
for all NMOS Sizes
10
10-6
6.75
7.2
7
6.7
6.8
.45
6.6
6.66.
6.2
6.55
6
5.8
5.6
6.5
6.45
5.4
Currents
Std of Currents
Figure 7-3: Spatial saturation mean currents (left) and normalized standard deviations (right)
per chip across wafer for all NMOS of different sizes. N=528.
x10 3
Chip to Chip Means for NMOS VT
0.545
Chip to Chip Std for NMOS VT
10
0.545
0 53
0.525
7
0.52
0.-
6
0.05
.495
Voltage [V]
4
Std of Voltage [V]
Figure 7-4: Spatial saturation mean currents (left) and standard deviations (right) for threshold
voltage of NMOS transistors with 0.18 gm gate length. N=176.
129
Figure 7-4 reaffirms the trend observed in Figure 7-3, showing that the threshold
voltage of the minimum sized NMOS transistors also follows the same pattern: the
largest threshold voltages are towards the center of the wafer (the south-south west corner
of our data) and some of the smallest threshold voltages are towards the north-east corner
of the wafer. The threshold voltages plotted in Figure 7-4 are for all of the 0.18 Rm gate
length NMOS test structures per chip. There are 11 different 0.18 pLm gate length NMOS
test structures per chip, each with gate widths of 0.5 gm to 3 gm (in increments of
0.25 tm), as explained in more detail in Section 3.1.1. There are 16 replicates of each of
the NMOS test structures per chip, hence the sample size is 176. The plots in Figure 7-4
show a correlation between the threshold voltage means and the standard deviations per
chip of -33%. We plot fewer chips in these plots than in Figure 7-3 because some test
chips are damaged in the testing process, and others were outliers. VT calculations are
more prone to measurement glitches than the saturation measurements because of the
voltage sweeps (many more data points sampled).
The trend of having the "slowest" (lower current, highest VT) chips towards the
center of the wafer may be due to wafer scale non-uniformity with typical edge versus
center differences, which typically occurs on CMP and other processes. A possibility is a
variation in oxide thickness across the wafer, which has a first order effect on threshold
voltage variation. We find a range of 2.7 % in the mean of the different dies across the
wafer.
7.2
Within Chip Spatial Analysis
Repetition in the test chip enables spatial analysis per row. Figure 7-5 shows the
spatial trends of the mean output saturation current (at VDS
= VGs
= 1.8 V) of the most
130
ENIENNNIENNNEEMN
-
replicated test structure, the 3-finger, minimum spacing NMOS transistor, which is
replicated 16 times per row. These plots are the die spatial maps averaged across all 35
chips.
Within Chip Current Mean for Both Rows
X1 0-4
I1.600
1.595
1.590
1.585
1.580
N=70
Within Chip Current Mean for Row 1
X1 0-4
1.605
1.600
1.595
1.590
1.585
1.580
1.575
1.570
N=35
Within Chip Current Mean for Row 3
1.605
1.600
1.595
1.585
1.580
1.575
N=35
Figure 7-5: Within-row spatial analysis for most replicated NMOS, showing mean current values for
the sixteen replicates per row for 35 chips. N=35.
At the top of Figure 7-5 we show the aggregated data, averaged across both rows, and
the bottom two plots show each of the two FEOL rows. In the individual rows, there is a
soft trend of current extremes (highest and lowest) towards the edges. This may be
131
because of the low layout density around the edges, that can affect the etching or other
processes. The low pattern density can be seen in the full chip photo, previously shown in
Figure 2-7. The within row means (using the average "both rows" data) have a 0.38%
variation, compared to 1.65% for the die to die variation of the same structure, as found
in Section 7.1. Figure 7-6 shows the standard deviation of these test structures, which
have no clear spatial trend.
Within Chip Current Std for Both Rows
0-6
3.9
3.8
3.7
3.6
I
N=70
Within Chip Current Std for Row 1
3.5
3.4
3.3
3.2
3.1
3.0
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
N=35
Within Chip Current Std for Row 3
X1 0 6
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
N=35
Figure 7-6: Within-row spatial analysis for most replicated NMOS, showing 1-sigma current values
for the sixteen replicates per row for 35 chips. N=35.
132
Because we note no obvious trends in the within die spatial map, we look at
individual dies to see if there is a small within die trend that differs depending on the
location of the chip in the wafer. If there is, for example, a "slanted plane" within die
trend arising from a wafer level "bowel" shaped uniformity, and we average all chips
(e.g., including both left tilting planes with right tilting planes), the within die spatial
information may be lost. We thus consider study the within die trends of three particular
dies: one at the upper right hand side wafer edge (chip 17), one at the left-center edge
(chip 38) and one that is towards the center of the wafer (chip 41), as illustrated in
Figure 7-1.
Figure 7-7 shows the plots for the spatial location of the most replicated NMOS test
structure (three finger, minimum spacing device) at saturation bias conditions
(VDS
=
VGS
=
1.8 V). Each row presents the output current of each device in one row,
with no averaging of any kind. The plots in Figure 7-7 also lack a clear spatial pattern,
and we conclude that there is no obvious spatial trend within die.
Because of the long dimensions of the test row, a trend showing a systematic voltage
drop across the rows is a possibility because of voltage drops in the line. We use Kelvin
sensing connections to prevent this systematic trend. Because such a trend is not observed
in our analysis, it gives us confidence of the functionality of the feedback network to
prevent voltage drops in the long interconnect lines.
133
Within Chip Currents Row I for Chip 17
10-4
1.505
1.6
1.595
1.59
1.585
1.58
1.575
1.57
Within Chip Currents Row 1 for Chip 38
10-4
1.605
1.6
1.595
1.59
1.585
1.58
1.575
1.57
Within Chip Currents Row I for Chip 41
10-4
1.505
1.6
1.595
1.59
1.585
1.58
1.575
1.57
Figure 7-7: Within-row spatial analysis for most replicated NMOS, showing saturation current
values for the sixteen replicates per row in a specific chip. N=1.
7.3
Summary
In this chapter we presented spatial trends across a wafer and across the FEOL rows
of our test chip. The chip-to-chip spatial variation for aggregated NMOS structures shows
a trend of increasing current diagonally, from the center of the wafer (which is the bottom
edge of our sample) to the top right corner of the wafer. The spatial analysis of VT for
NMOS transistors of minimum gate length also shows a similar trend, confirming that on
134
this particular wafer the slowest transistors tend to be towards the center. Within-chip
analysis shows a subtle trend of extreme currents towards the edges of rows, but the lack
of a strong trend helps to verify that the feedback network to prevent power losses works
well. This chapter concludes the analysis of our test structure methodology and devices
under test; Chapter 8 discusses how the architecture can be re-implemented or enhanced
for use in other technologies.
135
136
. ...
......
Chapter 8
Suggestions for Future Implementations
Our test chip methodology is efficient for use in measuring and characterizing
transistors and interconnects, and future work can explore this methodology further. The
test chip architecture can be more easily migrated to other technologies because of its
hierarchical approach. In this chapter we offer some suggestions on how the design can
be migrated and improved in future implementations, and for future technology
generations.
8.1
Gate Leakage in Newer Technologies
The 0.18 gm technology used for our test chip does not have the problem of high gate
leakage currents. More modem technologies that suffer from this problem will also need
a Kelvin sensing connection in the gate voltage terminal, as illustrated in Figure 8-1. This
will ensure that the voltage at the gate nodes of the switches and DUTs is the intended
one, and that it has not been decreased due to losses in the line. In addition, means for
measurement of gate currents may be desirable, when these become appreciable in some
bias conditions.
VDD
-
VGATE
Figure 8-1: Feedback implementation for technologies with high gate leakage currents.
137
8.2
Design of the On-Chip Feedback
The failure of the on-chip feedback jeopardizes the reliability of all the measurements
in the test chip, and it must be carefully designed. The sizing of the analog opamp will
likely need to change for other technologies to guarantee proper feedback. Because of
this, it is not recommended to build the on-chip feedback in a very young technology
where basic parameters are unknown. Some preliminary characterization must be done
before designing the on chip feedback in a given technology, so that it can be designed
with phase margin, step response and gain that fulfill the specifications to ensure that the
feedback will work.
In a young technology that is not yet robust enough for on-chip feedback, the
feedback can be implemented off-chip. On-chip feedback is, however, preferred to off
chip as Kelvin sensing works best when the feedback is as close to the DUTs as possible,
and it allows rapid measurements without additional setup.
The present design has some trouble providing low enough drain voltages to our
DUTs. We believe that the output stage of the operational amplifier can be eliminated.
The output stage used in this design, a source follower, has a complicated active bias that
can threaten the full output swing of the opamp, as seen in Figure 2-10. The revised
opamp needs to have a large enough common source gain stage to provide the currents
needed for all the DUTs. The resistive load is not an issue here as the opamp is
connected, by feedback, to its input stage, which is a very high resistance node.
8.3
Design Review of FEOL Low Leakage Switches
In the present design, we have only a single designed version of our FEOL switches.
In future designs, it may be best to have two: one for PMOS and one for NMOS DUTs.
138
We turn the NMOS DUTs off in two ways, by having the source and drain at the same
potential and by grounding its gate voltage, as shown in Figure 8-2. The PMOS off tiles,
however, are only turned off by making their source voltage equivalent to their drain
voltage. The PMOS tile can also be double turned off if the gate voltage were to be set to
VDD
in the off state, as shown in the revised tile in Figure 8-2.
/en
VGATE
en
/en
VDD
en
en
VGATE
/en
en
VREF
FEOL NMOS Tile
/en
VREF
FEOL PMOS Tile
Figure 8-2: Revised NMOS and PMOS FEOL tiles.
The problem of not turning a tile off both ways is highlighted in Figure 8-3. If PMOS
tiles have their gate voltages connected to ground and there is an offset between the
source and the drain voltage of the off PMOS transistors at low values of Vref, the
transistor will conduct current. That current will go to the output of the opamp as
illustrated in Figure 8-3. This additional current can create an offset in the output of the
opamp, hence failing to provide the accurate current. This can be easily fixed by having a
separate gate voltage input line for the PMOS transistors, that will be kept at a high
voltage instead of ground for the off tiles as shown in Figure 8-2.
139
Vref
Il
-+
len
en
/en
VREF
Figure 8-3: Problem with FEOL switches.
8.4
Off Tiles Leakage Currents
The leakage current of the off tiles can affect the functionality of the test chip,
because these currents add to the measurement of the currents of the desired DUT. In our
case, these currents only affect the lower end of the weak inversion region, and we are
able to gather the data we desire with the rest of the inversion region. However, new
technologies may have higher "off' currents, or the designer may want lower "off'
currents so that the weak inversion region can be more widely studied.
One way to reduce the amount of leakage is by shortening the length of the test row.
In our technology, each off tile has approximately 3 pA of leakage current (in
simulation). This adds up to about 2 nA of leakage current for the 720 tiles when off at
the same time. If we had only use a "subrow" which includes 90 tiles, for example, the
leakage would be only 0.25 pA.
Another way to reduce leakage is by increasing the size of the switch transistor, but in
simulation we find that a 100% increase in the size of the switch (both width and length)
will reduce the leakage by only 7%.
140
8.5
Summary
Much has been learned from the design of this test chip, and in this chapter we
provide several suggestions for its future implementation. We address the issue of gate
leakage currents in more aggressive technologies, and we suggest adding a Kelvin
sensing connection at the gate voltage terminal. We also address the issue of the redesign
of the feedback opamp, which is likely the architecture component that will need the
most change when migrated to other technologies. The low leakage switches were
discussed and suggestions are given for improving their utilization and to minimize offstate leakage. Now that all aspects of our methodology have been discussed, we proceed
to discuss and summarize the thesis contributions in Chapter 9.
141
142
Chapter 9
Conclusions
This thesis focuses on the design, implementation, testing and analysis of a test chip
that can extract analog measurements without directly probing a test structure, while
multiplexing both the input and output signals of a large array of devices under test. It
provides a methodology that emphasizes hierarchy so the architecture can be easily
transported from one technology to another. In this last chapter we will summarize the
contributions of the thesis, including a summary of the findings, and present suggestions
for future work.
9.1
Thesis Contributions
We have successfully designed, implemented and demonstrated a test chip that can
gather analog (I-V) characteristics by multiplexing the use of pads. It enables tracking of
trends and variations in transistor and interconnect structures, with results that show
dependencies to common layout practices and process variation.
We can summarize the contributions of the thesis in two areas: the design of the test
chip and the analysis of the measurements taken.
9.1.] Test Chip Design and Implementation
We presented the design of a test chip that can gather a large amount of analog
characteristics in a much more limited area than traditional methods of testing. In it we
tested a total of 2128 test structures per chip (FEOL and BEOL), as opposed to
approximately 140 test structures that can be measured using traditional methods of
testing in the same area (in a 3 x 2.33 mm area, with 50 pm pads and using five pads for
two transistors, sharing one terminal with other devices).
143
The test chip is mainly composed of three blocks: the tile, row, and chip blocks. This
methodology is powerful because its hierarchy allows the user to make hierarchical
changes when migrating it to a new technology, and to modify the test chip (number of
test structures, area, etc.) at the user's convenience.
There are two different types of tiles, the front end of line (FEOL) tile and the back
end of line (BEOL) tile. The FEOL tile includes a device under test (DUT) that is
connected to two simple, novel low leakage pass gate switches, one in its gate and one in
the drain terminal, ensuring the on and off states of the DUTs within an entire row. The
tile also includes control circuitry (scan chain) to open and close the switches. The BEOL
tile includes a CBCM structure connected to a metal capacitor; the tile input signals turn
each of the four transistors in the tile on and off through low leakage switches. The
BEOL tile also has a low leakage switch to connect its output current to the output line.
Each row, a group of tiles, includes a carefully designed on-chip Kelvin sensing
feedback circuit to guarantee the drain voltage that each DUT receives, which is critical
to gather the desired VDS curves without probing each DUT directly. The feedback
system is composed of an operational amplifier built in 3.3 V devices that can provide the
output voltage and current needed to submit the front end of line DUTs to drain and gate
voltage sweeps. It can also provide a steady voltage for a CBCM structure. The chip was
fabricated using a 0.18 gm CMOS logic technology.
9.1.2 Testing Results andAnalysis of the Test Structures
All test structures were successfully measured and tested. Layout dependent test
structures show clear dependencies due to the layout practice used to implement them.
Unlike previous work [1], we are able to more clearly identify where the source of
144
variation is, because we measure only one device or interconnect structure at a time, and
because we can gather I-V curves from which parameters such as threshold voltage can
be extracted.
Structures with different orientation present an offset that is consistent between chips
and between most structures laid out next to each other. Interestingly, NMOS and PMOS
are affected inversely with orientation, probably because they are also affected inversely
by residual strain due to shallow trench isolation (STI). Structures with different spacing
between fingers show a mean shift consistent with a lithographic effect. Structures with
different number of fingers and equivalent gate length increase their variability as the
number of fingers increases and the size of each finger decreases.
We are also able to study an array of transistors of different sizes to characterize their
behavior and susceptibility to variation. We are able to show that variation changes
according to transistor sizing, following Pelgrom's model [35], [41], and that variation in
sub-threshold is much larger than when a transistor is on, particularly in transistors with
smaller gate lengths. We extract threshold voltage from the voltage sweep current curves,
and its variation also follows the Pelgrom model.
Interconnect capacitances are measured, with values that match closely the values
extracted from a parasitic extractor for two types of test structures (focusing on coupling
and plane to plane capacitances). For the third type of structure, we are able to determine
that the extractor overestimated the parasitic capacitance value, highlighting the need of
having on-chip measurements to ensure proper calculation of parameters.
Spatial analysis is able to highlight wafer-wide trends for FEOL structures. Within
chip trends are not dominant, adding assurance that the voltage feedback did its work in
145
assuring a constant power voltage for all test structures within a row.
9.2
Future Work
The successful testing and implementation of the test chip opens doors to use it for
different analyses in future work. The methodology can be transported to a different
technology by following the guidelines presented in Chapter 8. Below we suggest a few
ideas on future work using this methodology.
9.2.1 On-chip Measurements
If chip area is available, it would be interesting to use the test chip methodology
presented in this thesis together with on-chip current measurements, such as in [11] and
[20]. This will simplify testing and can simplify the design of on-chip feedback for the
ground line.
9.2.2 Study of Sub-threshold Variation
It was found in our analysis that variation in the sub-threshold regime is of great
impact. It was, however, difficult to examine at the low end of the weak inversion region
because of the leakage of the off tiles. It would be interesting to repeat the experiment
with lower leakage currents, using the methods suggested in Section 8.4 or others, so that
variation in this area can be studied for lower gate voltages.
9.2.3 Charge Based CapacitanceMeasurementStructures
The "blank" charge based capacitance structures (without any connected capacitor
test loads) were found to exhibit non-zero capacitance measurements. As discussed in
Section 6.1, these capacitance offsets were subtracted from all other CBCM test
structures, which removes most of the chip to chip spatial trends in these structures.
Future work should consider extensions to the CBCM approach to correct for these
146
offsets, preferably on an individual structure by structure basis.
9.2.4 Coupling CapacitancesStructures
We were unable to decouple with our test structures the impact on variation due to
metal thickness and spacing in coupling capacitances. Future work may consider an
experiment with a larger array of different distances between the spacing or the width of
the metal.
9.2.5 Directly Probed Transistors
It would be useful to have some transistors directly connected to pads within our test
chip, to prove the functionality of the test rows. Analog characteristics of these directly
probed transistors can be compared to those of individual transistors within the scan
chain, to estimate the efficiency and accuracy of the measurements of the transistors
using the test chip architecture.
We attempted to implement such directly probed transistors in our test chip, but they
appear to have been damaged during the fabrication, packaging, or testing process, and
we were unable to gather meaningful transistor current curves from them. We did not
protect the pads or terminals with ESD structures, and it is possible that electrostatic
discharge resulted in destructive breakdown of the gate dielectric or other damage to
these devices. In particular, we observe that these devices do not turn off (the source
current remains large even at low gate voltages), and large currents (in the gA range) are
measured in the gate terminal. Additional caution must be used when laying out these
directly probed transistors, so they have adequate protection to avoid damage during
fabrication, packaging or testing.
147
9.3
Summary of Contributions
This thesis has focused on the design, successful testing and analysis of a test chip
capable of gathering analog measurements with a limited number of pads and input
signals. Its implementation is more area effective than traditional methods of directly
probing individual transistors. The large amount of data allows us to characterize the
devices under test, both transistors and interconnects. Ideas have also been given for
future implementations of the test chip.
148
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152
Appendix I
Test Structures Nomenclature and Row Location
FEOL Cells
There are 90 different FEOL cells. These are the FEOL included in the design:
SIN
(N type structures of
different sizes. All gate
lengths are 0.18u, and
the widths are from
0.50-3u in 0.25u
increments)
S2N
(N type structures of
different sizes. All gate
lengths are 0.36u, and
the widths are from
0.50-3u in 0.25u
increments)
S3N
(N type structures of
different sizes. All gate
lengths are 0.54u, and
the widths are from
0.50-3u in 0.25u
increments)
tilelp18wp50
tilelpI8wp75
tilelpl8wIpO
tilelp18w1p 2 5
tilelpl8wlp50
tilelpl8wlp75
tilelpi 8w2p0
tilelpI8w2p25
tilelp I 8w2p50
tilelp 1 8w2p75
tilelp 1 8w3p0
tilelp36wp5O
tilelp36wp75
tilelp36wlpO
tilelp36wlp25
tilelp36wlp5O
tilelp36wlp75
tilelp36w2pO
tilelp36w2p25
tilelp36w2p5O
tilelp36w2p75
tilelp36w3pO
tilelp54wp5O
tilelp54wp75
tilelp54wlpO
tilelp54wlp25
tilelp54wlp5O
tilelp54wlp75
tilelp54w2pO
tilelp54w2p25
tilelp54w2p5O
tilelp54w2p75
tilelp54w3pO
153
I tilePlpl8wp5O
SIP
(P type structures of
different sizes. All gate
lengths are 0.18u, and
the widths are from
0.50-3u in 0.25u
increments)
S2P
(P type structures of
different sizes. All gate
lengths are 0.36u, and
the widths are from
0.50-3u in 0.25u
increments)
S3P
(P type structures of
different sizes. All gate
lengths are 0.54u, and
the widths are from
0.50-3u in 0.25u
increments)
tilePlp 18wp75
tilePlp18wlpO
tilePIp18wlp25
tilePlp 18w lp50
tilePIp18wlp75
tilePlp 1 8w2p0
tilePlp 1 8w2p25
tilePlp 1 8w2p50
tilePlp 1 8w2p75
tilePlp 1 8w3p0
tilePlp36wp5O
tilePlp36wp75
tilePlp36wipO
tilePlp36wlp25
tilePlp36wlp5O
tilePlp36wlp75
tilePlp36w2pO
tilePlp36w2p25
tilePlp36w2p5O
tilePlp36w2p75
tilePlp36w3pO
tilePlp54wp50
tilePlp54wp75
tilePlp54wipO
tilePlp54wlp25
tilePlp54wlp5O
tilePlp54wlp75
tilePlp54w2pO
tilePlp54w2p25
tilePlp54w2p5O
tilePlp54w2p75
tilePlp54w3pO
154
OR
NMOS and PMOS
oriented vertically and
horizontally. All are
1/.18u
PS
Three finger structures
with different spacing
between the fingers
(minimum, 1.2x
minimum, 1.5x
minimum, 3x minimum)
, NMOS and PMOS. All
are 0.5u/. 18u per finger
PF
Structures with
equivalent gate length
but different number of
fingers. All w=0.5u.
Lengths are 3x
minimum (1 finger, 2
finger and 3 finger), and
4x (1 finger, 2 fingers
and 4 fingers) NMOS
and PMOS
tileNV
tileNH
tilePV
tilePH
tileNS Ix
tileNSlp2x
tileNSlp5x
tileNS3x
tilePSIx
tilePSIp2x
tilePS 1 p5x
tilePS3x
tileND3xif
tileND3x2f
tileND3x3f
tilePD3xlf
tilePD3x2f
tilePD3x3f
tileND4xlf
tileND4x2f
tileND4x4f
tilePD4xif
tilePD4xIf
tilePD4x2f
tilePD4x4f
155
BEOL Cells
There are 23 unique BEOL test structures, which are:
Combs
Comb structures with minimum width
and minimum space,
I.2x minimum width and minimum
space, and minimum width and 1.2x
minimum space, in MI, M2, M3, M4,
M5
Grids
A combination of Combs and Planes,
these are a horizontal metal layer under
a vertical metal layer of higher order, all
at minimum width and spacing
Planes
A large plane of metal-x over another
one of metal x-1. The x- 1 plane is larger
in case they misalign during the mask
process
CbcmTileCombM1
CbcmTileCombMlS
CbcmTileCombMlW
CbcmTileCombM2
CbcmTileCombM2S
CbcmTileCombM2W
CbcmTileCombM3
CbcmTileCombM3S
CbcmTileCombM3W
CbcmTileCombM4
CbcmTileCombM4S
CbcmTileCombM4W
CbcmTileCombM5
CbcmTileCombM5S
CbcmTileCombM5W
CbcmTileGridM2M1
CbcmTileGridM3M2
CbcmTileGridM4M3
CbcmTileGridM5M4
CbcmTilePlaneM2M1
CbcmTilePlaneM3M2
CbcmTilePlaneM4M3
CbcmTilePlaneM5M4
Rows
The FEOL and BEOL rows are composed of the tiles described above. There are two
FEOL rows in the chip. There are 728 FEOL tiles in a row, including eight blank tiles to
prove the functionality of the scan chain. The row is subdivided in eight sub-rows. Each
sub-row contains one of each of the unique FEOL structures. All FEOL structures are
repeated eight times per row (the three finger, minimum spacing is repeated 16 times, as
"tileNS Ix" and "tileND3x If'). The order in which the tiles are placed per sub-row varies,
for a broader spatial analysis. This is the order of the FEOL sub-rows.
156
ROWA
ROWB
ROWC
ROWD
ROWE
ROWF
ROWG
ROWH
lp18wp50
Plp18wp5O
NV
NS1x
lpl8wp50
Plp18wp5O
NV
NS1x
lp18wp75
Plp18wp75
NH
NSlp2x
lpl8wp75
Plpl8wp75
NH
NSlp2x
lp18wlp0
Plp18wlp0
PV
NSlp5x
lp18wlp0
Plp18wlp0
PV
NSlp5x
p18w1p25
Plpl8wlp25
PH
NS3x
lp18w1p25
Plpl8wlp25
PH
NS3x
lpl8wlp50
Plpl8wlp5O
NS1x
PSix
lp18wlp5O
Plpl8wlp5O
NS1x
PSix
lpI8wlp75
Plpl8wlp75
NSlp2x
PSIp2x
lp18w1p75
Plp18wlp75
NSlp2x
PSlp2x
lpl8w2pO
Plpl8w2pO
NSlp5x
PSlp5x
lpI8w2pO
Plpl8w2p0
NS1p5x
PSlp5x
lp18w2p25
lp18w2p50
lp18w2p75
Plp18w2p25
NS3x
PS3x
NS3x
PS3x
PSIx
ND3xlf
Plpl8w2p50
PSIx
ND3xlf
Plpl8w2p75
PS p2x
ND3x2f
lp18w2p25
lp18w2p50
lp18w2p75
Plpl8w2p25
Plpl8w2p50
Plp18w2p75
PS p2x
ND3x2f
lpI8w3pO
Plpl8w3pO
PSlp5x
ND3x3f
lpl8w3pO
Plpl8w3p0
PSlp5x
ND3x3f
lp36wp50
Plp36wp5O
PS3x
PD3xlf
lp36wp5O
Plp36wp50
PS3x
PD3xlf
lp36wp75
Plp36wp75
Blank
PD3x2f
Ip36wp75
Plp36wp75
Blank
PD3x2f
lp36wlpO
lp36w1p25
1p36w1p50
Plp36wlpO
ND3xlf
PD3x3f
lp36wlpO
Plp36wlpO
ND3xlf
PD3x3f
Plp36w1p25
ND3x2f
ND4xlf
Plp36w1p25
ND3x2f
ND4xlf
Plp36wlp50
ND3x3f
ND4x2f
Plp36wlp5O
ND3x3f
ND4x2f
1p36w1p75
Plp36wlp75
PD3xlf
ND4x4f
1p36w1p25
lp36w1p50
1p36w1p75
Plp36w1p75
PD3xlf
ND4x4f
lp36w2p0
1p36w2p25
lp36w2p50
lp36w2p75
lp36w3p0
lp54wp50
lp54wp75
Plp36w2pO
PD3x2f
PD4xlf
1p36w2p0
Plp36w2pO
PD3x2f
PD4xlf
PIp36w2p25
PD3x3f
PD4x2f
lp36w2p25
Plp36w2p25
PD3x3f
PD4x2f
Plp36w2p50
ND4xlf
PD4x4f
Plp36w2p50
ND4xlf
PD4x4f
Plp36w2p75
ND4x2f
lpl8wp50
lp36w2p50
1p36w2p75
Plp36w2p75
ND4x2f
Plp36w3pO
ND4x4f
lpl8wp75
Ip36w3p0
Plp36w3pO
ND4x4f
lpl8wp50
lpl8wp75
Plp54wp5O
PD4xlf
lp18wlp0
lp54wp5O
Plp54wp5O
PD4xlf
lpl8wlpO
Plp54wp75
PD4x2f
lpl8wlp25
1p54wp75
Plp54wp75
PD4x2f
lp54wlpO
Plp54wlpO
PD4x4f
lpl8wlp50
lp54wlpO
Plp54wlpO
PD4x4f
lp54w1p25
lp54w1p50
lp54wlp75
lp54w2p0
lp54w2p25
lp54w2p50
lp54w2p75
lp54w3p0
Plp54w1p25
lpl8wp50
lpl8wlp75
1p54w1p25
PIp54w1p25
lp18wp50
1p18w1p25
Ipl8wlp50
lp18w1p75
Plp54wlp5O
lpl8wp75
lpI8w2pO
lpl8wp75
lpI8w2pO
lpl8wlpO
Plp54w1p75
lpl8wlpO
lp18w2p25
Plp54w2pO
1p18w1p25
lp54w2p0
Plp54w2pO
lp18w1p25
lpl8w2p5O
Plp54w2p25
lpl8wlp5O
lp18w2p25
1p18w2p50
lp18w2p75
lp54w1p50
1p54w1p75
Plp54wlp5O
Plp54w1p75
PIp54w2p25
lpl8wlp5O
lp18w2p75
Plp54w2p50
lp18w1p75
Ip18w3p0
Plp54w2p50
1p18w1p75
lpl8w3p0
Plp54w2p75
lpl8w2pO
lp36wp5O
Plp54w2p75
lpl8w2pO
lp36wp5O
Plp54w3p0
lp36wp75
lp54w2p25
lp54w2p50
1p54w2p75
1p54w3p0
Plp54w3pO
lp36wp75
lp36wlpO
Plpl8wp50
Blank
Plpl8wp75
NV
1p18w2p25
lp18w2p50
lp18w2p75
Plpl8wlpO
NH
lpl8w3pO
Blank
NV
lp18w2p25
lp18w2p50
Plpl8wp50
NH
1p18w2p75
Plpl8wp75
PV
lpl8w3pO
Plp18wlpO
PH
lp36wp5O
lp36w1p25
lp36w1p50
lp36wlp75
Plp18wlp25
PV
lp36wp5O
lp36wlpO
lp36w1p25
lp36w1p50
lp36w1p75
Plpl8wlp25
NS1x
lp36wp75
lp36w2pO
Plpl8wlp50
PH
lp36wp75
lp36w2pO
PIpl8wlp50
NSlp2x
lp36wlpO
lp36w2p25
Plpl8wlp75
NS1x
lp36wlp0
Plpl8wlp75
NSlp5x
1p36w1p25
1p36w2p50
PlpI8w2pO
NSlp2x
1p36wlp25
Plpl8w2pO
NS3x
lp36wlp5O
lp36w2p75
Plp18w2p25
NSlp5x
lp36wlp5O
lp36w2p25
lp36w2p50
1p36w2p75
Plpl8w2p25
PSIx
lp36w1p75
1p36w3p0
Plpl8w2p50
NS3x
lp36w1p75
lp36w3p0
Plpl8w2p5O
PSlp2x
lp36w2pO
lp54wp5O
Plp18w2p75
PSlx
1p36w2p0
lp54wp50
PIp18w2p75
PSlp5x
lp36w2p25
lp54wp75
PlpI8w3pO
PSlp2x
lp36w2p25
lp54wp75
Plpl8w3pO
PS3x
lp36w2p50
lp54wlpO
Plp36wp5O
PSlp5x
lp36w2p50
lp54wlpO
Plp36wp50
ND3xlf
lp36w2p75
lp54w1p25
Plp36wp75
PS3x
lp36w2p75
lp54w1p25
Plp36wp75
ND3x2f
lp36w3pO
lp54wlp5O
Plp36w0pO
ND3xlf
lp36w3p0
lp54wlp5O
157
Plp36wlpO
ND3x3f
1p54wp50
lp54wlp75
Plp36wlp25
ND3x2f
lp54wV5O
1p54wlp75
Plp36wlp25
PD3xlf
1p54wp75
1p)54w2p0
PIp36wlp5O
ND3x3f
Ip54wp75
1p54w2P0
Plp36wlp5O
PD3x2f
lp54wlpO
1p54w2p25
Plp36wlp75
PD3xlf
lp54wlpO
1p54w2p25
Plp36wlp75
PD3x3f
1p54wlp25
lp54w2p50
Plp36w2pO
PD3x2f
lp54wlp25
1p54w2p50
Plp36w2pO
ND4xlf
1p54wlp50
1p54w2p75
Plp36w2p25
PD3x3f
1p54wlp50
1p54w2p75
Plp36w2p25
ND4x2f
1p54wlp75
1p54w3p0
Plp36w2p50
ND4xlf
lp54wlp75
l1p54w3p0
Plp36w2p50
ND4x4f
1p54w2p0
Plpl18wp50
Plp36w2p75
ND4x2f
Ip54w2 0
Blank
Plp36w2p75
PD4xlf
1p54w2p25
Plpl8wp75
Plp36w3pO
ND4x4f
lp54w2p25
Plpl8wp5O
Plp36w3pO
PD4x2f
1p54w2p50
Plpl8wlpO
Plp54wp5O
PD4xlf
lp54w2p50
Ppw75
Plp54wp5O
PD4x4f
1p54w2p75
Plpl8wlp25
Plp54wp75
PD4x2f
1p54w2p75
Plpl8wlpO
Plp54wp75
Blank
1p54w3p0
Plpl8wlp5O
Plp54wlpO
PD4x4f
1p54w3p0
Plpl8wlp25
Plp54wlpO
lpl8wp5O
Plpl8wp5O
PIpl8wlp75
Plp54wlp25
lpl8wp5O
Plpl8wp50
Plpl8wlp5O
Plp54wlp25
lpl8wp75
Plpl8wp75
PlplI8w2pO
Plp54wlp5O
lpl8wip75
PlplI8wp7 5
Plpl8wlp75
PIp54wlp5O
lpl8wlpO
Plpl8wlp0
Plp)18w2p25
Plp54wlp75
lpl8wlpO
PIpl8wlpo
Plpl8w2pO
Plp54wlp75
1pl8wlp25
Plpl8wlp25
PlplI8w2p5O
Plp54w2pO
1pt8wlp25
Plpl8wlp25
Plpl8w2p25
Plp54w2pO
lP18wlp5O
Plpl8wlp5O
Plpl8w2p75
Plp54w2p25
lpl8wlp50
Plpl8wlp5O
Plpl8w2p5O
Plp54w2p25
lp18wlp75
Plpl8wlp75
Plpl8w3pO
Plp54w2p50
1p18wlp75
Plpl8wlp75
PIp18w2p75
Plp54w2p50
lpl8w2pO
Plpl8w2pO
Pltp36wp5O
Pl5wp5
lplI8w2pO
Plpl18 2pO
Plpl8w3pO
Plp54w2p75
1p)18w2p25
Plp 18w2p25
Plp36wp75
Plp)54w3pO
I18w2p)25
Ppwp25
Plp36wp5O
Plp54w3pO
1p18w2p50
Plpl8w2p5O
Plp36wlpO
NV
1p1I8w2p50
Plpl8w2p5O
Pl3w75
NV
1p 18w2p75
Plp18w2p75
Plp36wlp25
NH
1p18w2p75
Plpl8w2p75
Plp36wlpO
NH
lpl~w3pO
Plpl8w3pO
Plp36wlp5O
PV
lpl8w3pO
PlplI8w3pO
Plp36wlp25
PV
1p36wp50
Plp36wp)5O
Plp36wlp75
PH
lp36wp50
Plp36wp5O
P1 36wp 50
PH
lp36wp75
Plp36wp75
Plp36w2pO
Blank
lp36wp75
PIV36wp75
Plp36wlp75
NSlx
lp36wlpO
Plp36wlpO
Pp6p25
NSlx
lp36wlpO
Plp36wlpO
Plp36w pO
NSlp2x
1p36wlp25
Plp36wIp25
Plp)36w2p50
NSlp2x
lp36wlp25
Plp36wlp25
Plp36w2p25
NS lp~x
1p36wlp50
Plp36wlp50
Plp)36w2p75
NSlp5x
1p36wlp50
Plp36w ip5O
Plp36w2p50
NS3x
1p36wlp75
Plp36wlp75
Plp36w3pO
NS3x
1p36wlp75
Plp36wl7
P~3
PSix
1p36w2p0
Plp36w2pO
Plp54wp5O
PSix
1p36w2p0
Plp36w2pO
Plp36w3pO
PSlp2x
1p36w2p25
Plp36w2p25
P~5w75
PS lp2x
1p36w2p25
Plp36w p25
Plp54wp5O
PSlp5x
1p36w2p50
Plp36w2p50
Plip54wlpO
PSlp5x
1p36w2p50
Plp36w2p50
Plp)54wp75
PS3x
lp36w2p75
Plp36w2p75
Plp54wlp25
PS3x
1p36w2p75
Plp36w2p75
Plp54wlpO
ND3xlf
lp36w3p0
Plp36w3pO
PIp54wlp5O
ND3xlf
1p36w3p0
Plp36w pO
Plp)54wlp25
ND3x2f
lp54wp5O
PIP54wP5O
Plp54wlp75
ND3x2f
15pPlp54wp5O
Plp54wlp5O
ND3x3f
lp54wp75
Plp54wp75
Plp54w2pO
ND3x3f
lp54wp75
Plp54wp75
Plp54wlp75
PD3xlf
lp54wlpO
Plp54wlpO
Plp)54w2p25
PD3xlf
lp54wlpO
Plp54wlpO
Plp54w2pO
PD3x2f
lp54wlp25
Plp)54wlip25
Plp)54w2p50
PD3x2f
1p54wlp25
Plp54wlp25
Plp54w2p25
PD3x3f
1p54wlp50
Plp54wlp5O
Plp54w2p75
PD3x3f
1p54wlp50
Plp54wl5
PIp54w2p50
ND4xlf
1p54wlp75_
Plp54wlp75
Plp54w3pO
ND4xlf
1p54wlp75
Plp54wlp75
Plp54w2p75
ND4x2f
1p54w2p0
Plp54w2pO
Blank
ND4x2f
1p54w2p0
Plp54w2pO
Plp54w3pO
ND4x4f
1p54w2p25
Plp54w2p25
NV
ND4x4f
1p54w2p25
Plp54w2p25
NV
PI)4xlf
1p54w2p50
Plp54w p50
NH
PD4xlf
lp54w2p50
Plp54w2p50
NI-I
PD4x2f
lp54w2p75
Plp)54w2p75
PV
PD4x2f
1p54w2p75
Plp54w2p75
PV
PD4x4f
1p54w3p0
Plp54w3pO
PH
PD4x4f
1p54w3p0
Plp54w3pO
PH
p75
158
There are 2 BEOL rows on the chip, with 8-subrows, like in the FEOL case. These
sub-rows have 42 tiles each. This is the order of the BEOL sub-rows:
ROWA
ROWB
ROWC
ROWD
ROWE
ROWF
ROWG
ROWH
CombMl
GridM2Ml
PlaneM2Ml
CombMl
GridM2M1
PlaneM2M1
CombMl
GridM2Ml
CombMlS
GridM3M2
PlaneM3M2
CombMlS
GridM3M2
PlaneM3M2
CombMlS
GridM3M2
CombMlW
GridM4M3
PlaneM4M3
CombMlW
GridM4M3
PlaneM4M3
CombMlW
GridM4M3
CombM2
GridM5M4
PlaneM5M4
CombM2
GridM5M4
PlaneM5M4
CombM2
GridM5M4
CombM2S
PlaneM2Ml
CombMl
CombM2S
PlaneM2Ml
CombMl
CombM2S
PlaneM2ML
CombM2W
PlaneM3M2
CombMlS
CombM2W
PlaneM3M2
CombMlS
CombM2W
PlaneM3M2
CombM3
PlaneM4M3
CombM2
CombM3
PlaneM4M3
CombM2
CombM3
PlaneM4M3
CombM3S
PlaneM5M4
CombM2S
CombM3S
PlaneM5M4
CombM2S
CombM3S
PlaneM5M4
CombM3W
CombM1
CombM3
CombM3W
CombMl
CombM3
CombM3W
CombMl
CombM4
CombMlS
CombM3S
CombM4
CombMlS
CombM3S
CombM4
CombMlS
CombM4S
CombM2
CombM4
CombM4S
CombM2
CombM4
CombM4S
CombM2
CombM4W
CombM2S
CombM4S
CombM4W
CombM2S
CombM4S
CombM4W
CombM2S
CombM5
CombM3
CombM5
CombM5
CombM3
CombM5
CombM5
CombM3
CombM5S
CombM3S
CombM5S
CombM5S
CombM3S
CombM5S
CombM5S
CombM3S
CombM5W
CombM4
GridM2Ml
CombM5W
CombM4
GridM2Ml
CombM5W
CombM4
GridM2Ml
CombM4S
GridM3M2
GridM2Ml
CombM4S
GridM3M2
GridM2Ml
CombM4S
GridM3M2
CombM5
GridM4M3
GridM3M2
CombM5
GridM4M3
GridM3M2
CombM5
GridM4M3
CombM5S
GridM5M4
GridM4M3
CombM5S
GridM5M4
GridM4M3
CombM5S
GridM5M4
GridM2Ml
Blank
GridM5M4
GridM2Ml
Blank
GridM5M4
GridM2Ml
PlaneM2Ml
GridM3M2
PlaneM2Ml
PlaneM2Ml
GridM3M2
PlaneM2M1
PlaneM2Ml
GridM3M2
PlaneM3M2
GridM4M3
PlaneM3M2
PlaneM3M2
GridM4M3
PlaneM3M2
PlaneM3M2
GridM4M3
PlaneM4M3
GridM5M4
PlaneM4M3
PlaneM4M3
GridM5M4
PlaneM4M3
PlaneM4M3
GridM5M4
PlaneM5M4
Blank
PlaneM5M4
PlaneM5M4
Blank
PlaneM5M4
PlaneM5M4
Blank
Blank
PlaneM2Ml
CombMl
Blank
PlaneM2MI
CombMl
Blank
PlaneM2M1
CombMl
PlaneM3M2
CombMlS
CombMl
PlaneM3M2
CombMlS
CombMl
PlaneM3M2
CombMlS
PlaneM4M3
CombMlW
CombMlS
PlaneM4M3
CombM1W
CombMlS
PlaneM4M3
CombM2
PlaneM5M4
CombM2
CombM2
PlaneM5M4
CombM2
CombM2
PlaneM5M4
CombM2S
CombMl
CombM2S
CombM2S
CombMl
CombM2S
CombM2S
CombMl
CombM3
CombMlS
CombM2W
CombM3
CombMlS
CombM2W
CombM3
CombMlS
CombM3S
CombMlW
CombM3
ConbM3S
CombMlW
CombM3
CombM3S
CombM1W
CombM4
CombM2
CombM3S
CombM4
CombM2
CombM3S
CombM4
CombM2
CombM4S
CombM2S
CombM3W
CombM4S
CombM2S
CombM3W
CombM4S
CombM2S
CombM5
CombM2W
CombM4
CombM5
CombM2W
CombM4
CombM5
CombM2W
CombM5S
CombM3
CombM4S
CombM5S
CombM3
CombM4S
CombM5S
CombM3
GridM2Ml
CombM3S
CombM4W
GridM2Ml
CombM3S
CombM4W
GridM2Ml
CombM3S
GridM3M2
CombM3W
CombM5
GridM3M2
CombM3W
CombM5
GridM3M2
CombM3W
GridM4M3
CombM4
CombM5S
GridM4M3
CombM4
CombM5S
GridM4M3
CombM4
GiridM5M4
CombM4S
CombM5W
GridM5M4
CombM4S
CombM5W
GridM5M4
CombM4S
PlaneM2M1
CombM4W
GridM2Ml
PlaneM2Ml
CombM4W
GridM2Ml
PlaneM2M1
CombM4W
PlaneM3M2
CombM5
GridM3M2
PlaneM3M2
CombM5
GridM3M2
PlaneM3M2
CombM5
PlaneM4M3
CombM5S
GridM4M3
PlaneM4M3
CombM5S
GridM4M3
PlaneM4M3
CombM5S
PlaneM5M4
CombM5W
GridM5M4
PlaneM5M4
CombM5W
GridM5M4
PlaneM5M4
CombM5W
159
160
Appendix II
Calculation for Crossover Capacitance
Parameters:
h2=8e-7
wl=0.23e-6
w2=0.28e-6
si=0.23e-6
s2=0.28e-6
t0=5300e-10
EOX =3.85e-1 1
Equations (from Wong et al. [42]:
c2/Eox=
3.73*w2 0 .6*(s 1 *s2)
02
*(tl/(tl+(0.035*h2)))1- 64*(tI/(t1 +(0.85 1*S1 ))) 0 12*exp(-h2/(0.7*(s 1+.4*h2)))
c I/ cox =w l*w2/h2
Results:
cl = 3.0993e-018
c2 = 4.5094e-018
(cl+c2)*25*76= 1.4457e-014
161
162
Appendix III
Layout Screen Shots
These are some of the structures included in the test chip:
FEOL:
PMOS transistors in different sizes
NMOS transistors in different sizes
163
Transistors with different number of poly
fingers and different spacing between poly fingers
PMOS and NMOS transistors with different orientation
164
BEOL:
Metal 1 Comb Structures, Different Spacing and Different Widths
165
-9100"OW-- ---owd
Metal 2 Comb Structure in Tile
166
Grid Structure (M2-M1)
167
Plane Structure (M2-M1)
168
Rows:
FEOL Row
BEOL Row
169