Deeply-Scaled GaN High Electron Mobility Transistors
for RF Applications
AROMV ES
by
MASSACHUSETTS INS117T E
OFTECHNOLOGY
Dong Seup Lee
B.S., Electrical Engineering
Seoul National University, 2007
S.M., Electrical Engineering and Computer Science
Seoul National University, 2009
APR 10 2014
H-S
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degree of
Doctor of Philosophy
at the
Massachusetts Institute of Technology
February, 2014
C 2014 Massachusetts Institute of Technology. All Rights Reserved.
Author
Department of Electrical Engineerj
and Computocience
January 21, 2014
Certified by
T
s Palacios
Associate Professor of Elec ical Engineering
Thesis Supervisor
Accepted by
s le A. Kolodziej ski
Professor of Electrical Engineering
Chairman, Department Committee on Graduate Students
§
Deeply-Scaled GaN High Electron Mobility Transistors
for RF Applications
by
Dong Seup Lee
Submitted to the Department of Electrical Engineering and Computer Science
On January 21, 2014 in Partial Fulfillment of the Requirements for the Degree of
Doctor of Philosophy
ABSTRACT
Due to the unique combination of large critical breakdown field and high electron velocity,
GaN-based high electron mobility transistors (HEMTs) have great potential for next generation
high power RF amplifiers. The performance of GaN devices has increased continuously in the
last two decades. However, in spite of the improvements, there are still several critical issues
limiting the high frequency operation of these devices. One of the key challenges is the lowerthan-expected maximum current gain cutoff frequency (fT) of deeply-scaled GaN HEMTs. The fT
of the short channel devices is well below both projections from maximum frequency in the long
channel devices and theoretical expectations based on material properties. Another important
issue is a roll-off of the device frequency performance under wide bias range, which limits the
large-signal high speed operation in the deeply-scaled devices. This thesis focuses on these two
important problems and investigates them both analytically and experimentally. First, through
systematic study of the transistor delay, the critical factors limiting intrinsic and extrinsic device
speed are clarified and several technologies are demonstrated to overcome these limits. This has
allowed the demonstration of state-of-the-art high frequency performance GaN HEMTs. Second,
in order to understand the origin of the decrease in device speed at high drain and gate bias, a
new extraction method and novel transistor structure have been developed, which provide an
excellent guide for future device optimization.
Thesis supervisor: Tomis Palacios
Title: Associate Professor of Electrical Engineering
ACKNOWLEDGEMENT
The past four and half years in MIT have been a very important period in my life, which allows
me to become both better researcher and more mature person. As this has been possible thanks to
help of outstanding people, it is my great pleasure to acknowledge them here.
First, I am deeply indebted to my advisor, Prof. Tomas Palkicios. His scientific insight,
consistent support, and endless encouragement have always motivated me to focus on research
and enabled me to overcome challenges. Also, I have learned about many other aspects from him,
including his kindness and politeness. It has been my great fortune to be his student and he will
be my model for future.
Second, I would like to express my sincere gratitude to my thesis committee, Prof. Jesus del
Alamo and Prof. Judy Hoyt for their invaluable advices and comments. Measurement and
analysis methods developed in Prof. Jesus del Alamo's group have been an important foundation
in my research. Also, Prof. Judy Hoyt has always encouraged me with excellent suggestions.
Thanks to their help, I have been able to make my thesis more complete.
Thirdly, although not in my committee, I would like to thank Prof. Dimitri Antoniadis in MIT
and Prof. Patrick Fay in Notre Dame University. With his vast knowledge of device physics and
modeling, Prof. Dimitiri Antoniadis has given excellent advices and guides. Also, Prof. Patrick
Fay has helped me for high frequency measurements and shared his knowledge and insight on
microwave characterization with me.
I would like to acknowledge DARPA NEXT program monitored by Dr. John Albrecht, which
has continuously supported this work. In addition, I am grateful to Triquint and IQE for their
close collaboration for this project. I also want to express my gratitude to Samsung Scholarship
for its financial support for my Ph. D. years.
I am also thankful to all my colleagues in Palacios's group. Former group members, Han Wang
and Jinwook Chung taught me device fabrication methods and measurement skills, which
allowed me to start my research smoothly. Bin Lu, Daniel Piedra and Min Sun were always
happy to share their knowledge on power electronics and help my process. Omair Saadat and
Allen Hsu helped me a lot with low temperature measurement and program setup. I also enjoyed
discussion with Feng Gao and Mohamed Azize on device reliability and film growth,
respectively. Yuhao Zang helped me with simulation setup and I learnt about two-dimensional
material systems from Xu Zhang and Lili Yu. Also, Dr. Kevin Kyungbum Ryu and Dr. Hyung
Seok Lee gave me many good advices and shared their research experiences. Dr. Tatsuya
Fujishima helped me to learn InN process and I enjoyed discussion with Dr. Elison Matioli and
Dr. Puneet Srivastava on RF devices. I thank all other former and present group members
including Benjamin Mailly, Tadahiro Imada, Sameer Joglekar, Cosmi Lin, Charles Mackin,
Ahmad Zubair, Dr. Zhihong Liu, Dr. Takamichi Sumitomo, Dr. Alexandre Rocha Paschoal, Dr.
Marco de Fazio, and so on. Also, I would like to express my appreciation to Joseph Baylon and
Elizabeth Kubicki for their administrative assistance. Moreover, I should not forget the other
sixth floor fellows and MTL staffs for their friendship and help.
Finally, my sincere gratitude goes to my family for their love and support. My lovely wife
Yeonyoon Jeong has always supported me with love. This thesis is dedicated to them.
Contents
C hapter 1. Introduction.......................................................................................................
22
1.1. N itride-based sem iconductors.........................................................................................
22
1.2. GaN transistors.....................................................................................................................24
1.3. Issues in GaN RF devices.....................................................................................................29
1.3.1. Low maxim um device speed.........................................................................................29
1.3.2. Roll-off of the device frequency perform ance at high biases....................................
1.4. Project goal and thesis outline.........................................................................................
30
31
Chapter 2. Basic Device Design and Physics in GaN HEMTs................34
2.1. Polarization in GaN-based heterostructures....................................................................
34
2.2. Fabrication process of GaN HEM Ts................................................................................37
2.3 DC characteristics of GaN HEM Ts..................................................................................
40
2.4. RF characteristics of GaN HEM Ts..................................................................................
41
Chapter 3. Intrinsic Device Limits for Maximum GaN HEMT Speed..........48
3.1. Introduction.........................................................................................................................48
3.2. Limiting factors in the intrinsic GaN transistor..............................................................
50
3.2.1. Analysis tools to study device speed.......................................................................
50
3.2.2. Intrinsic delay.................................................................................................................52
3.3. Gate length scaling...............................................................................................................53
3.3.1. Electron-beam lithography technology ..........................................................................
53
3.3.2. Issues in deeply-scaled AlGaN/GaN HEM Ts...........................................................
56
3.4. Top barrier engineering..................................................................................................
59
3.4.1. Gate modulation efficiency.........................................................................................
59
3.4.2. InAlN/GaN heterostructure.........................................................................................
60
3.4.3. Device fabrication.......................................................................................................
61
3.4.4. DC characteristics.......................................................................................................
63
3.4.5. RF characteristics.......................................................................................................
66
3.5. Channel charge confinem ent........................................................................................
67
3.5.1. Pinch-off and subthreshold characteristics................................................................
67
3.5.2. InAiN/G aN HEM Ts with AlGaN back barrier.........................................................
68
3.5.2.1. AlGaN back barrier heterostructure....................................................................
68
3.5.2.2. Device fabrication...............................................................................................
71
3.5.2.3. Im pact of AlGaN back barrier.............................................................................
72
3.5.2.4. Deeply-scaled InAIN/GaN HEMT with AlGaN back barrier..............74
3.5.3. InAIN/GaN HEM Ts with vertical channel scaling.......................................................76
3.5.3.1. Heterostructure for vertical channel scaling.......................................................
76
3.5.3.2. Device fabrication...............................................................................................
79
3.5.3.3. DC characteristics...............................................................................................
80
3.5.3.4. RF characteristics.................................................................................................
83
3.5.3.5. Vertical channel scaling design...........................................................................
87
3.6. Conclusion..........................................................................................................................88
Chapter 4. Extrinsic Limits for Maximum GaN HEMT Speed..............90
4.1. Introduction.........................................................................................................................90
4.2. Parasitic delay......................................................................................................................91
4.2.1. Origin of the parasitic delay.......................................................................................
91
4.2.2 Low temperature m easurem ent..................................................................................
94
4.2.3 GaN HEM Ts with ultra-low on-resistance.....................................................................96
4.2.3.1 Technologies to reduce source/drain resistances..................................................
96
4.2.3.2. Device fabrication...............................................................................................
97
4.2.3.3. DC characteristics...............................................................................................
98
4.2.3.4. RF characteristics...................................................................................................100
4.3. Extrinsic delay...................................................................................................................103
4.3.1. Im portance of extrinsic delay.....................................................................................103
4.3.2. Device fabrication......................................................................................................104
4.3.3. Passivation effect on DC and pulsed-IV characteristics.............................................105
4.3.4. Passivation effect on RF characteristics.....................................................................108
4.3.5. Extraction of gate fringing capacitance......................................................................109
4.4. Projection of fT in deeply-scaled GaN HEMTs
Conclusion......................................................118
4.5.
.............................
115
4.5. Conclusion ........................................................................................................................118
C hapter 5. D elay under H igh D rain B ias: D rain D elay .................................................
120
5.1. Introduction.......................................................................................................................120
5.2. Drain delay extraction........................................................................................................122
5.2.1. D rain delay extraction method in literatures................................................................122
5.2.2. Small-signal equivalent circuit model including drain delay effects...........................124
5.2.3. Comparison to other extraction m ethods.....................................................................129
5.3. Drain delay in short channel devices.................................................................................131
5.3.1. H igh extracted drain delay rate....................................................................................131
5.3.2. Suppression of gm.int degradation at high drain bias.....................................................134
5.3.3. Scaling gate-to-drain spacing ......................................................................................
136
5.4. Conclusion.........................................................................................................................140
Chapter 6. Nonlinearity of Deeply-Scaled GaN HEMTs....................142
6.1. Introduction........................................................................................................................142
6.2. N onlinearity of gm in GaN HEM Ts...................................................................................143
6.2.1. Current understanding in the literature........................................................................143
6.2.2. Self-aligned GaN HEM Ts............................................................................................145
6.3. N anow ire channel GaN HEM Ts........................................................................................146
6.3.1. Limitation of source access region.........................................................................
146
6.3.2. D evice structure...........................................................................................................148
6.3.3. D evice fabrication........................................................................................................149
6.3.4. D C characteristics........................................................................................................152
6.3.5. Effect of channel w idth and w idth ratio..................................................................
6.3.6. Surrounding gate effect...............................................................................................159
6.3.7. RF characteristics.........................................................................................................160
6.3.8. Breakdow n voltage......................................................................................................161
6.4. Conclusion..........................................................................................................................162
156
C hapter 7. C onclusion and Future W ork...........................................................................164
7.1. Summ ary...........................................................................................................................164
7.2. Future w ork........................................................................................................................170
7.2.1. Channel engineering to increase the electron velocity................................................170
7.2.2. Technologies to m inim ize the extrinsic delay .............................................................
171
7.2.3. Effect on device design on drain delay ........................................................................
171
7.2.4. A dvanced nanow ire channel devices...........................................................................172
R eferences.................................................................................................................................173
List of Figures
Figure 1-1. Diverse application areas of nitride-based semiconductors. ..........................................
22
Figure 1-2. Promising applications of GaN electronics. (a) Power electronics and (b) RF
am p lification . ..........................................................................................................................
24
Figure 1-3. On-resistance and breakdown voltage in different semiconductor device technologies. ....... 25
Figure 1-4. Breakdown voltage and current gain cutoff frequency (fT) of different semiconductor devices
(modified from [18]). GaN device has a potential to outperform other devices thanks to its outstanding
m aterial properties. ..........................................................................................................................
Figure 1-5. Evolution of f and
fmax
26
in AlGaN/GaN HEMTs. Highest fTs and fmaxs reported in each year
(1994-2010) w ere plotted in this figure. .......................................................................................
28
Figure 1-6. fT distribution of 30-nm gate length AlGaN/GaN HEMTs. The plot shows the critical issues in
the device speed of the deeply-scaled GaN HEMTs: (1) low maximum fT, (2) fT roll-off at high drain and
gate bias ranges. .............................................................................................................................
29
Figure 2-1. (a) Zincblende unit cell. (b) Wurtzite GaN crystal structure and its unit cell. ..................
34
Figure 2-2. Crystal structure and polarization field in (a) Ga-face and (b) N-face GaN [41]. ...........
35
Figure 2-3. (a) Polarization charge distribution of AlGaN/GaN heterostructure. (b) 2-DEG induced by
p olarization field . .............................................................................................................................
36
Figure 2-4. Fabrication process of GaN HEMTs. (a) Wafer preparation, (b) mesa isolation, (c) ohmic
contact metal deposition, (d) metal annealing, (e) gate metal deposition, (f) passivation layer
d ep o sition . ......................................................................................................................................
38
Figure 2-5. Top view SEM image of the fabricated AlGaN/GaN HEMT with gate length of 1.3-pim and
gate-to-source distance of 5 tm . ...................................................................................................
39
Figure 2-6. DC (a) output and (b) transfer characteristics of AlGaN/GaN HEMT with gate length of 1.3m . .................................................................................................................................................
40
Figure 2-7. RF measurement setup and flow of the mixed signal. ............................................
41
Figure 2-8. Layouts for (a) device-under-test, (b) open, and (c) short pattern. .................................
42
Figure 2-9. RF characteristics of AlGaN/GaN HEMT with gate length of 1.3-pm. ...........................
44
Figure 2-10. A simple small-signal equivalent circuit model for field-effect transistors. .................
45
Figure 3-1. The electron velocity and electric field characteristics of GaN and other semiconductors
[7 3 ]. ................................................................................................................................................
48
Figure 3-2. fTs of AlGaN/GaN HEMTs reported in literatures. ........................................................
49
Figure 3-3. Small-signal equivalent circuit model based on the delay analysis method. .....................
51
Figure 3-4. (a) T-gate with about 50 nm foot length. (b) Structural instability of T-gate with sub-50 nm
foot length. (c) Misalignment between gate head and foot. ............................................................
54
Figure 3-5. Process flows for (a) double layer and (b) single layer electron-beam lithography. ..........
55
Figure 3-6. Comparison of DC (a) output and (b) transfer characteristics of AlGaN/GaN HEMTs with
gate length of 160 nm and 30 nm . ....................................................................................................
56
Figure 3-7. (a) RF characteristics of 160 nm and 30 nm gate length AlGaN/GaN HEMTs and (b)
comparison of the fis of AlGaN/GaN HEMTs with literature data. ................................................
57
Figure 3-8. fT-Lg product of AlGaN/GaN HEMTs in literatures and this experiment as a function of aspect
ratio (L g/tb). ....................................................................................................................................
58
Figure 3-9. (a) Comparison of lattice constant and energy gap between Ino. 17A1o.83N and other nitride
alloys [84]. (b) Comparison of simulated 2-DEG sheet charge density between InAlN/GaN and
A lG aN /G aN heterostructure [87]. .....................................................................................................
61
Figure 3-10. (a) Cross-sectional schematic image of InAlN/GaN HEMT. (b) Cross-sectional TEM image
of 30 nm gate length device. .............................................................................................................
62
Figure 3-11. DC (a) output and (b) transfer characteristics of 30 nm gate length InAlN/GaN
H E M T . ...........................................................................................................................................
63
Figure 3-12. Comparison of the subthreshold characteristics of InAlN/GaN and AlGaN/GaN HEMTs. (a)
DIBL as a function of gate length. DIBL is extracted in
VDS=1
and 5 V at ID=1 mA/mm. (b) Subthreshold
characteristics of 30 nm gate length devices at VDS=l and 5 V. ...............................................
64
Figure 3-13. Normalized intrinsic transconductance as a function of the gate length in InAlN/GaN and
AlGaN/GaN HEMTs. The inset shows the intrinsic transconductance before normalization. .............
65
Figure 3-14. (a) Maximum fT as a function of the gate length in InAlN/GaN and AlGan/GaN HEMTs. (b)
RF characteristics of 30 nm gate length InAlN/GaN HEMT. ..........................................................
66
Figure 3-15. Energy band structure of InAiN/GaN HEMT in (a) active and (b) pinch-off regimes. .... 68
Figure 3-16. (a) Polarization charge distribution and (b) energy band structure simulation of InAIN/GaN
heterostructure w ith AlGaN back barrier. .....................................................................................
69
Figure 3-17. Simulation result of the band structure of InAlN/GaN heterostructure with AlGaN back
barrier depending on the Aluminum composition. .........................................................................
69
Figure 3-18. Cross-sectional schematic images of (a) control InAlN/GaN heterostructure and (b)
InAlN/GaN heterostructure with AlGaN back barrier. ..................................................................
71
Figure 3-19. Comparison of DC (a) output and (b) transfer characteristics of 65-nm gate length
InAIN/GaN HEMTs with and without AlGaN back barrier. ............................................................
72
Figure 3-20. Comparison of subthreshold characteristics of InAIN/GaN HEMTs with and without AlGaN
back barrier. (a) DIBL as a function of the gate length. (b) Subthreshold characteristics of 65-nm gate
len g th d ev ices. ...........................................................................................................
73
Figure 3-21. (a) Cross-sectional TEM image of 27 nm gate length device. DC (b) output and (c) transfer
characteristics of the device. ............................................................................................................
74
Figure 3-22. Comparison of (a) subthreshold and (b) pinch-off characteristics of the 30-nm gate length
range devices with and without back barrier. .................................................................................
75
Figure 3-23. RF characteristics of 27 nm gate length InAlN/GaN HEMT with AlGaN back barrier. ...... 75
Figure 3-24. (a) Polarization charge distribution and (b) energy band structure of Ino. 17Al 0.83N/GaN
heterostructure with lno15. Gao8ssN back barrier. ...............................................................................
76
Figure 3-25. Cross-sectional TEM images of heterostructures with (a) 26 nm GaN channel and (b) 3.4 nm
G aN chann el. ..................................................................................................................................
77
Figure 3-26. Energy band diagram simulation results depending on the GaN channel thickness (a)
26 nm, (b)
tGaN=1
2
nm, (c)
tGaN=
6.2nm, (d)
tGaN=
3
.
4
nm. .........................................................
tGaN=
78
Figure 3-27. Mobility and 2-DEG charge density depending on GaN channel thickness in InAlN/GaN
heterostructures. .............................................................................................................................
79
Figure 3-28. Contact resistance depending on GaN channel thickness. The inset shows the contact
resistance depending on annealing temperature in 3.4 nm GaN channel wafer. ........................
80
Figure 3-29. DC transfer and output characteristics of 30-nm gate length InAlN/GaN HEMTs with
different GaN channel thickness
(tGaN
26, 12, 6.2, 3.4 nm). ..................................................
81
Figure 3-30. (a) DIBL as a function of gate length in the devices with different GaN channel thickness.
(DIBL is extracted at ID
10-3
A/mm.) (b) Subthreshold characteristics of 30 nm gate length devices with
different G aN channel thickness. ......................................................................................................
82
Figure 3-31. (a) Leakage current at VGs= -6 V in the devices with different GaN channel thickness. (b)
Leakage current path in the devices at pinch-off regime. ................................................................
82
Figure 3-32. (a) Maximum fT as a function of the gate length in the devices with different GaN channel
thickness. (b) RF characteristics of 30-nm gate length devices. ......................................................
83
Figure 3-33. Delay analysis process: (a) extraction of the intrinsic and extrinsic capacitances (b) intrinsic
transconductance depending on the gate length. ..........................................................................
Figure 3-34. Delay extraction results of the devices with different GaN channel thickness at
tGaN
26 nm, (b)
tGaN
12 nm, (c)
tGaN=
6.2 nm, (d)
tGaN
85
VDS=
4 V. (a)
3.4 nm .------...............-.............
86
Figure 3-35. Average electron velocity and mobility of the devices with different GaN channel
thickness. ..................................................
. . . ..............................................................................
87
Figure 4-1. Distribution of each delay component in different gate length devices. .........................
90
Figure 4-2. Simple small-signal equivalent circuit model for (a) ideal transistor with no source/drain
resistances and infinite output resistance and (b) real transistor with non-zero source/drain resistances and
finite output resistance. ....................................................................................................................
92
Figure 4-3. (a) Sheet and contact resistances depending on the temperature. (b) On-resistance depending
on the tem perature. ..........................................................................................................................
94
Figure 4-4. DC (a) output and (b) transfer characteristics of 40-nm gate length device at 300 and 77
K . ...................................................................................................................................................
95
Figure 4-5. (a) RF characteristic of 40-nm gate length device at 300 and 77 K. (b) fT as a function of the
drain bias at different tem peratures. .............................................................................................
95
Figure 4-6. Schematic image of sub-30 nm device with extremely low on-resistance. ......................
98
Figure 4-7. (a) TLM1 pattern and its measurement result. (b) TLM2 pattern and its measurement
result. ..............................................................................................................................................
99
Figure 4-8. DC characteristics of the devices with gate length of (a) 50-nm and (b) sub-30 nm. .......... 100
Figure 4-9. (a) Comparison of the maximum fT between devices in this experiment and devices used in
section 3.5.3. (b) RF characteristic of sub-30 nm gate length device. ...............................................
101
Figure 4-10. (a) Delay analysis result of devices with regrowth contact and scaled source/drain distance
(LSD). (b) Comparison of delay analysis of 30-nm gate length devices with Ron > 1 2-mm (alloy contact
and LsD> 1 [tm) and Ron < 0.5 £-mm (regrowth contact and
LSD <0.7
gm). ...............................
102
Figure 4-11. Parasitic delay components depending on the gate length. .............................................
103
Figure 4-12. Cross-sectional device structure used in this study. .......................................................
105
Figure 4-13. DC (a) output and (b) transfer characteristics of sub-30nm gate length devices with A1 0
2
passivation thickness of 10 nm and 40 nm . .................................................................................
3
106
Figure 4-14. DIBL in the devices with the passivation thickness of 10 nm and 40 nm. ........................ 106
Figure 4-15. Current collapse depending on the passivation thickness and comparison of the DC and
pulsed-IV characteristics of the devices with passivation thickness of 10 nm and 40 nm. .................... 107
Figure 4-16. (a)
fT
as a function of the gate length depending on the passivation thickness
(tpass).
(b)
Degradation of fT with increasing the passivation thickness. (c) Cross-sectional image of the gate fringing
capacitance due to increase of the passivation thickness. ..................................................................
108
Figure 4-17. Extracted Cgs and
Cgd
in (a) saturation bias condition
(VDS=
3 V,
VGS
-3.5 V) and (b) ON-
state condition (V DS= 0 V , V GS= OV ). .............................................................................................
110
Figure 4-18. Gate capacitance distribution at the pinch-off bias condition. ........................................
110
Figure 4-19. Extraction of the gate fringing capacitance at the pinch-off condition. ...........................
111
Figure 4-20. Gate capacitances extracted from the simulation results from different gate length. ......... 112
Figure 4-21. Gate fringing capacitance extraction from the simulated gate capacitance at (a) pinch-off
condition and (b) ON -state condition. .............................................................................................
113
Figure 4-22. Gate fringing capacitance extracted from the measurement depending on the passivation
th ickn ess. ......................................................................................................................................
1 14
Figure 4-23. (a) Simulation device structure for T-gate and (b) gate fringing capacitance depending on
passivation thickness and T-gate height. ..........................................................................................
115
Figure 4-24. (a) Gate capacitance modeling. (b) Intrinsic transconductance model including short channel
effect. (c) Output resistance model including short channel effect. ....................................................
116
Figure 4-25.
projection depending on the technology improvement. ..............................................
116
Figure 4-26. RF characteristics of sub-30 nm gate length device. ......................................................
117
Figure 5-1.
121
fT
fT
as function of
VDS
in different gate length devices. ......................................................
Figure 5-2. N. Moll delay time analysis method [40]. Extraction methods of (a) channel charging delay
and (b) drain delay . ........................................................................................................................
122
Figure 5-3. Cross-sectional image of GaN device under deep saturation regime. ..............................
124
Figure 5-4. (a) Lateral electric field and (b) electron charge distribution in the depletion region based on
the charge control model used for base-collector junction in BJT. (This model can be used for drain-side
depletion region in H EM T .) ..........................................................................................................
125
Figure 5-5. Small-signal equivalent circuit model including the gate extension effect. ....................... 127
Figure 5-6. Change of each delay component with increasing drain voltage. (a) 1, (b) T2, (c)T3. ....
. . . . . 128
Figure 5-7. Drain delay extracted from 220-nm gate length device based on the different extraction
meth o d . .........................................................................................................................................
13 0
Figure 5-8. Drain delay extracted from the short channel devices. (a) Lg=120-nm, (b) Lg=60-nm. ...... 131
Figure 5-9. Change of (a) Cgs and (b)
gmint
with increasing drain voltage in different gate length
d ev ices. .........................................................................................................................................
13 2
Figure 5-10. Change of DC gmwith drain voltage. (a) Lg=40-nm, (b) Lg=60-nm, (c) Lg=330-nm..........1 33
Figure 5-11. Extracted drain delay rate as a function of the gate length. The drain delay rate increases
rapidly as the gate length scales down below about 100 nm. ............................................................
134
Figure 5-12. (a) Blocking the path of punch-through current with structure of vertical channel scaling. (b)
Comparison of the
gm.int
degradation at high drain bias between the devices with vertical GaN channel
scaling and control structure. ........
.
-... -.. ...........................................................................
135
Figure 5-13. Comparison of the drain delay rates in the 80-nm gate length devices with vertical GaN
channel scaling and control structure. .............................................................................................
136
Figure 5-14. (a) Schematic and top view SEM image of the device with scaled gate-to-drain spacing. (b)
Comparison of the fT trends at high drain bias between devices with
n m . ........................................................
Lgd=
100-nm and
Lgd=
......................................................................................
350-
13 9
Figure 5-15. (a) Expansion of the depletion region width and (b) change of Cgd in the devices with
Lgd= 100 nm and 300 nm . ...............................................................................................................
140
Figure 6-1. Nonlinearity of (a) g. and (b) fT in GaN HEMTs with different gate length. .................... 142
Figure 6-2. Two different explanations about origin of gm nonlinearity. (a) Non-linear source access
resistance [139]. (b) Optical phonon scattering [143]. ......................................................................
144
Figure 6-3. (a) Device structure of self-aligned GaN HEMTs and DC (b) output and (c) transfer
characteristics of the device [127]. ..................................................................................................
145
Figure 6-4. (a) Cross-section schematic of short channel GaN device under saturation. (b) Simulation of
longitudinal electric field and resistance in the source access region [139]. (c) Electron velocity depending
on electric field in the different transport model [139]. ....................................................................
147
Figure 6-5. Device structure of the nanowire channel GaN HEMT. ..................................................
148
Figure 6-6. Previous studies about nanowire channel GaN devices. (a) [145], (b) [146], (c) [162]. ...... 149
Figure 6-7. Fabrication process of the nanowire channel GaN HEMT. (a) Mesa isolation and ohmic
contact formation, (b) Si 3 N 4 deposition and nanowire patterning with e-beam lithography and selective
dry etching with CF 4 plasma, (c) gate e-beam patterning with ZEP520 resist, (d) top barrier and GaN
channel dry etching with BCl 3/Cl 2 plasma, (e) Si3N4 pattern removal with dry etching with CF 4 plasma,
(f) gate metal deposition and lift off, (g) removal of Si 3 N 4 pattern on the access region with BOE wet
etching, (h) A120
3
passivation layer deposition with ALD. ..............................................................
150
Figure 6-8. Top view SEM image of (a) Si 3N 4 nanowire pattern and (b) device after gate lift off process.
Only under the gate, the channel is etched. ......................................................................................
151
Figure 6-9. (a) SEM and (b) AFM images of the test structure after removing gate metal. .........
151
Figure 6-10. DC (a) transfer and (b) output characteristics of 70-80 nm gate length nanowire channel
device and conventional planar device. The nanowire channel device characteristics are normalized based
on the effective channel w idth. .......................................................................................................
153
Figure 6-11. (a) Gate current injection method and (b) source resistance extracted by the method. ...... 154
Figure 6-12. DC (a) transfer and (b) output characteristics of nanowire channel device and conventional
device based on the entire device width normalization. .....................................................................
155
Figure 6-13. (a) Variation of nanowire channel width in the device layout. (b) Extrinsic gm as a function
of the gate voltage in the devices with different width ratio. ..............................................................
156
Figure 6-14. Test device structure to study the effect of the nanowire width. .....................................
157
Figure 6-15. DC (a) transfer and (b) output characteristics of the test structure and planar device. ....... 158
Figure 6-16. Current flow in (a) nanowire device and (b) test structure with wide channel width. ........ 158
Figure 6-17. Test device structure to study the surrounding gate effect. .............................................
159
Figure 6-18. DC (a) transfer and (b) output characteristics of the test structure and conventional planar
dev ice. ...................................................
...................................................................................
15 9
Figure 6-19. f1 as a function of the gate voltage in the nanowire channel device and conventional planar
dev ice. ......................................
.............
. . . ............................................................................
16 0
Figure 6-20. Fringing capacitances in the nanowire channel device. (a) Fringing capacitance between gate
and sidewall of the nanowire. (b) Fringing gate capacitance between gate and additional access
reg io n . ..........................................................................................................................................
16 1
Figure 7-1. (a) Improvement in fT of deeply-scaled GaN HEMTs through this work. (b) Comparison of
the fTs in this work with those of AlGaN/GaN HEMTs reported in the literature (Figure 3-2). ............ 167
List of Tables
Table 1-1. Comparison of electrical properties of GaN with relevant semiconductors. ...................
23
Chapter 1. Introduction
1.1. Nitride-based semiconductors
In recent 20-30 years, a nitride-based semiconductor technology has been tremendously
developed since critical issues hindering its progress, such as high quality growth and p-type
doping, have been solved through extensive research [1], [2]. The outstanding material properties
of the nitride alloys have stimulated many different fields, which expands many possible
application areas as shown in Figure 1-1.
In optoelectronics, the wide range of potential energy band gaps from 0.7 eV (InN) to 6.2 eV
(AlN) can provide a single complete solution for emission and detection from infrared to
ultraviolet. Since the first GaN electroluminescent diode was demonstrated in 1971 [3], a light
emitting diode (LED) technology based on the nitride alloys has been improved remarkably [2],
IRF
Power Conversion
(Automobiles / Aircrafts)
Stations)
(Wireless
Transistors
PowerBase
Solid State Lighting
White/Blue/UV LEDs)
MEMS
(Pressure Sensors)\
UV Detectors
(Bio Detection)
Switches
(Display Panels)
Blue Laser Diodes
(DVD Storage)
Engine Electronics
(Temperature Sensors)
Hydrogen Generation
(Fuel Cells)
High Frequency MMICs
(Wireless Broadband)
Figure 1-1. Diverse application areas of nitride-based semiconductors.
22
[4] and the first commercial nitride-based LEDs were launched in Nichia Chemical Industries in
1993. Also, the potential optoelectronic applications have expanded from the original LEDs, to
photo detector [5] and laser diodes [6].
In addition, the high structural stability and Young's modulus, as well as strong piezoelectricity
of these materials make them attractive for microelectromechanical systems (MEMS). For
example, GaN cantilevers [7], [8] and surface acoustic wave (SAW) devices [9], [10] were
demonstrated by using these excellent properties. In addition, chemical and biological
applications such as gas sensor and bio sensor were explored [11], [12].
In electronics, GaN-based devices are a very promising candidate for both high power and high
frequency applications. Table 1-1 shows a comparison of key electrical properties of various
semiconductors. Compared to other semiconductors such as Si and GaAs, GaN can provide a
significantly larger breakdown voltage for a given on resistance thanks to its high critical electric
field. Moreover, high electron mobility and saturation velocity allow GaN-based devices to
operate at very high frequencies. SiC has many properties similar to GaN, but several critical
issues such as challenge in heterostructure design and extreme process condition limit its
applications. In contrast, GaN can form heterojunctions with other nitride alloys and this makes
Semiconductors
GaAs
InP
(AIGaAs/InGaAs)
(InAIAs/InGaAs)
sic
GaN
(AIGaN/GaN)
Properties
Unit
Band gap
eV
1.11
1.42
1.35
3.26
3.39
Critical
breakdown field
MV/cm
0.3
0.4
0.5
3
3.3
1.0
(1.0)
1.3
(2.1)
1.0
(2.3)
2.0
(2.0)
1.3
(2.5)
1350
8500
5400
700
2000
Saturated (peak)
electron velocity
Electron mobility
at 300 K
x 10
7
cm/s
cm 2/V-s
Table 1-1. Comparison of electrical properties of GaN with relevant semiconductors.
23
it possible to utilize high-electron mobility transistor (HEMT) structure which has been widely
used in many other semiconductor systems. Moreover, a two-dimension electron gas (2-DEG)
induced by the polarization effect in the heterojunctions makes device fabrication simple,
removing need for additional doping process. Based on these advantages, GaN electronics has
been developed significantly in the past three decades.
1.2. GaN transistors
The first demonstration of GaN-based transistors was based on MESFET structure [13].
However, after the existence of the 2-DEG with high mobility was verified in AlGaN/GaN
heterostructures [14]-[16], the HEMT structure has become the main device structure for GaN
transistors [17]. The potential of GaN transistors which can provide both large breakdown
voltage and high speed operation has attracted two main commercial areas: 1) power switching
and 2) RF high power amplification, as shown in Figure 1-2. Although there is no fundamental
difference in the basic device structure, the device design and target performance vary depending
on the specific application.
(b)
(a)
Figure 1-2. Promising applications of GaN electronics. (a) Power electronics and (b) RF amplification.
24
1000
GaN (MIT 2011)
GaN (IR)
I GaN (EPC)
0 GaN (other research labs)
0 Sic
Si Super-Junction
Si IGBT
E 100
Si Limit
1
0
U)
10
Uk
10.
10O
(
- --------- -.......
- - -....
A Sic Limit
0.11
GaN Limit
1000
100
10000
Breakdown Voltage (V)
Figure 1-3. On-resistance and breakdown voltage in different semiconductor device technologies
In the case of devices for power switching, their operating frequency range is typically below
GHz (kHz - MHz), while the breakdown voltages vary from a few tens of volts to a few
thousands of volts. In addition to the breakdown voltage, the device on-resistance is another
important parameter, which is critical to maximize the energy efficiency of power electronics
circuits. Thus, the product of the breakdown voltage and specific on-resistance is one of the most
important figure-of-merits (FOMs) in this application. Figure 1-3 shows theoretical comparison
and experimental results of the FOM of GaN transistors with other semiconductor technologies.
The theoretical estimation based on the material parameters anticipates more than an order-ofthe-magnitude better performance in GaN transistors than conventional Si devices. Also,
research GaN transistors already outperform commercial Si devices optimized for best
performance. Although there are still many issues which need to be solved for successful
commercialization, these results clearly show the huge potential of GaN devices in power
electronics.
25
100
SiBJT
*
ANTT GaN HFET
A MIT
4A
SInPH8T
A
GaNHFETA
A
GaN HFET
SSi NMOS
C
UCSO
A GaH HFET
HIRL
MP DHBT
0)
GaNHFET
C
A HFET
A
TRW
10
-
'l
xdAkaWn
PSHBT
0
DHBT
WVesse
S NEC
HflW DHBT
C
0
T
*kIPDHBT
h
IM IBM SIGe
ma
BJ T leomWs
Si BJT Hitachi-
1
-
%
Sim
SiGo HBT
Dahniea-BenzSiGe HBT
IBM SIGe
9HP
9HP
10
100
1000
fT [GHz]
Figure 1-4. Breakdown voltage and current gain cutoff frequency (fT) of different semiconductor devices
(modified from [18]). GaN device has a potential to outperform other devices thanks to its outstanding
material properties.
Another promising application for GaN transistors is in RF power amplifiers. In the devices
targeting this application, maximum output power and operating frequency are the most
important parameters. As these two parameters are closely related to the breakdown voltage and
electron velocity, GaN is an ideal candidate to improve the performance of the RF power
amplifiers to the next level as shown in Figure 1-4 [18]. Since the first microwave characteristics
of AlGaN/GaN HEMT were reported in 1994 [19], there have been extensive efforts to improve
its performance. Specifically, the research on RF devices has focused on two topics: 1) largesignal power performance, 2) small-signal frequency characteristics.
The large-signal power performance including maximum output power density (Put) and
power-added efficiency (PAE) is closely related to the required specs of power amplifiers. These
26
characteristics are measured at a target operating frequency and show how much power can be
delivered efficiently from the devices. The first large-signal RF characteristics were measured
with 1 -tm gate length AlGaN/GaN HEMT at 2 GHz in 1996 [20]. The device showed Po
0 t of 1.1
W/mm and PAE of 18.6 %. Since then, both the operating frequency and power performance
have been increased significantly. Wu et al. reported P0 ut of 3.3 W/mm and PAE of 18.2 % at 18
GHz in 1997 [21] and Moon et al. demonstrated a 0.15 tm gate length device with Po0 t of 6.6
W/mm and PAE of 35 % at 20 GHz [22]. In 2004, by using a field-plate technology [23], Chini
et al. demonstrated devices with Pout of 12 W/mm and PAE of 58 % at 4 GHz [24] and Wu et al.
significantly improved P0 ut to 41.4 W/mm with PAE of 60 % at the same frequency [25]. In 2005,
Palacios et al. reported P0 ut of 10.5 W/mm and PAE of 33 % at 40 GHz [26] and Wu et al.
improved Po0 t to 13.7 W/mm and PAE to 40 % at 30 GHz in 2007. In addition, many promising
results in high frequency band such as V and W bands have also been reported [27]-[29].
Complementary to the large-signal power performance, the small-signal characteristics
highlight the potential of devices by providing information about their maximum possible
operating frequency. Current gain cutoff frequency (fT) and power gain cutoff frequency (fmax)
are the most important figure of merits (FOMs) in the small-signal performance. Since the
possible operating frequency range of a real application is determined based on these metrics,
improving the cutoff frequencies is an important step to expand the potential application area.
Since Khan et al. reported the first small-signal microwave characteristics of 0.25-[tm gate length
AlGaN/GaN HEMT with fT= 11 GHz and fmax= 35 GHz [19], there has been a continuous
increase of both fT and fmax as shown in Figure 1-5. Khan et al. increased the maximum fT and
fmaxto
36.1 GHz and 70.8 GHz, respectively in 0.25-tm gate length device in 1996 [30]. Wu et
al. demonstrated fT of 50 GHz and fmax of 92 GHz in the device with a gate length of 0.2 pim in
27
400
AIGaN/GaN HEMTs
[38]
300
fmax
-
-
N
[37]
[35]
in
E 200
M
[33]
[32]
T
,[39]
[34],
*[37]
"*W
I
[36]
[34]
100 . .32]
[30]
[19]
[19]'
190
,/
[31]
[31
[30]
1995
2000 2005
Year
2010
2015
Figure 1-5. Evolution of fT and fmax in AlGaN/GaN HEMTs. Highest frs and fmaxs reported in each year
(1994-20 10) were plotted in this figure.
1997 [31] and Micovic et al. improved the f1 to 110 GHz and fmax to 140 GHz with 0.15 ptm gate
length device in 2000 [32]. In 2002, Kumar et al. fabricated 0.12
m gate length device with f1
of 121 GHz and fmax of 162 GHz [33]. In 2005, Palacios et al. demonstrated 90 nm gate length
device with
fT
of 163 GHz and fmax of 185 GHz [34]. In 2006, Palacios et al. pushed the fmax to
230 GHz by using InGaN back barrier structure in 100 nm gate length device [35] and
Higashiwaki et al. improved the f1 to 181 GHz by scaling the gate length to 30 nm [36]. In 2008,
with 60 nm gate length AlGaN/GaN HEMT with thin barrier, Higashiwaki et al. reported fl of
190 GHz and fmax of 251 GHz [37]. Finally, in 2010, Chung et al. obtained a new record
performance, f- of 225 GHz and fmax of 300 GHz in the 55 nm and 60 nm recessed-gate
AlGaN/GaN HEMT, respectively [38], [39].
28
200
fT drop in high VDS
Low maxim urn fT
50
150
kL
g
.100
-3
~20
50
L =3O-nm
00
0-n
2
200
1VDS=3
VGS= -5.6V
010
10
4 6 8
VDs (V)
t\~NFrequency (GHz
S150
200
fT dirop
in high VGS
L g= 30-nm
9100
4
VDs (V)
2
0 -10
-4
VGS (V)
VGS (V)
-8
Figure 1-6. fT distribution of 30-nm gate length AlGaN/GaN HEMTs. The plot shows the critical issues
in the device speed of the deeply-scaled GaN HEMTs: (1) low maximum fT, (2 fr roll-off at high drain
and gate bias ranges.
1.3. Issues in GaN RF devices
In spite of the significant improvement in microwave performance of GaN HEMTs, there are
still many unsolved problems. Especially, two critical issues related to the speed of the devices
are summarized as shown in Figure 1-6.
1.3.1. Low maximum device speed
As mentioned in the previous section, the device speed or current gain cutoff frequency (f1 ) of
GaN HEMTs has been increased continuously. The main strategy to increase the speed of the
29
device has been gate length scaling and the minimum gate length has been dramatically
decreased to about 30 nm range [36]. However, in spite of the extremely scaled gate length, the
maximum device speed is much lower than both the theoretical expectations based on the
material properties and projections based on experimental long channel devices. Moreover, the
variation of the device speed depending on the technology becomes larger in shorter channel
devices. In order to realize the potential of GaN transistors, the causes for degradation and
variation of the speed in the deeply-scaled devices need to be clarified. Also, new technologies to
overcome these challenges are necessary.
1.3.2. Roll-off of the device frequency performance at high biases
Compared to other high frequency semiconductor devices based on GaAs or InP, one of the
main differences in GaN RF devices is the large signal operation required to delivered high
output power. In order to support high speed large-signal operation, maintaining high frequency
performance over a wide bias range is as important as pushing the maximum speed at a given
bias condition. However, as shown in Figure 1-6, the speed of a typical GaN device decreases
rapidly with increasing both drain bias and gate bias. Moreover, it is observed that the
degradation becomes more significant in shorter gate length devices, which makes it one of the
key challenges in the deeply-scaled GaN HEMTs. The decrease in device speed at high drain
bias has been already studied in other semiconductor devices and the effect, which is called drain
delay, has been measured based on the method proposed by Moll et al.[40]. However, it is
challenging to understand the essence of the effect accurately since the extraction method is not
based on theoretical and mathematical background. In the case of the decrease of the device
speed at high gate bias or high drain current, its origin has been controversial. Since there is no
30
solid understanding about these problems, it is very challenging to find a good solution to
overcome them.
1.4. Project goal and thesis outline
This thesis addresses two key issues regarding the speed of the deeply-scaled GaN HEMTs,
described in the previous section. First, in order to identify what limits the maximum speed of
these devices, systematic analysis of the device speed is performed by revisiting the device
physics. Based on the study, new technologies are applied to overcome these challenges and
push the device speed to the next level. Then, the origin of the roll-off of the device speed in the
wide bias range is investigated through both theoretical and experimental studies. Based on the
analysis, new approaches to minimize the effects are developed.
The thesis is organized as follows:
In chapter 2, the basics of GaN HEMT technology are concisely outlined. The mechanism of
GaN heterostructures and device fabrication process are described. In addition, both DC and RF
characteristics of typical GaN HEMTs are explained, highlighting important figures-of-merits.
In chapters 3 and 4, the limitation in the maximum speed of the deeply-scaled GaN HEMTs is
studied in detail by dividing the device into intrinsic and extrinsic regions. In chapter 3, the
limiting factors in the intrinsic device performance are described. In order to suppress the
increase of the intrinsic delay caused by the degradation of the gate modulation efficiency, an
InAlN/GaN heterostructure is applied to a 30 nm gate length device, which allows a maximum f1
of 245 GHz, higher than any other GaN HEMTs demonstrated previously. In addition, to
31
improve the subthreshold and pinch off characteristics, two different approaches are investigated.
Both AlGaN back barrier structure and vertical channel scaling technologies contribute to the
improvement of the device performance by increasing the channel charge confinement. Also, the
relevant trade-offs of each technology are also discussed for further optimization. Thanks to
these studies, the maximum speed of GaN HEMTs is pushed to 300 GHz.
Chapter 4 studies the extrinsic device components limiting the maximum device. First, the effect
of the parasitic resistances is investigated through characterization at low temperature. To reduce
these parasitic resistances, several technologies including heterostructure with low sheet
resistance, sub-[ m source-to-drain distance, and regrowth contact have been combined in this
work and the total device resistance is decreased to about 0.4 Q-mm. As the second extrinsic
device component, the impact of the fringing gate capacitance is investigated, focusing on the
passivation layer. The significant influence of the fringing gate capacitance on the speed of
deeply-scaled devices is studied based on both experimental results and device simulation. Based
on these studies, we show that maximum device speed over 400 GHz is possible in the 30 nm
gate length range. An experimental device with a maximum fT of 375 GHz is demonstrated by
minimizing the extrinsic components.
In chapter 5 and 6, the roll-off of the device frequency performance at high biases is discussed.
In chapter 5, in order to study the drain delay more accurately, a new extraction method is
proposed based on the small-signal equivalent circuit model and it is compared to the other
methods in literature. In addition, based on the proposed method, it is shown that rapid decrease
in the speed of short channel devices at high drain bias is not only caused by the drain delay
32
effect, but also degradation of the gate electrostatics. In order to reduce the delay resulting from
these effects, technologies with vertical channel scaling and lateral gate-to-drain distance scaling
are investigated.
In chapter 6, the origin of the decrease of device speed with increasing gate bias (or drain
current) is identified. In order to prove that it results from the limitation of the current supply in
the source access region, a novel nanowire channel structure with sub-100 nm gate length is
developed. The proposed nanowire channel device solves the nonlinearity of gm and fT thanks to
its higher current drivability of the source access region compared to that of the intrinsic channel.
Moreover, the current density of the nanowire channel is increased over 3 A/mm which is closer
to the theoretical expectation. These results do not only verify that drop of the device speed at
high gate bias is caused by extrinsic source region, but also emphasize the importance of the
source design to realize the full potential of intrinsic GaN HEMTs.
Finally, chapter 7 summarizes the main results of this thesis. In addition, future research
directions are proposed to further improve the speed of the deeply-scaled GaN HEMTs.
33
Chapter 2. Basic Device Design and Physics in GaN HEMTs
In this chapter, the basic device design and physics parameters in GaN-based high electron
mobility transistors (HEMTs) are briefly explained, including polarization, device fabrication
process, and DC/RF characteristics.
2.1. Polarization in GaN-based heterostructures
The most common crystalline structure in GaN is wurtzite, with Gallium (Ga) and Nitrogen (N)
atoms ionically bonded. Due to the difference in the electron affinity between two materials, the
distribution of valence electrons in the bonding becomes strongly asymmetric, which combined
with the lack of center symmetry in the wurtzite structure induces a polarization field. In other
compound semiconductors such as GaAs and InP, the polarization field also exists in each ionic
bonding through the same mechanism, but it is almost cancelled out because of the symmetry of
their zincblende crystal structure (Figure 2-1(a)) and the net polarization becomes close to zero.
(a)
(b)
Figure 2-1. (a) Zincblende unit cell. (b) Wurtzite GaN crystal structure and its unit cell.
34
Ga-face
N-facm
N
Ga
N
Ga
Substrate
Substrate
(a)
(b)
Figure 2-2. Crystal structure and polarization field in (a) Ga-face and (b) N-face GaN [41].
In GaN, however, wurtzite crystal structure prevents the offset and generates a fairly large net
polarization field in the c-axis direction (Figure 2-1(b)). Depending on the growth direction, GaN
can be divided into Ga-face and N-face, and the direction of the polarization field becomes
opposite as shown in Figure 2-2 [41]. (Research in this thesis is based on Ga-face structure and
the following also assumes the Ga-face unless mentioned otherwise.) This polarization field is an
intrinsic material property determined by chemical elements and crystal structure, so that it is
called as a spontaneous polarization (Psp).
In GaN heterostructures such as AlGaN/GaN, InAlN/GaN, and AlN/GaN, there is an additional
polarization component in addition to the spontaneous polarization. Once the top layer (AlGaN,
InAlN, or AlN) is grown on top of the GaN, it gets strained due to the lattice mismatch. If the
layer thickness is below its critical thickness, the strain is maintained and it induces piezoelectric
polarization (PPZ) [14]. Thus, the polarization in the heterostructure is typically combination of
the spontaneous polarization and piezoelectric polarization. The polarization can be expressed
35
GaN
Substrate
a2
- EG
2D
-- -E-GaN
+UAIGaN
-Substrate
+CJGaN
4,
0
0
GaN
AIGaN
(a)
(b)
Figure 2-3. (a) Polarization charge distribution of AlGaN/GaN heterostructure. (b) 2-DEG induced by
polarization field.
with a polarization charge at the interface and Figure 2-3(a) shows the polarization charge
distribution in AlGaN/GaN heterostructures.
Large energy band bending caused by high polarization field in the top barrier layer generates
donor-like surface states and free electrons. As shown in Figure 2-3(b), the free electrons slide
down to GaN, following the electric field and accumulate at the interface between the top barrier
layer and the GaN, forming a two dimensional electron gas (2-DEG) [42]. This process continues
until the Fermi level is pinned at the ionized donor-like surface state level. Thanks to the sharp
interface at the heterostructure and the separation from the positive charges of the surface states,
the 2-DEG can have a high mobility over 1000-2000 cm 2 -V/s [43], [44]. Also, the high
polarization field in the structure allows the density of the 2-DEG to go over 1013 cm~2. The
combination of high mobility and large charge density, which is unique compared to other
semiconductors, makes GaN a very promising candidate for high frequency and high power
applications.
36
2.2. Fabrication process of GaN HEMTs
Compared to Si MOSFETs, the fabrication process of conventional AlGaN/GaN HEMTs is
significantly simpler. The 2-DEG channel, which is formed spontaneously at the heterostructure
interface, eliminates the need of any additional doping process such as implantation and dopant
activation annealing. In addition, since the top AlGaN layer isolates the gate electrode from the
channel thanks to its larger band gap and high Schottky barrier, a gate oxide formation step
similar to the one in Si MOSFET technology is not required.
Figure 2-4(a) shows an example of an initial AlGaN/GaN wafer structure. As a substrate for the
GaN growth, Si, sapphire or SiC is widely used. On top of the 1-2 tm GaN, AlN interlayer and
AlGaN top barrier are grown pseudomorphically to form heterojunction. The AlN interlayer is
typically inserted between top barrier (AlGaN) and GaN in order to improve the 2-DEG mobility
by reducing alloy disorder scattering [45]. Figure 2-4(b)-(f) shows an example of conventional
fabrication process of AlGaN/GaN HEMTs. The process begins with mesa isolation with
BCl 2/C12-based plasma dry etching as shown in Figure 2-4(b). The depth of the mesa etching
(150 ~ 200 nm) should be much deeper than that of the 2-DEG channel to reach complete
isolation. The sidewall of the mesa is depleted due to the plasma damage and Fermi level pinning
at the surface, which prevents the leakage current through the sidewall contact. As an alternative
method for device isolation, implantation is also widely used [46]-[49]. The damage induced by
the implantation destroys the 2-DEG channel outside the active area, which provides isolation
effect. Compared to the mesa isolation, the advantage of the implantation isolation is that it does
not generate a large step height, which is favorable for subsequent technology processes.
After device isolation, source/drain contacts are made through photo lithography and
subsequent metal stack deposition as shown in Figure 2-4(c). In the conventional contact process,
37
I
)AIN
imtin
AIN
GaN (1 ~ 2 pm)
GaN
Substrate (SiC, A120 3, Si)
(a)
AIGaN
GaN
Substrate
(b)
(c)
NAfftN
AIN
~-
GaN
Substrate
A
AIN
-
~-GaN
AIN
GaN
Substrate
Substrate
(d)
(e)
Substrate
(
Figure 2-4. Fabrication process of GaN HEMTs. (a) Wafer preparation, (b) mesa isolation, (c) ohmic
contact metal deposition, (d) metal annealing, (e) gate metal deposition, (f) passivation layer deposition.
a Ti/Al-based metal stack is widely used such as Ti/Al/Ni/Au [50], Ti/Al/Mo/Au [51], and
Ti/Al/Ti/Au [52]. After the deposition, the metal stack forms the Schottky contact to the AlGaN
top barrier. To make it an ohmic contact, a high temperature annealing above 700-800 'C is
required as shown in Figure 2-4(d). Depending on the heterostructure, the optimum annealing
condition varies, but generally, it is between 800 'C and 900 'C. During the high temperature
annealing, Ti forms TiN with AlGaN layer introducing N-vacancies near the interface, which act
as donor states, creating a tunnel junction to reduce the contact resistance [53], [54]. The
combination of TiN, n-type doped AlGaN interface, and Ti/Al alloy provide an ohmic contact in
the heterostructure. The top Ni/Au layers prevent the oxidation of Ti/Al and Ni also acts as a
diffusion barrier for Au into Al. After annealing of the metal stack, the surface of the contact
38
becomes rough due to the alloy of the different metal layers. The contact resistance in the
conventional alloy contact process described above is about 0.3-0.6 Q-mm in AlGaN/GaN
heterostructure.
After ohmic contact process, a gate electrode is formed between source and drain contacts
through gate photo lithography and metal deposition as shown in Figure 2-4(e). Ni/Au or Pt/Au
stacks are generally used as gate metal due to the high Schottky barrier height between Ni or Pt
and the AlGaN layer. Au is used on top to lower the sheet resistance of the metal stack. Since the
gate electrode is defined through a different lithography than the ohmic contacts, there is a space
between the gate electrode and the source/drain metal contacts, the access region. In the
conventional GaN HEMT process, it is challenging to make a self-aligned device with no access
region because of the high temperature annealing needed for ohmic contact formation and the
subsequent rough morphology of the annealed contact.
As a final step in the fabrication, a passivation layer is deposited on top of the device to reduce
surface trapping and current collapse, as shown in Figure 2-4(f). Several dielectric materials have
been used as passivation, including Si 3N4 [55], SiO2 [56], and A12 0 3 [57]. Figure 2-5 shows a top
view Scanning Electron Microscopy (SEM) image of the fabricated AlGaN/GaN HEMT.
Figure 2-5. Top view SEM image of the fabricated AlGaN/GaN HIEMT with gate length of 1.3-pm and
gate-to-source distance of 5 pm.
39
Lg= 1.3-pm
0.8 VGS -4
Lg= 1.3-pm
E
V
0.8
VDS= 1, 3,
5V
-4 -3
-2
E
0.4-
00
0.4
0
0
0-
2
0
4
6
VDS (V)
8
10
5
--------
-1
0
1
VGS (V)
(b)
(a)
Figure 2-6. DC (a) output and (b) transfer characteristics of AlGaN/GaN HEMT with gate length of 1.3pm.
2.3 DC characteristics of GaN HEMTs
Figure 2-6(a) shows the DC output characteristic of a conventional AlGaN/GaN HEMT with
gate length of 1.3 pm. At low drain voltage (VDs), drain current is linearly dependent on VDS and
the slope, which is called as on-resistance (Ron), is determined by sum of the contact
resistance,
access resistance and channel resistance. At high VDS above knee voltage, drain current is
saturated and it is mainly determined by gate voltage (VGS). In spite of the long gate length, the
maximum drain current of the device is over 0.7 A/mm at a gate voltage (VGS)
Of
1 V. (The
maximum positive gate voltage (1 - 2 V) is limited by the turn-on voltage of the gate Schottky
contact.) As the maximum drain current is determined by the sheet charge density of the
heterostructure and electron velocity dependent on lateral electrical field, it can be further
increased by using heterostructure with higher polarization charges and scaling the device
laterally.
40
As shown in Figure 2-6(b), the threshold voltage (VT) is typically negative because the
polarization-induced 2-DEG channel needs to be depleted to turn off the device (depletion-mode).
In order to achieve enhancement-mode operation, additional process or change of heterostructure
design is necessary such as gate recess [58], [59], fluorine treatment [60] and InGaN cap layer
[61]. A transconductance (gm), defined as a ratio of drain current change to gate voltage change,
is also the important parameter in the transfer characteristic. It typically increases with increasing
Vcs and reaches its maximum point at 30-50 % of maximum drain current level as shown in
Figure 2-6(b). The gm can be improved by increasing coupling between gate and 2-DEG charges
and electron velocity in the channel.
2.4 RF characteristics of GaN HEMTs
The high frequency performance of GaN transistors is typically measured by using a Vector-
Vector Network Analyzer
Bias Tee
CBias
Tee
[DC Power Supply
Device under Test
Figure 2-7. RF measurement setup and flow of the mixed signal.
41
Network-Analyzer (VNA) and Figure 2-7 shows a general setup for RF measurement. Before the
device characterization, the system is calibrated with standard methods such as Short-OpenLoad-Through (SOLT) or Line-Reflect-Match (LRM) to move the reference plane to the end of
the probes. High frequency small signal from VNA is combined with DC bias generated by a
power supply in a bias tee and the mixed signal is applied to a device-under-test (DUT). Based
on the information about input and output signal from the device, S-parameters of the DUT are
defined at each bias and frequency. As the conventional transistor can be modeled as a two-port
network, a 2 x 2 S-parameter matrix can be obtained from the measurement. A typical device
layout has a large pad area for probe contact as shown in Figure 2-8(a), so that the measured Sparameters include the effects of the pad parasitic capacitance, resistance and inductance. A
procedure to remove these effects from the measured data is called as de-embedding. In general,
the difference before and after de-embedding is minimal in long channel devices due to the large
gate capacitance compared to the pad capacitance. However, in the short channel devices, the
S
S
S
D
G
D
S
S
S
(a)
(b)
(c)
Figure 2-8. Layouts for (a) device-under-test, (b) open, and (c) short pattern.
42
effect of the pad capacitance cannot be ignored and the de-embedding procedure is critical to
characterize the device RF performance accurately.
Cold/hot FET and open-short de-embedding are two most popular de-embedding methods. In
the cold/hot FET method [62] , the pad capacitance is measured from the device at pinch-off bias
condition (cold FET), while the parasitic inductance and resistance are obtained from the device
at ON-state (hot FET). Since the parasitic components are directly extracted from the actual test
device in this method, it does not need any additional pattern for the de-embedding process.
However, as the principle behind the method is based on the device modeling, it is exposed to
the potential error caused by discrepancy between the model and the actual device.
In the case of open-short de-embedding method [63], open/short patterns are required as shown
in Figure 2-8(b)-(c). The layout of the open pattern is same to that of the DUT except the lack of
the mesa region and gate electrode between source and drain. Thus, each pad is electrically
isolated. On the other hand, all the pads are connected with metal layer in the short pattern. The
measured S-parameters of the DUT and open/short patterns can be transformed to Y-parameters
and the data of the transistor without pad parasitic effects can be obtained with the following
equation [63].
Ytransistor = ((YUt
-
Yopen) 1
-
(Yshort -
Yopen
(2.1)
Although the method requires additional patterns for the de-embedding procedure, it can avoid
the potential error of cold/hot FET method by subtracting the measured pad effect directly from
the device data, rather than extracting each component through device modeling. In this work,
the open-short de-embedding method is used for high frequency characterization.
43
30
L = 1.3-pm
25-
T
S15
10 GHz
1h 2 1I
10
max
29 GHz
5VGS= -1.5
V
01
10
50
Frequency (GHz)
Figure 2-9. RF characteristics of AlGaN/GaN HEMT with gate length of 1.3-pm.
Current gain cutoff frequency (f 1 ) and maximum oscillation frequency (fmax) are the most
important figure of merits in the high frequency characteristics of RF transistors. The fT is based
on the short-circuit current gain (h21 ) which is the ratio of the small-signal output current (drain
current) to input current (gate current) with the output short-circuited. Generally, the magnitude
of the current gain rolls off with a slope of -10 dB/decade at high frequency range. The fl is the
frequency that the magnitude of the current gain becomes unity. In addition, from a device
physics point of view, fT is closely related to the electron transit time or electron charging time in
the device, so that it is the important tool to analyze the device speed.
fmax is defined as the frequency that the unilateral power gain (U) equals unity. The unilateral
power gain (U) is the power gain under the assumption of no feedback from the output to the
input (unilateralization) and it rolls off with the -20 dB/decade slope at high frequency range.
fmax is the highest frequency at which the device can be regarded as an active device, which is
very important in determining possible operating frequency as a power amplifier. If f 1 or fmax of
44
the device is higher than the maximum frequency of the microwave measurement system, they
are typically extracted from the extrapolation based on the slope of Ih2i12 (-20 dB/decade) and U
(-20 dB/decade).
Figure 2-9 shows the typical microwave characteristic of GaN HEMT with gate length of 1.3gm. Maximum fT of 10 GHz is measured at VDS= 5 V and VGS= -1.5 V, which is close to the bias
condition with maximum gm. At the same bias, fmax of 29 GHz is obtained and it is increased to
41 GHz with increasing VDS to 10 V. In general, the fT and fmax increase with scaling down the
gate length thanks to increase in the electron velocity and decrease of the gate capacitance.
More detailed analysis of the RF characteristics can be conducted with a small-signal
equivalent circuit model. When the device dimension is much smaller than the signal wave
length, the device can be modeled with lumped circuit elements such as capacitor and resistor.
Figure 2-10 shows a simple small-signal equivalent circuit model for transistor under saturation
regime. (Depending on the model requirements, more circuit parameters can be added to
represent second order effects such as gate leakage and non-quasi-static effect [64], [65].) In the
R
Cgd
G
Rd
-AA--
D
cgs
Rsd (1/sd)
Rs
gm.int exp(-jwr) - vgs
S
Figure 2-10. A simple small-signal equivalent circuit model for field-effect transistors.
45
model, a total gate capacitance is divided into gate-to-source capacitance (Cgs) and gate-to-drain
capacitance (Cgd). In the saturation regime, the charge distribution in the channel is asymmetric
and the Cgs becomes the main gate capacitance while Cgd gets close to zero. In the ideal long
channel device, the Cgs is about two-third of the capacitance calculated based on the parallel
plate capacitance model as shown in the following equation.
Cgls
2
23EbE
~Eb E2 '
Wfl - L'q
tb
.2)
where fb is relative permittivity of barrier between gate and channel, co is permittivity of vacuum,
Wg is gate width, Lg is gate length, and
tb
is the barrier thickness. (Considering quantum
mechanical effects, the Cgs can be smaller than the value calculated by the above equation due to
the finite separation of the centroid of the charge distribution to the barrier/channel interface [66]
and quantum capacitance caused by the finite density of states [67].) In actual devices, however,
gate fringing capacitances are included in both Cgs and Cgd, so that the extracted capacitances are
generally larger than the values estimated from the equation.
In the small signal equivalent circuit model, the current flow in the channel is modeled as a
parallel connection of a voltage-controlled current source and resistor. The voltage-controlled
current source represents the saturated drain current which only depends on the gate-to-source
voltage (vgs). - indicates the time delay between change of the gate voltage and drain current.
The resistor connected in parallel, which is called as output resistance (Rsd), accounts for the
increase of the drain current with increasing drain voltage in saturation regime, which can be
caused by channel length modulation or drain-induced barrier lowering (DIBL). Ri accounts for
the distributed channel resistance and non-quasi-static effect.
46
In addition to the device components explained above, there are parasitic resistances. R, and Rd
are parasitic source and drain resistances, respectively. Since the conventional GaN HEMTs have
non-self-aligned structures, both Rs and Rd are composed of the contact resistance and access
resistance. Rg is the gate resistance. Since the gate is made of metal such as Ni, Au and Pt, its
resistance is typically negligible in long gate length devices. However, in the short gate length
devices, the resistance is not negligible due to the small cross-sectional area of the gate electrode.
To reduce the gate resistance in the short gate length devices, a T-shaped gate structure is widely
used.
For accurate extraction of each circuit parameter from the measured S-parameters, several
methods have been proposed in the literature [62], [64], [65], [68], [69]. In this thesis, the
following procedure is mainly used for the extraction. First, after de-embedding the pad parasitic
by using open/short patterns [63], the parasitic resistances such as Rg, Rs and Rd are extracted at
ON-state bias condition (VGS > VT, VDS= 0 V) [62], [68], [70], [71]. After transforming the deembedded S-parameters to Z-parameters, the extracted parasitic resistances are subtracted from
the Z-parameters. Then, the Z-parameters are transformed to the Y-parameters. Once the Yparameters including only the intrinsic device part is obtained, all the small-signal circuit
parameters can be calculated analytically as shown in [65]. fT and fmax can be calculated based on
the small-signal equivalent circuit parameters as shown in the following equations [72].
fr =
27T(Cgs + Cgd)
1 +
9m.int
(Rs Rsd
+R)
fmax
(2.3)
+ 9m.intCgd(Rs + Rd)
fT
2 /RR
Rsd
+s R + ( 2 WfT)RgCgd
47
(2.4)
Chapter 3. Intrinsic Device Limits for Maximum GaN HEMT Speed
3.1. Introduction
Gate length scaling has been one of the most effective methods to increase the frequency
performance in most semiconductor field effect transistor (FET) technologies. As the gate length
scales down, the gate capacitance decreases linearly with the length. At the same time, the lateral
electric field in the channel increases at the given drain bias. In long channel devices where the
electron velocity is linearly dependent on the electric field, the device speed increases inversely
proportional to the square of the gate length because of the effect of the gate capacitance and
electron velocity. In short channel devices where the electron velocity is saturated due to the high
channel electric field, the speed increases inversely proportional to the gate length.
In GaN, the saturation electric field is about 100-200 kV/cm as shown in Figure 3-1 [73]. If
approximately constant channel electric field is assumed, the saturation of electron velocity
65 V/cm
140 k V/cm
4kV/cm
InN
GaAs
GaN
10
>
1
AIN
10
450kV/cm
100
1000
Electric Field [kV/cm]
Figure 3-1. The electron velocity and electric field characteristics of GaN and other semiconductors F731.
48
300
I
250
150-
50
100
0
50
150
100
200
250
L9 (nm)
Figure 3-2. fTs of AlGaN/GaN HEMTs reported in literatures.
becomes important as the gate length scales down to about quarter micron (250 nm) at drain bias
of 2-3 V. Since the channel electric field is not uniform in actual devices, the effect of the
electron velocity saturation is observed in devices with a gate length longer than 250 nm. Figure
3-2 shows current gain cutoff frequencies (fis) of sub-quarter micron gate length AlGaN/GaN
HEMTs reported in literatures as a function of the gate length. As explained in the previous
chapter,
fT
is one of the key parameters representing the device speed and the red dotted line in
the figure is the theoretical expectation of the
fT
in ideal GaN transistors. The reported
experimental data is well below the expected value and the gap is more significant as the devices
are scaled down. Also, the variation of the device speed gets larger especially in the shorter gate
length devices.
The saturation and variation in the device speed of deeply-scaled devices are the result of both
intrinsic and extrinsic effects. The intrinsic device includes the gate and channel right underneath
49
the gate, which is the core region of the Field-Effect Transistor (FET). The extrinsic device
includes all the components of the device except the intrinsic device. Chapter 3 will focus on the
analysis of the intrinsic device, while the extrinsic one will be analyzed in chapter 4. In this
chapter, important device parameters which determine the intrinsic device performance will be
discussed with a delay analysis. Based on this, critical issues in increasing the intrinsic device
speed will be studied and diverse approaches to overcome the challenges will be investigated.
3.2. Limiting factors in the intrinsic GaN transistor
3.2.1. Analysis tools to study device speed
In order to perform a systematic study on the device speed, good physical understanding of the
origin of device delay and a robust analysis methodology are necessary. By definition,
fT
is the
frequency at which the magnitude of the short-circuit small-signal current gain (h 21 1)becomes
unity. From a device physics point of view, it is the most appropriate parameter to study the
device speed since it is closely associated with the delay components in the device. The total
device delay (-1 ) can be obtained from fT with the following equation:
1
Tt =
(3.1)
The physical meaning of the total device delay can be studied from a few different perspectives,
including the total electron transit time or a total device charging time.
In order to investigate the total device delay in depth, a delay analysis based on the small-signal
equivalent circuit model is used in this thesis. This analysis method, first proposed in InGaAsbased HEMTs operating at very high frequency range above 600 GHz [74], holds the essence of
50
Cgd.ext
Gae
C
1Drain
IGt
Source
R,
Rd
gm nt
Figure 3-3. Small-signal equivalent circuit model based on the delay analysis method.
the device physics and a solid mathematical background. These advantages allow us to study the
device delay more systematically compared to other delay analysis methods. Figure 3-3 shows
the small-signal equivalent circuit model based on the delay analysis method, overlapped with
the GaN transistor structure. The key difference between this model and the conventional model
is that the total gate capacitance is separated into intrinsic gate capacitance and extrinsic gate
capacitance. The intrinsic gate capacitance is the capacitance resulting from the direct coupling
between the bottom of the gate electrode and intrinsic channel, while the extrinsic gate
capacitance includes all other capacitances. Based on the model, the total device delay can be
separated into intrinsic delay (Tint), extrinsic delay
(Text),
and parasitic delay (Trar) as shown in the
following equations.
_t
(3.2)
(Cgs + Cgd) + (Rs + Rd) - tCgd + (Cgs + Cgd) - gsd
9m.int
9m.int
(Cgs.int + Cgd.int)
9m.int
(Cgs.ext + Cgd.ext)
+
9m.int
+ R)+
= Tint + Text + Tpar
51
(Rs
d
+
'Cgd
(C
+ Cd)3 gs
g
9m.int
The intrinsic delay (Tit) is the main delay component in the intrinsic device, while the extrinsic
(Text)
and parasitic delay
are associated to the extrinsic device. This chapter identifies the
(rpar)
limiting factors in the intrinsic delay of GaN HEMTs and several new approaches are
investigated to overcome them.
3.2.2. Intrinsic delay
The intrinsic delay is the fundamental delay of field-effect transistors (FETs). Following an
incremental change of the gate voltage, the channel electrons are charged or discharged,
responding to the change of the electric field between gate and channel. The intrinsic delay can
be interpreted as the time required by electrons to respond to the gate voltage and
charge/discharge the intrinsic channel as shown in the following equation.
7 int
where
qint.channel
-
ia(-qint.channe)/aVlgs _ (Cgs.int + Cgd.int)
adaa
mit(3.3)
Olda/
Vgs
gm.int
is the charge in the intrinsic channel and id is the drain current.
In order to reduce the intrinsic delay, the intrinsic gate capacitances (Cgs.int, Cgd.int) should be
minimized
while
maximizing
the
intrinsic
transconductance
(gm.int).
The
intrinsic
transconductance also influences the extrinsic and parasitic delays as shown in equation (3.2),
but it is mainly discussed in this section because its value is determined by the relation between
gate and intrinsic channel. In scaled devices, these two parameters, intrinsic gate capacitance and
transconductance, are closely linked as shown in the following equations.
Cgs.int + Cgd.int = a, Cg.unit - W - Lg
52
(3.4)
9
m.int = fl
Cg.unit *
(3.5)
-V'sat
where Cg.unit is unit area gate capacitance, Lg is gate length, Wg is gate width,
velocity, a is a factor related to the charge distribution in the channel, and
Vsat
is saturation
p is a factor related to
the degree of the velocity saturation and gate modulation efficiency. The Cg.unit is the
combination of a top barrier capacitance, electron wave function centroid capacitance, and
quantum capacitance [67]. The a factor is close to 2/3 in the saturation regime due to asymmetric
channel charge distribution. In the case of P, it increases and becomes close to unity with
increasing the number of channel electrons achieving velocity saturation. That is, the increase of
the lateral electric field in the channel can increase P. However, a too high lateral electric field
can also lower the P by degrading the gate modulation efficiency.
Based on these relations, there are two important approaches to minimize the intrinsic delay.
First, the gate length scaling can increase the intrinsic transconductance by increasing the
channel electric field as well as decreasing the intrinsic gate capacitance. Second, maintaining
good electrostatics in short gate length devices can prevent the decrease of the intrinsic
transconductance caused by the degradation of the gate modulation efficiency.
3.3. Gate length scaling
3.3.1. Electron-beam lithography technology
As explained in the previous section, gate length scaling is one of the most effective approaches
to reduce the intrinsic delay and it has been the main strategy to improve device speed in the
initial development of GaN transistors. Conventional gate technology for RF devices has been
based on T-shape (or mushroom-shape) gate structure to maintain a low gate resistance even in
53
(a)
(b)
(c)
Figure 3-4. (a) T-gate with about 50 nm foot length. (b) Structural instability of T-gate with sub-50 nm
foot length. (c) Misalignment between gate head and foot.
short gate length geometries as shown in Figure 3-4(a). Although the T-shape gate technology is
indispensable for commercial RF applications, it can degrade device frequency performance and
hide important device physics needed to fully understand device behavior. First, structural
instability and process complexity caused by the combination of a large gate head and a short
foot makes it challenging to scale down the gate length below 50 nm as shown in Figure 3-4(b).
Also, misalignment errors between the head and the foot make it difficult to get a fair
comparison between devices as shown in Figure 3-4(c). Moreover, it is not easy to measure the
actual gate length accurately in the T-gate structure due to the large head. Scanning electron
microscope (SEM) is generally used on a tilted sample, but the measurement can be affected by
the tilt angle and sample position. Cross-sectional transmission electron microscope (TEM) can
solve the problem, but it is an expensive, slow and destructive method.
In order to avoid these issues, a deep-submicron rectangular-shape gate process was developed
in this project. Although the rectangular shape gate causes a high gate resistance, this high
resistance does not influence the device speed measured by fr. Also, the proposed rectangular
gate simplifies the fabrication process and gate length measurement, which is favorable for
research purposes. In this project, double layer and single layer electron-beam lithography
54
Metal
MMA
GaN
MMA
MMA
GaN
G
GaN
(a)
GaN
GaN
GaN
(b)
Figure 3-5. Process flows for (a) double layer and (b) single layer electron-beam lithography.
technologies were developed to achieve sub-100 nm rectangular shape gates. In the double layer
process, polymethyl methacrylate (PMMA) and methyl methacrylate (MMA) are used as shown
in Figure 3-5(a). After electron-beam exposure, the top PMMA layer is developed with a diluted
methyl isobutyl ketone (MIBK) solution, which defines the gate length. Then, the bottom MMA
layer is developed with a diluted Methanol solution to make an undercut. Thanks to the undercut
made of the bottom MMA layer, the lift-off of a metal-evaporated layer quite straightforward in
the double layer process. Unfortunately, the thick electron-beam resist stack required by the
double layer process and the spread of the evaporated metal in the undercut region make it
challenging to shrink the gate length below 50 nm.
55
To solve the problems associated with the double layer process, a single layer process was
developed for the fabrication of sub-50 nm gate length devices. Instead of the PMMA/MMA ebeam resist stack, a single PMMA layer is coated on the sample as shown in Figure 3-5(b).
During the electron-beam exposure, the electron scattering in the PMMA layer and at the
interface between PMMA and the top barrier can result in the reverse slope in the developed
PMMA pattern, which makes it possible to do a successful lift-off with the single layer electronbeam resist. However, as the lift-off in the single layer process is more challenging than the
double layer process, it requires more accurate dose optimization and vertical metal evaporation.
3.3.2. Issues in deeply-scaled AlGaN/GaN HEMTs
Based on the developed technology for gate length scaling, short channel AlGaN/GaN HEMTs
are fabricated. The wafer used in this study was grown on a SiC substrate and the heterostructure
consisted of 23 nm Alo. 23 Gao. 7 7N top barrier, 1 nm AlN, and GaN buffer. The fabrication process
.0.6
1.5
E
-Lg= 160 nm
-- L =30 nm
E
3V
~L9= 160 nm
-- L =30 nm
VDS=
VGS= -8 ~ 0 V
E
'0
-- 1
E
0
00
0
2
.4-
6
V DS (V)
4
8
8
10
-6
-2
-4
VGS (V)
0
(b)
(a)
Figure 3-6. Comparison of DC (a) output and (b) transfer characteristics of AlGaN/GaN HEMTs with
gate length of 160 nm and 30 nm.
56
300
50
Open: L= 30 nm
4
250
Filled: L= 160 nm
3
+
:M
~200
-3
x
I 30 -N
150
98 GH
o
-
-
S20--
1
171 GHz
10
-
5
0
1
-
50
0
10
100200
Frequency (GHz)
(a)
50
100 150
L (nm)
200
250
(b)
Figure 3-7. (a) RF characteristics of 160 nm and 30 nm gate length AlGaN/GaN HEMTs and (b)
comparison of the fTs of AlGaN/GaN HEMTs with literature data.
follows the standard process described in the chapter 2 and the single layer electron-beam
process explained in the previous section. Figure 3-6 shows the DC characteristics of
AlGaN/GaN HEMTs with the gate length of 160 nm and 30 nm. In 160 nm gate length device,
the effective channel control by the gate provides excellent DC characteristics such as high
transconductance, low output conductance and good pinch-off at high drain bias. On the other
hand, the serious degradation of the gate modulation in the 30 nm gate length devices results in
significant increase of the output conductance, incomplete pinch-off, and large negative shift of
the threshold voltage. Especially, the maximum transconductance, which is closely related to the
intrinsic delay, is decreased from 290 mS/mm to 215 mS/mm.
The degradation of DC characteristics of the short channel device is also reflected in RF
performance. Figure 3-7 (a) shows the microwave characteristics of 160 nm and 30 nm gate
length devices measured with Agilent N5430A network analyzer. The system was calibrated
57
with an off-wafer LRRM calibration standard and on-wafer open and short patterns were used to
de-embed parasitic pad capacitances and inductances from the measured S-parameters [63]. The
160 nm gate length device shows a maximum fr of 98 GHz, which gives a fairly large fr-Lg
product of 15.7 GHz-pm. Also, it is very close to the best frequency performance reported in
literature for that gate length range as shown in Figure 3-7 (b). In contrast, the maximum
fT
of 30
nm gate length device is limited in 171 GHz, resulting in a very low fr-Lg product of 5.13
GHz-pm. Figure 3-7(b) shows the device speed is not only well below theoretical expectation,
but it is even below experimental data in longer gate length devices. These results clearly show
that simply scaling gate length does not reduce the intrinsic delay effectively in such a short gate
length range.
As discussed in section 3.2.2, the intrinsic delay is not only affected by the gate length (Lg), but
also gate modulation efficiency (p). Figure 3-8 shows the fT-Lg product of AlGaN/GaN HEMTs
20
188 nm
160 nm*
-15
-1nm'
N
II
30nm
5
\
35nm
30Onm
If
Ti
Thi* experiment
014
* Literatures
V
0
2
4
6
8
10
12
14
L g tb
Figure 3-8. fr-Lg product of AlGaN/GaN HEMTs in literatures and this experiment as a function of
aspect ratio (L,/tb).
58
in both literatures and this experiment as a function of an aspect ratio (Lg/tb, where Lg is gate
length and
tb
is a total top barrier thickness.) Since the aspect ratio is the efficient measure of the
gate electrostatic, this plot can show the impact of the gate modulation efficiency on the device
speed. In the data from both literatures and this experiment, significant decrease of the fT-Lg
product is observed in the devices with the aspect ratio below about 5. (e.g. The aspect ratio of
30 nm gate length device in this experiment is only 1.2.) This result shows that it is critical to
suppress degradation of the gate modulation efficiency for effective scaling of the intrinsic delay
in the short channel devices.
3.4. Top barrier engineering
3.4.1. Gate modulation efficiency
As shown in the previous section, maintaining the high gate modulation efficiency with scaling
the gate length is important to achieve minimum intrinsic delay. For proper operation of the
field-effect transistors (FETs), the vertical electric field from the gate should be much larger than
the lateral electric field across the channel. Under these conditions, the electron density in the
channel is determined by the gate voltage, which provides effective modulation of the drain
current. However, as the gate length scales down, the increased lateral electric field diminishes
the effect of the vertical electric field and the gate starts to lose its controllability of the drain
current. In order to alleviate the degradation of the gate modulation efficiency in the short gate
length devices, the vertical electric field should be enhanced along with the increased lateral
electric field caused by gate length scaling. In the following section, InAlN/GaN heterostructures
are introduced to the deeply-scaled GaN HEMTs, as one of the solutions to increase the vertical
electric field.
59
3.4.2. InAIN/GaN heterostructure
In GaN HEMTs, a top barrier layer has two main roles: 1) It creates a polarization charge
discontinuity at the interface with GaN, which induces the 2-DEG; 2) It isolates the gate
electrode from the channel, similar to the gate oxide in Si MOSFETs. The most conventional top
barrier material is AlxGa.xN (x < 0.35) and its thickness is generally about 20-30 nm to provide
enough charges by inducing a large polarization field. However, in devices with sub-100 nm gate
length, this barrier thickness is too thick to maintain good electrostatics, which results in serious
degradation of the gate controllability as explained in the previous section.
One of the solutions is to thin down the top barrier thickness to increase the vertical electric
field between gate and channel. However, scaling the top barrier thickness reduces the 2-DEG
charge density, which increases the source/drain access resistances and decreases the current
drivability. To avoid this problem, a gate recess process can be used with Cl 2 plasma-based dry
etching [38], [75], [76], but it is very challenging to get uniform recess profile when the gate
length is very short. In addition, the damage under the gate, induced by the plasma etching, can
cause the degradation of the electron transport property in the channel [77]-[79].
In order to solve these issues, new barrier materials such as high Al composition AlxGa 1 xN (x >
0.35) [36], [37], [80], AlN [81]-[83] and InAlN [84]-[86] have been proposed. These materials
have much higher polarization field compared to the conventional AlxGaixN (x < 0.35), so that
they can provide higher sheet charge density with thinner barrier thickness. Especially, InAlN
with 17 % Indium composition can be lattice-matched to GaN as shown in Figure 3-9(a) [84],
which reduces strain resulting from the lattice-mismatch and provides the potential for better
reliability than other heterostructures. Also, device operation at temperatures near 1000 'C has
also been demonstrated, which shows the high thermal stability [86]. In addition, although there
60
7
9-
E
3.0-
InO. ,A10 .83NIGaN
A0.3GacjN/GaN
N
IA
m.1AIN1
-2.0-
AIGaN
04
nAIN
*1.5
4.
.-
M
GaN
1.0-
nGaN
*
U
InN
0.5-
Experiments
23A
35
Lattice constant, at 300 K (Angstrom)
32
33
34
NV
36
0.0-
0
3
6
9
12
15
18 21
24
27
30
33
Barrier thickness (nm)
(a)
(b)
Figure 3-9. (a) Comparison of lattice constant and energy gap between Ino. 17Ao.83N and other nitride
alloys [84]. (b) Comparison of simulated 2-DEG sheet charge density between InAiN/GaN and
AlGaN/GaN heterostructure [87].
is almost no piezoelectric strain in the lattice-matched InAlN/GaN heterostructure, the sheet
charge density is still much larger than AlGaN/GaN heterostructure due to the high spontaneous
polarization of InAlN layer as shown in Figure 3-9(b) [87]. Thanks to these advantages,
InAlN/GaN HEMTs have attracted significant attention as an alternative to the conventional
AlGaN/GaN HEMTs and several promising results have been reported [87]-[91]. In this study,
InAlN/GaN heterostructure is combined with sub-50 nm gate process to push the maximum
frequency of GaN HEMTs by suppressing the degradation of the gate modulation efficiency at
short channel dimensions.
3.4.3. Device fabrication
The lattice-matched Ino. 17A10.83N/GaN heterostructure used for this study was grown on a SiC
substrate by metal-organic chemical vapor deposition (MOCVD). The thickness of the InAlN
barrier and the AlN interlayer was 4.5 nm and 1.0 nm, respectively. Hall measurements
61
Plasma oxide 1
SD
A1203
GaN
InAIN/AN
GaN
SiC substrate
(a)
(b)
Figure 3-10. (a) Cross-sectional schematic image of InAIN/GaN HEMT. (b) Cross-sectional TEM image
of 30 nm gate length device.
conducted in a van der Pauw structure after surface passivation with a 10 nm A12 0
showed a two-dimensional charge density (2-DEG) of 1.5
1670 cm 2 VI sI
,
x
3
dielectric
1013 cm- 2, an electron mobility of
and a sheet resistance of 250 fj/n.
Figure 3-10(a) shows the cross-sectional schematic image of the fabricated InAIN/GaN HEMT.
The device fabrication process began with mesa isolation using C12/BCl
3
plasma-based dry
etching. Then, ohmic contacts were formed by depositing a Ti/Al/Ni/Au metal stack followed by
annealing at 850 'C for 30 s in a N 2 atmosphere. The contact resistance measured in transmission
line measurement (TLM) was 0.6-0.7 Q.mm and the source-to-drain distance was 1.3 tm. After
the ohmic anneal, the surface of the InAlN was subjected to an oxygen plasma treatment to
reduce the gate leakage by forming a thin oxide layer. Electron-beam lithography was used to
define rectangular shape gate in the middle of the source and drain based on the single PMMA
layer process described in Figure 3-5(b). With an optimized exposure condition, a minimum gate
length of 30 nm was achieved and the gate metallization consisted on a Ni(10 nm)/Au(40 nm)
62
2
-
Lg= 30 nm
L= 30 nm
1.5
.
-
VS3
E
0.4
0.5
0.2
1)
2
4
6
VD (V)
8
005
10
-4
-3
-2
VGS (V)
-1
0
(b)
(a)
Figure 3-11. DC (a) output and (b) transfer characteristics of 30 nm gate length InAIN/GaN HEMT.
metal stack as shown in Figure 3-10(b). After gate metallization, the devices were passivated
with a 10 nm A12 0 3 layer deposited in 250 'C by atomic layer deposition (ALD) [57].
3.4.4. DC characteristics
Figure 3-11 shows DC output and transfer characteristics of InAIN/GaN HEMT with 30-nm
gate length. A maximum drain current of 1.57 A/mm is obtained at VGS = 1 V, and the peak
extrinsic transconductance
is 467 mS/mm at VDS = 3 V. Compared to the conventional
AlGaN/GaN HEMTs, the top barrier is thinner by about four times, but the maximum current is
higher thanks to the high polarization field in InAlN barrier. The extrinsic transconductance is
lower than the expected value due to the high contact resistance (0.6-0.7 Q-mm). The increase of
the aspect ratio with InAlN/GaN heterostructure effectively alleviates the degradation of the gate
controllability even in the 30 nm gate length range, which is clearly reflected in the device
characteristics in both subthreshold and saturation regimes. Figure 3-12 shows the comparison of
63
10
800
2
* InAIN/GaN (tb= 6.5 nm)
* AIGaN/GaN (tb= 25 nm)
-
InAIN/GaN (tb= 6.5 nm)
AIGaN/GaN (tb= 25 nm)
10
600
E
E
-400
10
-2
10
200
VDs= 1, 5 V
6L = 30-nm
010
0
50
100 150 200 250
L9 (nm)
-10
-8
-4
-6
VGS (V)
-2
0
(b)
(a)
Figure 3-12. Comparison of the subthreshold characteristics of InAIN/GaN and AlGaN/GaN HEMTs. (a)
DIBL as a function of gate length. DIBL is extracted in VDS=I and 5 V at ID=I mA/mm. (b)
Subthreshold characteristics of 30 nm gate length devices at VDS= 1 and 5 V.
the subthreshold characteristics of InAIN/GaN HEMTs and AlGaN/GaN HEMTs. Draininduced-barrier-lowering (DIBL) is reduced by more than 50 % in InAIN/GaN HEMTs and its
effect becomes larger in the shorter gate length devices. Also, the increase of the subthreshold
swing (SS) at high drain bias is suppressed as shown in Figure 3-12(b). The improvement in the
device performance at the saturation regime is more critical for the high speed operation. Figure
3-13 shows comparison of the maximum intrinsic transconductance as a function of the gate
length in InAIN/GaN and AlGaN/GaN HEMTs. The intrinsic transconductance is estimated
based on the DC extrinsic transconductance and it is normalized by the maximum estimated
intrinsic delay in each device to compensate the difference cause by the different top barrier
thickness. In the AlGaN/GaN HEMTs, the normalized intrinsic transconductance starts to
decrease as the gate length scales down below about 100 nm and the degradation becomes
64
1.2
InAIN/GaN (tb= 6.5 nm)
C
-- AIGaN/GaN
0.8 -
(tb=
25 nm)-
-
E 1000
o0
0
......
0
00100
VDS=
0
50
200
L 9(nm)
3V
100
150
L9 (nm)
200
250
Figure 3-13. Normalized intrinsic transconductance as a function of the gate length in InAIN/GaN and
AlGaN/GaN HEMTs. The inset shows the intrinsic transconductance before normalization.
serious below 50 nm. In the 30 nm gate length device, about 40 % decrease compared to the
maximum value is observed. In contrast, the normalized intrinsic transconductance continues to
increase up to about 40 nm gate length range in InALN/GaN HEMTs and less than 10 % decrease
is observed in the 30 nm gate length device. These results show key advantages of InAlN/GaN
HEMTs against AlGaN/GaN HEMTs to push the speed of the deeply-scaled devices.
In spite of the significant improvement in the performance at the subthreshold and active bias
regime, the pinch-off at high drain bias is not completely solved even in InAlN/GaN HEMTs. An
incomplete pinch-off is observed in the 30 nm gate length range as shown in Figure 3-1 1(a). A
heterostructure with less than 6 nm top barrier thickness can be used to improve the pinch-off,
however excessive top barrier scaling causes significant increase of the sheet resistance even in
65
300
250
0
*
0
60
InAIN/GaN (tb= 6.5 nm)
0.2
Lg= 30-nm
1lslope: 250 GHz
50
AIGaN/GaN (tb=25nm)
Ih
21,
200~...0
E 0.05
3440
20001-20
CD
150
30
100
Frequency (G z)
-
(U
-
5
IMAG
20
245 GHz
50
00
50
100 150
L (nm)
100
0
VGS= -1.7V~
100
Frequency (GHz)
2
(b)
(a)
Figure 3-14. (a) Maximum fr as a function of the gate length in InAiN/GaN and ALGaN/GaN HEMTs.
(b) RF characteristics of 30 nm gate length InAiN/GaN HEMT.
InAIN/GaN heterostructure. It is therefore necessary to develop additional approaches to
improve the transistor pinch-off, which will 2be1discussed
1
in 2later1 sections of this chapter.
3.4.5. RF characteristics
The RF performance of the transistors was characterized from 100 MHz to 45 GHz by using an
Agilent N5250C network analyzer. The system was calibrated with an off-wafer Line Reflect
Match (LRM\)
calibration standard. The measured S-parameters were de-embedded using on-
wafer open and short test structures [631. Figure 3-14(a) shows the comparison of the maximum
f1 obtained from InAlN/GaN HEMTs and AlGaN/GaN HEMTs. In the devices with gate length
above 100-150 nm, AlGaN/GaN HEMTs show slightly higher fr than InAlN/GaN HEMTs
thanks to its higher mobility (2240 cm2 V
s vs 1670 cm2 V s') and lower contact resistance
(0.4-0.5 Q-mm vs 0.6-0.7 G-mm). However, as the gate length scales down to deep sub-lO0nm
66
range, InAIN/GaN HEMTs starts to outperform AlGaN/GaN HEMTs thanks to effective
suppression of degradation of the gate modulation efficiency as shown in Figure 3-13.
Figure 3-14(b) shows the RF characteristics of the 30 nm gate length InAIN/GaN HEMTs at the
bias condition for maximum fT (VDS
3.5 V and VGs = -1.7 V). Through extrapolation of 1h2 112
with a -20 dB/dec slope, an fT of 245 GHz is obtained [92]. Gummel's method is also applied as
an alternative way for extraction [93] and it yields a very similar
fT
value of 250 GHz. This
device speed is higher than any other GaN HEMTs that have been demonstrated previously.
Considering that it is initial stage of this research and the process condition such as ohmic
contact formation is not optimized, these results show a great potential of InAlN/GaN
heterostructure as a platform for the deeply-scaled devices.
3.5. Channel charge confinement
3.5.1. Pinch-off and subthreshold characteristics
It was shown in the previous section that InAIN/GaN heterostructures can effectively suppress
the degradation of the intrinsic transconductance in the deeply-scaled devices. However, in the
30 nm gate length devices, incomplete pinch-off was still observed at high drain bias as shown in
Figure 3-11 and DIBL was also relatively large (> 300 mV/V). Although the pinch-off
characteristic is not directly related to the device speed measured in active bias condition, a good
pinch-off characteristic is critical for high efficiency large signal operation. In addition, the
DIBL in the subthreshold characteristic can indirectly impact the device speed through the output
resistance because threshold voltage shift caused by the DIBL is one of the main origins of the
output resistance in the short channel devices. Therefore, the intrinsic device needs to provide the
good channel controllability not only in the active bias condition, but also in subthreshold and
67
Active regime
AIN
InAIN
AIN
2-DEG
Pinch-off regime
InAIN
-------------------- Ef
------------------------
GaN
Ef
GaN
Charge confinement
with band bending
No charge confinement
(a)
(b)
Figure 3-15. Energy band structure of InAIN/GaN HEMT in (a) active and (b) pinch-off regimes.
off-state bias conditions. In general, to maintain the good electrostatics in subthreshold or off-
state regime, stronger channel charge control is required than in the active regime because there
is almost no charge confinement through the bending in the conduction band in the channel as
shown in Figure 3-15. To improve channel charge confinement, two different approaches are
investigated with combination of the InAlN/GaN heterostructure in this section.
3.5.2. InAIN/GaN HEMTs with AlGaN back barrier
3.5.2.1. AlGaN back barrier heterostructure
As the first approach to improve the charge confinement, an AlGaN back barrier structure can
be used as shown in Figure 3-16(a). Unlike the conventional structure, the GaN channel is grown
on the AlGaN buffer, so the GaN channel layer suffers from compressive strain. The strain in the
GaN layer induces the polarization field and it raises the conduction band of the GaN layer as
shown in Figure 3-16(b). The electric field in the GaN layer pushes the electrons in the channel
to the top barrier interface and improves the charge confinement. The degree of the charge
68
4
InAIN
SiC
sic
GaN
* AINA~
GaN
2
la
- - - -
0 ---+GInAIN
- .....
-...
.
Ef
A
+UAIGaN
4
+CJGaN
C-,
Raised GaN energy band
-4
4-CyGaN
0
0
10
-CAIGaN
InAIN
30
20
Depth (nm)
40
50
(b)
(a)
Figure 3-16. (a) Polarization charge distribution and (b) energy band structure simulation of InAIN/GaN
heterostructure with AlGaN back barrier.
A.
MAIN
2
/
AIN
GaN
AlGaN
0[
Aluminum composition: 0 % -+12 %
C)
a)
I-
w -2
-4
0
10
30
20
Depth (nm)
40
50
Figure 3-17. Simulation result of the band structure of InAIN/GaN heterostructure with AlGaN back
barrier depending on the Aluminum composition.
confinement can be controlled through Aluminum composition of the AlGaN back barrier.
Figure 3-17 shows simulation results on how the energy band structure varies with the
Aluminum composition in AlGaN back barrier structures. With higher Aluminum composition,
69
the polarization charge induced at the interface between GaN and AlGaN layers is increased,
which increases the electric field in the channel. However, the high Aluminum composition
increases the lattice-mismatch between two layers, so that the dislocation or trap formation can
become serious. In addition, increase in a thermal resistance of the AlGaN buffer is also critical
issue in the AlGaN back barrier with high Aluminum composition. Moreover, the raised GaN
conduction band results in the decrease of the 2-DEG charge density. Because of the trade-off, it
is important to choose the Aluminum composition in this technology carefully.
The AlGaN back barrier structure was first applied to conventional AlGaN/GaN HEMTs with
fairly thick top barrier thickness (40 nm) and relatively long gate length devices (0.15 pm) [94].
The strong charge confinement with the back barrier structure successfully improves the pinchoff characteristic by redeeming the thick AlGaN top barrier. However, introduction of new
heterostructures with sub-10 nm top barrier such as high Al composition AlxGai-N (x>0.35),
AIN, and InAlN makes it possible to achieve the similar performance without additional electron
confinement from the back barrier structure in this gate length range (< 0.15 pm). Thus, no
research on the AlGaN back barrier structure has been conducted in these heterostructures.
However, as shown in Figure 3-11(a), once the gate length is scaled down to deep sub-50 nm
range, the thin top barrier is not enough to effectively suppress the degradation of pinch-off
characteristics at high drain voltage. Moreover, there is a limit in the top barrier scaling because
excessive scaling can result in several issues such as the significant decrease of 2-DEG density
[87] and the increase of the sensitivity to the surface states. In this work, InAlN/GaN
heterostructure and AlGaN back barrier are combined to relieve the requirement of the top
barrier scaling and improve pinch-off and subthreshold characteristics in the deeply-scaled
devices [95].
70
A1203 (10 nm)
GA1203
nm)
Plasma oxide
(1 0
Plasma oxide 1 nm
n
GaN (21 nm)
GaN
SiC substrate
SiC substrate
(b)
(a)
Figure 3-18. Cross-sectional schematic images of (a) control InAIN/GaN heterostructure and (b)
InAIN/GaN heterostructure with AlGaN back barrier.
3.5.2.2. Device fabrication
For a systematic study on the impact of the AlGaN back barrier, two lattice-matched
Ino. 17A10.83N/GaN heterostructures with and without AlGaN back barrier were grown on SiC
substrates by metal-organic chemical vapor deposition as shown in Figure 3-18. The thickness of
the InAlN barrier and AIN interlayer in both samples were 5.0 and 1.0 nm, respectively. One
wafer had 0.8 pm Alo.o4 Gao.96 N back barrier with 21.0 nm GaN channel layer, while the other
one had a GaN buffer only. 4 %Aluminum composition was chosen for the AlGaN back barrier
to get reasonable charge confinement effect with minimal side effects discussed in the previous
section. A two-dimensional charge density (2-DEG) of 1.1 x 1013 cm-2, an electron mobility of
1635 cm2 V-1 s- , and a sheet resistance of 310 Q/o were measured in the wafer with the AlGaN
back barrier through Hall measurements. The sample without the back barrier showed a total 2DEG charge density of 1.7 x 101 cm-2 with a mobility of 1369 cm2 V-1 s~1 and a sheet resistance
of 260 Q/o. The lower 2-DEG charge density in the wafer with the back barrier was caused by
the effect of the raised GaN conduction band.
71
Transistor fabrication was performed on the two wafers at the same time. First, Cl 2/BC
3
plasma-based dry etching was used for mesa isolation. Then, a Ti/Al/Ni/Au ohmic metal stack
was deposited followed by annealing at 830 'C for 30 s in a N2 atmosphere. A contact resistance
of about 0.41 ± 0.04 Q-mm was obtained in both samples. After the ohmic contact process,
surface oxygen plasma was applied. Then, electron-beam lithography was used for submicrometer gates on a double layer resist stack made of polymethyl methacrylate (PMMA) and
methyl methacryllate (MMA). Rectangular shape gates with lengths in the 60 to 250 nm range
were then formed by depositing a Ni(10 nm)/Au(70 nm) metallization. Following a buffer oxide
etch (BOE) surface cleaning, 10 nm A12 0 3 passivation layer was deposited through atomic layer
deposition (ALD).
3.5.2.3. Impact of AlGaN back barrier
Figure 3-19 shows the output and transfer characteristi cs of the fabricated devices with 65-nm
gate length on the two heterostructures. A drain current of 1.3 A/mm is obtained at
2.5
2
Lg= 65-nm
VGS= -4
V=-4
-
1
- w/o back barrier
v
1
-- w back barrier
E,)
-1
E 1.5
0. 8
VGS=
1 V in
Lg= 65-nm
VDS=
5V
------
E 0. 6 w/o back barrier
0)
0. 4
1
0
0. 2
0.5
w back barrier
a
'OI
2
4
6
VDS (V)
8
10
-5
-4
-3
-2
VGS (V)
-1
0
(b)
(a)
Figure 3-19. Comparison of DC (a) output and (b) transfer characteristics of 65-nm gate length
InAlN/GaN HEMTs with and without AlGaN back barrier.
72
1 n2
2UU
-U- wlo back barrier
w back barrier
U wlo back barrier
0
0 w back barrier
10
,150
E
-1
50
10
0
106
0 -
-6
50 100 150 200 250 300
VDS= 1, 9 V
6L =65-nm
-4
-2
L9 (nm)
VGS (V)
(a)
(b)
0
Figure 3-20. Comparison of subthreshold characteristics of InAIN/GaN HEMTs with and without AlGaN
back barrier. (a) DIBL as a function of the gate length, (b) Subthreshold characteristics of 65-nm gate
length devices.
the device with the back-barrier, about 28 % lower than that of the conventional device (1.8
A/mm at VGS= 1 V). The smaller drain current in the device with the back-barrier mainly results
from the lower sheet charge density and subsequent higher threshold voltage. Due to the higher
access resistance, the device with the back barrier shows an extrinsic transconductance of 540
mS/mm, 9 % lower than that of the conventional device (590 mS/mm). However, increase of the
charge confinement reduces the output conductance significantly in the device with the backbarrier. The improvement is also reflected in the subthreshold characteristics. As shown in
Figure 3-20(a), in the devices with gate length above 100 nm, the DIBL is less than 50 mV/V in
both samples, which shows that the thin InAlN top barrier alone is enough to control the short
channel effects. However, as the gate length scales down below 100 nm, the DIBL begins to
increase rapidly in the conventional devices while it stays near 50-60 mV/V in the devices with
the back barrier. The smaller DIBL in the short channel devices with back barrier partially results
from the suppression of increase of SS at high drain bias as shown in Figure 3-20(b).
73
1.5
1
L,=27nm
L =27nm
E 0.8 V= 3V
VGS=-4~1V
EO.6.
E
10
n8
E
0
(a)
2
4
6
VDS (V)
8
10
04
-3
-2
VG
-1
0
(V)
(c)
(b)
Figure 3-21. (a) Cross-sectional TEM image of 27 nm gate length device. DC (b) output and (c) transfer
characteristics of the device.
3.5.2.4. Deeply-scaled InAIN/GaN HEMT with AlGaN back barrier
Based on the results of the study on the impact of AlGaN back barrier effect, sub-30 nm gate
length InAIN/GaN HEMTs with AlGaN back barrier were demonstrated [96]. The basic
fabrication process was very similar to the process described above except for the gate e-beam
lithography step. In order to shrink the gate length, a single PMMA layer was used instead of
PMMA/MMA double layer. Figure 3-21 shows DC characteristics and cross-sectional TEM
image of the fabricated device with the gate length of about 27 nm. The combination of the thin
InAlN top barrier and AlGaN back barrier provides excellent pinch-off characteristic for such a
short gate length range. Figure 3-22 shows the comparison of subthreshold and pinch-off
characteristic of the 27-30 nm gate length devices with and without back barrier. The device with
back barrier shows smaller SS and DIBL compared to the device without back barrier in spite of
slightly thicker top barrier thickness (7.0 nm vs 6.5 nm) and shorter gate length (27 nm vs 30
nm). In addition, the punch-through current at high drain bias is well suppressed in the device
with the back barrier, while it becomes significant in the device without the back barrier. Due to
74
slightly higher contact resistance (R,= 0.5-0.6 0-mm), the maximum g. (460 mS/mm) is lower
than the devices shown in Figure 3-19. However, thanks to the combination of 27 nm gate length
with well-controlled short channel effect, the device has a maximum fr of 270 GHz as shown in
Figure 3-23.
10
-
without back barrie
-+-
with back barrier
-
E
E
VDS= 5V
-
-
without back barrier
+ with back barrier
0.06
0
E
E 10 -2
-
0.08
102
0.0
0.0 2
10
VDS 1 V
10
-6
-6
Lg=
Lg= 27-30 nm
-5
-4
-3
-0.0
-1 0
-2
27-30 nm
60
2
VGS (V)
(a)
VGS=
-5 - -4 V---
4
6
VDS (V)
8
10
(b)
Figure 3-22. Comparison of (a) subthreshold and (b) pinch-off characteristics of the 30-nm gate length
range devices with and without back barrier.
60
L= 27 nm
5040 30
12
U
020
MSG
/MAG
100
i
1h21
270 GHz
VDS = 3 V
VGS = -2.16V
0
100
300
Frequency (GHz)
Figure 3-23. RF characteristics of 27 nm gate length InAIN/GaN HEMT with AlGaN back barrier.
75
3.5.3. InAIN/GaN HEMTs with vertical channel scaling
3.5.3.1. Heterostructure for vertical channel scaling
Vertical GaN channel scaling can be another approach to achieve the 2-DEG charge
confinement. In order to study the impact of the GaN channel thickness on the device
performance, we used an InAlN/GaN transistor structure with an InGaN back barrier. The InGaN
layer grown on the GaN buffer induces polarization charges at the interface between InGaN and
GaN which form a polarization discontinuity [35], [97]. The polarization charges induce the
electric field in the InGaN layer and provide an effective conduction band offset as shown in
Figure 3-24. One of the main differences with the AlGaN back barrier structure is that the 2DEG charge confinement is achieved not by polarization-induced electric field in GaN channel,
but by the band offset effect resulting from the polarization field in InGaN layer. Thus, the
distance between the top barrier and GaN/InGaN interface, which can be called as GaN channel
thickness (tGaN), determines the degree of confinement.
InGaN
4
GaN
channel
GaN
InAIN
sic
buffer
li
/-
2
na
kAIN
' 'Gnaa
-1- - - - - - - -- - - - - - -
+InGaGaN
I
I
OGGaN
Polarization field in InGaN
ied
IRd4
YnAIN
U0GaN
+
W
__
__N
0
Ua
~CynGaN
-UInAIN
(a)
10
20
30
Depth (nm)
40
50
(b)
Figure 3-24. (a) Polarization charge distribution and (b) energy band structure of Ino. 17A10.83N/GaN
heterostructure with lno.15 Gao.85N back barrier.
76
0
10
20
30
40
50
0
5
10
is
2
(b)
(a)
Figure 3-25. Cross-sectional TEM images of heterostructures with (a) 26 nm GaN channel and (b) 3.4
nm GaN channel.
For this study, four wafers with different GaN channel thickness between 3.4 nm and 26 nm
were used [98]. The wafers were grown on SiC substrates by metal-organic chemical vapor
deposition (MOCVD). The GaN channel layers with the different thickness were grown between
top barrier and InGaN back barrier structure grown on top of a thick GaN buffer. The Indium
composition of the InGaN layer was about 10-15 % and the thickness was about 2.0-3.3 nm. The
top barrier consists of about 7.4-7.5 nm of Ino. 17A 0 .8 3N layer and 1 nm AlN interlayer. Figure 325 shows the cross-sectional TEM images of the grown wafers with 26 nm and 3.4 nm GaN
channel. The energy band structure and the 2-DEG charge distribution of each wafer were
simulated as shown in Figure 3-26. It shows that the charge confinement can be improved with
scaling down the channel thickness defined by the distance between top barrier and InGaN back
barrier. According to the simulation result, however, the overlap between electron wave function
and InGaN layer is increased significantly in the case of the heterostructure with 3.4 nm GaN
channel. This can result in the decrease of the mobility by increasing the interface and alloy
77
4
4
InAIN/AIN
2-
tGaN
InGaN
2-DEG
InAIN/AIN
= 26 nm
0
tGaN
2
2-DEG
fO
~_
12 nm
InGaN
0
GaN
-2
Ef
0)
Ef
GaN
-2
-4
-4
0)
(
40
30
20
Depth (nm)
10
0
10
40
30
20
Depth (nm)
(b)
(a)
A
4
2
InAIN/AIN
tGaN = 6.2 nm
InAIN/AIN
2
2-DEG
0
0
-2
GaN
InGaN
0
GaN
-2
InGaN
Ef
-4
-4
C
3.4 nm
2-DEG
0)
Ef
tGaN
10
30
20
Depth (nm)
(c)
)
40
10
30
20
Depth (nm)
40
(d)
Figure 3-26. Energy band diagram simulation results depending on the GaN channel thickness (a)
3 4
26 nm, (b) tGaN 2 nm, (C) tGaN= 6.2nm, (d) tGaN= . nm.
tGaN=
scattering. In fact, as shown in Figure 3-27, a significant mobility drop is observed in the wafer
with 3.4 nm GaN channel while a slight decrease in the channel mobility occurs with scaling
down the GaN channel thickness from 26 nm to about 6 nm. In addition to the serious mobility
drop, a substantial increase in the charge density was observed in the wafer with 3.4 nm GaN
channel. This indicates the possibility of Indium segregation and diffusion into the GaN channel,
which can enhance polarization difference between the GaN layer and the top barrier. Also, this
can be another reason for such a significant decrease in the mobility in this wafer.
78
4
2000
E
W,1500-
-----,--
2C
1000
500
0
Abnormal increase in n
500
cl0
0-
0
3
25
20
15
10
5
GaN Channel Thickness tGaN m)
Figure 3-27. Mobility and 2-DEG charge density depending on GaN channel thickness in InAIN/GaN
heterostructures.
3.5.3.2. Device fabrication
The device fabrication process began with mesa isolation with BC 3/C1 2 plasma dry etching.
Then, ohmic contacts were formed with a Si/Ge/Ti/Al/Ni/Au metal stack deposition and
subsequent annealing at 820 'C for 30 s. A contact resistance of 0.3-0.4 n-mm was obtained in
the wafers with 12 nm and 26 nm GaN channel, while the contact resistance in the wafer with 6.2
nm GaN channel is slightly higher (R- = 0.4-0.6 Q-mm). In the case of the wafer with 3.4 nm
GaN channel, the contact resistance was very high and non-uniform (R, = 0.8-1.3 i-mm) as
shown in Figure 3-28, which can be caused by instability of the heterostructure. The source-todrain distance was 1.0-1.2 pm. After the ohmic contact fabrication, an oxygen plasma was
applied, which forms a 1-2 nm oxide layer on top of the InAlN layer. Submicron gates with
lengths from 30 to 230 nm were defined in the middle of the source-drain region by electronbeam lithography with a single PMMA layer. A Ni (10 nm)/Au (70nm) gate metal stack was
79
1.6
E
E 1.4-EE
2
1.5
-
1.
0
U)
1
1
.
Z
--
W 0.5
0.8
t
)0
--
-aN
700
860
900
Annealing Temperature (OC)
0
5
0
10
15
20
25
30
GaN Channel Thickness tGaN (nm)
Figure 3-28. Contact resistance depending on GaN channel thickness. The inset shows the contact
resistance depending on annealing temperature in 3.4 nm GaN channel wafer.
deposited by electron-beam evaporation. Finally, a I 0-nm A12 0 3 passivation layer was deposited
by atomic layer deposition (ALD).
3.5.3.3. DC characteristics
Figure 3-29 shows DC characteristics for 30-nm gate length InAlN/GaN HEMTs with different
GaN channel thickness. Thanks to the combination of high mobility and low contact/access
resistance, an extrinsic transconductance (gm) of 530 mS/mm with on-resistance (Ron) of 1.2
0-mm is obtained in the device with 26 nm GaN channel. As the GaN channel thickness
decreases, the extrinsic transconductance decreases due to degradation of the transport and
increased parasitic resistance. In particular, the device with 3.4 nm GaN channel has significantly
lower g..(150 mS/mm) and higher Ron (5.4 Q-mm) compared to other devices, which is expected
from the Hall and TLM measurements.
80
tGaN=
.E
1 VDS
=3
E
tGaNl
V
VDS =3
0.8
-
E 0.6
C0
26 nm
tGaN
V
0.6
0.2
0.2,
0.2
-
0
-6
-2
-6
VGs (V)
Co
s
-630
5= V
-4
-2
0.4
VDS =-6
0.2
-4
-2
0
2
-0 V
1 .5
0.5
0.5
0.5
0 .5
3 4
VDS (V)
5
01
-4
-2
VD = -6 ~0 V
1.5-
1 V02
-6
2
.
Vs = -6 -0 V
1.5-
VGS (V)
=15O mS
-
VGS (V)
1.5
0
-
VGS (V)
VGS (V)
2
3 V
MS
S470
9m maX=470 mS
0.4-
-4
VDS'=
0.8
0.4-
-6
1*
0.6
gsma=500 mS
3.4nm
tGaN
0.8
0.4
0
6.2 nm
VDS= 3 V
0.8 -
0.6-
sa~5O ms
2
34
VDS (V)
5
10
1
2
3
4 5
V DS (V
Figure 3-29. DC transfer and output characteristics of 30-nm gate length InAIN/GaN HEMTs with
different GaN channel thickness (tGaN 26, 12, 6.2, 3.4 nm).
In spite of the negative impact on the transport properties, vertical GaN channel scaling
contributes to the improvement of the subthreshold and pinch-off characteristics. Figure 3-30
shows DIBL as a function of the gate length in the devices with different GaN channel thickness.
(DIBL of the devices with 3.4 nm GaN channel could not be extracted due to the high gate
leakage caused by the poor Schottky contact.) DIBL in the device with 26 nm GaN channel
increases rapidly as the gate length scales down to sub-50 nm and it reaches 500 mV/V in 30 nm
gate length device. On the other hand, the device with 6.2 nm GaN channel has the DIBL of 220
mV/V at the similar gate length, which is 56 % lower than the device with 26 nm GaN channel.
81
In addition, the thin GaN channel prevents the degradation of the pinch-off characteristic at high
drain bias as shown in Figure 3-3 1(a). With scaling the GaN channel, the leakage current path
can be minimized by bringing the energy barrier induced by the InGaN layer toward the channel
as described in Figure 3-31(b).
600
tGaN=
500-
*tGaN=
26 nm
3tGN= 12 nm
400
A
-
tGaN
*
26
nm
VDS =1,
5V
tGaN=12
n
6 2
. nm
E
E 300
10 0
-j
-
200
-4
I ......
100
0-0
50
100
150
200
L9 (nm)
L =30-nm
250
10-8
-6
-4
-2
VGS (V)
(a)
(b)
Figure 3-30. (a) DIBL as a function of gate length in the devices with different GaN channel thickness.
(DIBL is extracted at ID= 103 A/mm.) (b) Subthreshold characteristics of 30 nm gate length devices with
different GaN channel thickness.
100
0
26
n
AGs G
V
tG-N= 12 nmV
10-2
10-4
tGaN
PA,2
A tGaN=62n
IL
E
E
10
10
-8
F
1
2
VGs= -6 V
4
SiC substrate
56
VDS (V)
(a)
(b)
Figure 3-31. (a) Leakage current at VGs= -6 V in the devices with different GaN channel thickness. (b)
Leakage current path in the devices at pinch-off regime.
82
400
60
0teaN
A tGaN
300 --
26 nm
N
6.2 nm
tGN=
tGaN
*
12 nm
50
3.4 nm
h
2
G
26 nm
*
GN
6.2 nm
V tGaN
tGaN=
12 nm
3.4 nm-
'4
40
o
200
- -30
234
295 GHzI
A
2
10
0
0
L
50
100
150
L (nm)
200
250
g
(a)
0
1
GHz
*300
20
100 - -
30 nm
10
100
Frequency (GHz)
400
(b)
Figure 3-32. (a) Maximum fr as a function of the gate length in the devices with different GaN channel
thickness. (b) RF characteristics of 30-nm gate length devices.
3.5.3.4. RF characteristics
The RF performance of the devices was characterized by using an Agilent N5250C network
analyzer. The system was calibrated with an off-wafer line-reflect-match (LRM) calibration
standard, and on-wafer open and short patterns were used to de-embed parasitic pad capacitances
and inductances from the measured S-parameters [63]. Figure 3-32(a) shows the f1 as a function
of the gate length in the devices with different GaN channel thickness. In most of the gate length
range, the devices with 26 nm GaN channel have the highest performance and the fr decreases as
the channel thickness scales down. Since the device speed measured in the active bias condition
is mainly determined by the channel transport property, the negative impact of the vertical
channel scaling on the transport results in the degradation of the f1 in the devices with thin GaN
channel in spite of the improvement of the electrostatic in subthreshold and off regime.
Moreover, the effect of the higher parasitic resistances in the devices with thinner channel results
in additional decreases of the fT. Due to these reasons, the highest f1 of 300 GHz is obtained in
83
the 30 nm gate length device with 26 nm GaN channel as shown in Figure 3-32(b). In the case of
the device with 12 nm GaN channel, the decrease of the f1 in minimal (295 GHz) thanks to the
low contact resistance and high output resistance. On the other hands, in the devices with 6.2 nm
and 3.4 nm GaN channel, the degradation of the device speed is compounded by the higher
contact resistance.
As explained above, the vertical channel scaling influences the device speed through several
factors such as transport, electrostatic, and parasitic resistance. In order to study the impact of the
vertical channel scaling especially on the intrinsic device, the total device delay is divided into
each delay component based on the small-signal equivalent circuit model explained in section
3.2.1 [74]. First, parasitic resistances (Rg, Rs, Rd) were extracted from on-state bias condition
(VDS= OV, VGS 9 VT). Then, gate capacitance (Cgs, Cgd), intrinsic transconductance (gm.int), and
output resistance
(Rsd)
were calculated analytically from the measured S-parameters in the
devices with different gate length and channel thickness. Finally, the intrinsic and extrinsic gate
capacitance were extracted through linear extrapolation at the same gate overdrive and drain
voltage. The extrinsic gate capacitances
(Cgs.ext, Cgd.ext)
were obtained from the y-intercepts and
the intrinsic gate capacitances were calculated based on the extrapolation slope (C*gs.int) as
follows:
(3.6)
Cgs = Cgs.int + Cgs.ext = CL*s.intg + Cgs.ext
Cgd = Cgd.int + Cgd.ext = C *j.intLg
Figure
3-33
shows
the
extracted
intrinsic/extrinsic
(3.7)
+ Cgd.ext
gate
capacitances
and
intrinsic
transconductance in the devices with 26 nm GaN channel. Since the devices are in saturation
84
1000
1000
tGaN=
26 nm
VDS=
4V
tGaN=
800
900
~. 600
800
S 400
Cg cta
E
200 - 50
100
150
L (nm)
VDS=
G~0 ~(~
4V
Can 7 i
700
sin
Egdint
00
26 nm
(a)
600
500
50
100
L (nm)
150
(b)
Figure 3-33. Delay analysis process: (a) extraction of the intrinsic and extrinsic capacitances (b) intrinsic
transconductance depending on the gate length.
regime, the extracted Cgs.int (4.9 fF/m
2)
is close to two-third of the unit gate capacitance as
discussed in the section 3.2.2. In the case of the intrinsic transconductance, it gradually increases
with decreasing the gate length up to about 50 nm thanks to the increased channel electric field,
but it starts to decrease in the gate length range below 50 nm because of the degradation of the
gate modulation efficiency. The same extraction procedure was also performed for the devices
with different GaN channel thickness and each delay component was calculated as shown in
Figure 3-34.
Different from the extrinsic (text) or parasitic delay (Tpar), the intrinsic delay (rint) scales almost
linearly with the gate length thanks to the linear dependence of the intrinsic capacitance (Cgs.int,
Cgdint) on the gate length. Theoretically, without short channel effects, the intrinsic delay
extracted at the same drain bias tends to decrease a little bit faster than linear trend due to the
gradual increase of the intrinsic transconductance (gmilt) resulting from the increase in channel
electric field. In contrast, if short channel effects are serious, the intrinsic delay scaling becomes
85
1
1
tGaN
26 nm
1
tGaN=12
nm
1
tGaN
6.2 nm
00.8
0.
-0.8-
0.8
%.. itTint
S0.6
0.6
T,~0.6
0.4
0.4
Text
V
V-0.2
Tpar
0
50
100
L (nm)
(a)
Text
Text
0.2
150
Tn
t
50
0.4 0.2
Text
Tpar
Tpar
00
0.6
TInt
Tpar
0.4
S0.2-
3.4 nm
tGaN
100 150
L (nm)
"0
(b)
50
100 150
L (nm)
(c)
10
50
100 150
L (nm)
(d)
Figure 3-34. Delay extraction results of the devices with different GaN channel thickness at VDs= 4 V.
(a) tGaN 26 nm, (b) tGaN= 12 nm, (c) tGaN 6.2 nm, (d) tGaN 3.4 nm.
slower than linear trend due to the decrease of the intrinsic transconductance (gm.int) caused by
the degradation of the gate modulation efficiency. Although the slight decrease of the intrinsic
transconductance in the 30 nm gate length device was observed, as shown in Figure 3-33(b), it
was not serious thanks to thin top barrier of the InAIN/GaN heterostructure. Based on the
extracted intrinsic delay, the average electron velocity (ve) can be calculated with following
equation.
Ve =
Tint
(3.8)
The extracted average electron velocity is one of the key parameters representing the
performance of the intrinsic device because it captures the effect of both transport and
electrostatic. Moreover, the transport property reflected in the average electron velocity is the
transport under high electric field, which is different from that under low electric field obtained
from Hall measurement. Figure 3-35 shows the extracted average electron velocity as a function
86
2
2000
decrease in Ve
1.5
1500
.
10000
0.5
E
-500
050
0
5
10
15
20
25
GaN Channel Thickness tGaN (nm)
38
Figure 3-35. Average electron velocity and mobility of the devices with different GaN channel
thickness.
of the GaN channel thickness. The highest average electron velocity of 1.45-1.5 x 107 cm/s is
obtained in the devices with 26 nm GaN channel and it gradually decreases with scaling down
the channel thickness to 6.2 nm. In the devices with 3.4 nm GaN channel, the electron velocity is
30 % lower than in thicker channel devices due to the significant degradation of the mobility in
this heterostructure. However, this degradation is less than what has been seen in the mobility
(55 %). This is because the devices in sub-100 nm gate length range operate under velocity
saturation, so that the average electron velocity is determined not only by the low field mobility,
but also high field saturation velocity.
3.5.3.5. Vertical channel scaling design
As shown in the experimental results, vertical channel scaling can improve the subthreshold and
pinch-off characteristics by increasing the degree of the channel charge confinement. However,
87
excessive channel scaling can cause the degradation of the transport properties by introducing
additional interface/alloy scattering, which causes the decrease of the device speed. Thus, in
order to take advantage of the vertical channel scaling technology without serious degradation of
the transport properties, optimization of the channel thickness is the most important. Based on
the experiments in this work, the channel thickness between 10 nm and 15 nm can provide a
good electrostatic with maintaining the high mobility. However, it should be noted that the
optimized condition can be changed depending the growth condition and heterostructure design.
For example, improvement in the growth technology can provide a better interface between
InGaN and GaN, which makes it possible to shrink the GaN channel thickness below 10 nm with
keeping the high mobility. Also, the change of the Indium composition or thickness of InGaN
layer can change the band structure and growth requirement. Lower indium composition or
thinner InGaN layer reduces the conduction band offset effect, but it can ease the growth of
heterostructure and improve the interface property by reducing the strain caused by the lattice
mismatch.
3.6. Conclusion
In this chapter, critical factors limiting the speed of the intrinsic device were studied. In order to
reduce the intrinsic delay, the main delay component of the intrinsic device, electron-lithography
technology was first optimized for scaling the gate length to 30 nm range. However, it was
observed that serious degradation of the gate modulation efficiency prevented the decrease of the
intrinsic delay with gate length scaling, which limited device speed of the 30 nm gate length
AlGaN/GaN HEMTs to 170 GHz range.
88
To maintain the gate modulation efficiency in the deeply-scaled devices, InAlN/GaN
heterostructure was applied, which improved the gate controllability by increasing the vertical
electric field with high aspect ratio. Moreover, the high polarization field of the InAlN layer
provided enough charge in spite of its thin thickness and the maximum drain current was over
1.5 A/mm. Thanks to these effects, a maximum fT of 245 GHz was achieved in the 30 nm gate
length device, which was higher than any other GaN HEMTs previously demonstrated in the
literature.
Despite the 30 nm gate length InAIN/GaN HEMTs showed excellent performance in the active
bias region, pinch-off degradation and high DIBL were observed in off-state and subthreshold
bias regions. In order for an intrinsic device design to be a complete solution, it should provide
excellent channel control in the entire bias range. To solve these issues, two different approaches
were combined with InAlN/GaN heterostructure. The use of an AlGaN back barrier structure
increased the 2-DEG charge confinement by inducing additional polarization field in GaN layer,
which allowed sub-30 nm gate length device to have excellent pinch off with reduced DIBL. As
another approach, vertical channel scaling could also provide the similar effect by introducing
the conduction band offset effect at the interface between GaN and InGaN. In spite of these
advantages, each technology had its own drawback. AlGaN back barrier structure reduces the 2DEG charge density due to the raised GaN conduction band and degrades the thermal
conductivity. In the case of vertical channel scaling technology, the mobility can be degraded
due to additional interface/alloy scattering if the channel is thinned down excessively. Thus,
careful heterostructure design and growth are required to take advantage of these technologies
with minimal side effects.
89
Chapter 4. Extrinsic Limits for Maximum GaN HEMT Speed
4.1. Introduction
In the previous chapter, the important factors limiting the speed of the intrinsic GaN transistor
were discussed. Since the intrinsic gate capacitance decreases in a way linearly proportional to
the gate length, the intrinsic delay (Trt) scales down with gate length scaling if the device has
good electrostatics. In contrast, because the source/drain resistance and gate fringing capacitance
stay almost constant regardless of the gate length, the extrinsic (Text) and parasitic delays
(Tpar)
become more important in the deeply-scaled devices. Figure 4-1 shows the delay analysis results
of different gate length devices [99]. In the device with a gate length over 100 nm, the intrinsic
delay is the main delay component while parasitic and extrinsic delays have a relatively small
contribution in the total device delay. However, as the gate length scales, the portion of these
components becomes larger due to the decrease in the intrinsic delay. In the 30 nm gate length
1.5
VDS= 4 V
L9=1 2 2 nm
L9= 9 2 nm
01
L9=7 3 nm
E
L9=30 nm
0.5
0Figure 4-1. Distribution of each delay component in different gate length devices.
90
device, the sum of the parasitic and extrinsic delay is about 63 % of total delay, which is much
larger than the intrinsic delay. This result highlights that understanding and minimizing these
delay components are critical in order to increase the speed of the short channel devices. In this
chapter, the impact of the extrinsic device on the speed of deeply-scaled GaN HEMTs is
investigated, focusing on the extrinsic and parasitic delays.
4.2. Parasitic delay
4.2.1. Origin of the parasitic delay
As shown in the section 3.2, the parasitic delay is defined by the following equation according
to the small-signal equivalent circuit model discussed in section 3.2.1 [74].
9sd
Tpar = (Rs + Rd) ' Cd + (Cs + Cd) . -
9M
41
(4.1)
Although the equation clearly shows that the parasitic delay results from the source and drain
resistances, it does not explain the mechanism by which the delay is generated. To understand
this, we should start by analyzing a device with no parasitic delay. Figure 4-2(a) shows a simple
small-signal equivalent circuit model for ideal transistors with no source/drain and infinite output
resistances. Since
Cgd
fT
is defined based on the short-circuited output, there is no Miller effect on
and total device delay (Tt) or fT of ideal transistors can be expressed by the following
equation.
Tt =
1
_Cgs+Cgd
=
2TT
91
gm
9m.int
(4.2)
Cgd
Gsv
+
C,
D
|
Vg
v,,
m.int
T
Vgs
V
=+s0
S
(a)
Cgd
G
R1
I
cgs
I
va,
Rsd Vs'
gm.int vgs
- 9m.int
D
(RS+R)V
1+ (Rs+Rd) / Rsd9'
R
T
I
MXJ
if=
9m.int
vy
S'
1+ R/(R+Rd)
(b)
Figure 4-2. Simple small-signal equivalent circuit model for (a) ideal transistor with no source/drain
resistances and infinite output resistance and (b) real transistor with non-zero source/drain resistances
and finite output resistance.
As shown in the equation, the total device delay in the ideal transistors is equal to the time
required for the incremental change of the drain current (gm.int) to charge the incremental change
of channel charge represented by the gate capacitance (Cgs, Cgd). In the real transistors, however,
non-zero source/drain resistances and finite output resistance exist as shown in Figure 4-2(b),
which introduces two additional effects. First of all, the source/drain resistances (Rs, Rd) generate
a voltage difference between intrinsic source and drain, which results in a Miller effect on Cgd. In
addition, the finite output resistance
(Rsd)
provides a path for the current resulting from this
92
voltage difference, which decreases the current available to charge the gate capacitance. Due to
these effects, the equations for Cgd and gm.int are changed as follows:
Cgd
1 +
9m.int - (Rs +
+ R +R
Rd)
(4.3)
Cgd
Rsd
9
9m.znt *1
m.int
+ RS + Rd
(4.4)
Rsd
Based on these equations, the total device delay in transistors with source/drain and output
resistances can be derived as follows:
+
cs
1+9m.int (Rs + Rd)
+ Rs +R
Cs+(1
Tt =
/
-Cgd
gm.int
(4.5)
+ Rs + Rd
Rsd
Cgs__
+
g
=y+y+
9m.int
Cg
- (Rs + Rd)+(Cgs +
sd
Cgd)-(Rs
where output conductance (gsd) is inverse of output resistance (1/
+ Rd)
Rsd).
-)9
m.int
Compared to the equation
(4-2), two additional terms are included in equation (4-5). The first term is caused by the Miller
effect and the second term results from leak of the charging current through the output resistance.
The sum of these two terms is the parasitic delay as defined in equation (4-1). In order to reduce
the parasitic delay, the source/drain resistances should be decreased, while the output resistance
should be increased.
93
2
300
200
0
0
0.6
86
E
E
*0.4
----
E
E 1.6
0
100
200
300
Temperature (K)
0
(a)
1
100
200
300
Temperature (K)
(b)
Figure 4-3. (a) Sheet and contact resistances depending on the temperature. (b) On-resistance depending
on the temperature.
4.2.2. Low temperature measurement
In order to estimate how much improvement in the device speed can be achieved by reducing
the source/drain resistances, we measured the high frequency performance of a 40-nm transistor
at cryogenic temperatures. The device used in this study was fabricated on an InAIN/GaN
heterostructure with AlGaN back barrier and has a conventional alloy ohmic contact. Figure 43(a) shows the sheet and contact resistances as a function of temperature. About 73 % of the
sheet resistance is decreased with decreasing temperature from 300 K to 77 K due to the
improved mobility, while the contact resistance is almost constant.
Figure 4-4 shows DC output and transfer characteristics of the device in 300 K and 77 K.
Thanks to the decrease in the access resistance, the on-resistance is decreased by 31 % (Figure 43(b)). Extrinsic transconductance is also increased mainly because of the reduced source
parasitic resistance. The improved mobility can increase the average electron velocity in the
channel, but its effect is small in the device with saturation electron velocity. In terms of
microwave performance, the maximum
fT
is increased from 240 GHz to 285 GHz as shown in
94
Figure 4-5. Moreover, the drain bias at the maximum fr becomes smaller with decreasing the
temperature because the effective drain bias (VDS
ID
-
(R, + Rd)) is increased thanks to the
x
reduced source/drain resistances. These results show that there is a large room for improvement
in both DC and RF device performance by reducing source/drain resistances.
1
Lg= 40-nm
L = 40-nm77K
VGS=
E0)
-4 ~1 V
1
E
E
0.8-
77 K
---
VDS= 3 V
0.6
300 K
..E
E
0.5
0
(
4
2
VDS (V)
1
-
0.2
I
Ron= 1.82 Q-mm
Wo
0.4
6
rii
8
I
0
-
-1
-2
-3
-4
VGS (V)
(b)
(a)
Figure 4-4. DC (a) output and (b) transfer characteristics of 40-nm gate length device at 300 and 77 K.
60
50
40
h
300
Open: 300 K
Filled: 77 K
L = 40-nm
-
-
77 K
250
2
180K
-
N
~0
X2
30
CD 20
300 K
200[
285 GHz
10
L
240 GHz
150'0
0%
"1
10
100 300
Frequency (GHz)
1
2
3
V
4
40-nm
5
6
(V)
(b)
(a)
Figure 4-5. (a) RF characteristic of 40-nm gate length device at 300 and 77 K. (b) fT as a function of the
drain bias at different temperatures.
95
4.2.3. GaN HEMTs with ultra-low on-resistance
4.2.3.1. Technologies to reduce source/drain resistances
As explained in the previous sections, the reduction of the source/drain resistances is critical to
decrease the parasitic delay. The increase of the output resistance through the use of a back
barrier structure or vertical channel scaling can also contribute to the reduction of the parasitic
delay, but its impact is not as significant as the source/drain resistances. The source/drain
resistances in GaN HEMTs are composed of the contact resistance and access resistance. There
has been extensive research to reduce the contact resistance in GaN HEMTs and diverse
technologies have been developed. For example, ohmic recess technology [38], [100], [101] and
Si implantation [102]-[105] were demonstrated in AlGaN/GaN heterostructure. However, the
contact recess technology is very sensitive to processing conditions such as etch depth and
annealing temperature, so it is not easy to get reproducible results. Also, it is very challenging to
apply it to heterostructures with thin top barriers like InAlN [84] and AlN [83]. In the case of Si
implantation, it can provide a low contact resistance by doping the top barrier and GaN layer
selectively, but high temperature annealing over 1000 'C is required to activate the dopants.
During this annealing process, the heterostructure interface can be degraded, which results in
serious mobility reduction. As an alternative approach, selective GaN regrowth technology was
developed [106], [107]. This process can provide a very low contact resistance by forming a
highly-doped region under the metal contact and minimizing the resistance to the 2DEG channel.
Also, as the regrown is conducted below 600-700 'C, there is no risk of mobility degradation.
To further reduce the access resistances, new barrier materials such as InAlN and AlN can
provide higher 2-DEG charge density than conventional AlGaN/GaN hestrostructure. Also,
scaling the gate-to-source distance and gate-to-drain distance can also decrease the access
96
resistance, although short gate-to-drain distance degrades the breakdown voltage. In this study,
contact regrowth technology, sub-micron source/drain distance (LsD), and low sheet resistance
heterostructure were combined to reduce the parasitic resistance and its impact on DC and RF
performance was studied.
4.2.3.2. Device fabrication
The wafer used in this study was grown on a SiC substrate by metal-organic chemical vapor
deposition (MOCVD). The heterostructure consisted of 10.3 nm Ino. 13A10. 83Gao.04N layer near
lattice-matched to GaN and 0.5 nm AIN interlayer as the top barrier, and 1 tm GaN buffer. A 2DEG of 1.64 x 1013 cm-2, an electron mobility of 1766 cm 2 / Vs and a sheet resistance of 210
n/o were obtained from van der Pauw Hall measurements.
Device fabrication began with the deposition of a SiO 2 hard mask by plasma enhanced chemical
vapor deposition (PECVD). After photolithography of the ohmic contacts, the hard mask and top
barrier were removed in the source/drain contact region using dry etching. Then, highly doped n+
GaN/InGaN layers were grown selectively on the exposed source/drain region by molecular
beam epitaxy (MBE). The InGaN layer helps to reduce the contact resistance because of its
smaller band gap. The distance between the regrown source and drain contacts was 660 nm.
After removing the SiO 2 layer, mesa isolation was conducted with BCl 3/C 2 plasma dry etching
and Ti/Al metallization was used to form unalloyed ohmic contacts. Afterwards, an oxygen
plasma treatment was applied to the source-to-drain region, which formed a thin oxide layer on
top of the InAlGaN barrier. Submicron rectangular-shape gates with lengths from sub-30 nm to
190-nm were defined by electron-beam lithography. A Ni (10 nm)/Au (11 Onm) gate metal stack
97
660 nm
sub-30 nm
I
G
A12030(0
Plasma oxide 1 nm)
R
Rc2
R2
D
nm):
n+ InGaN
GaN
Figure 4-6. Schematic image of sub-30 nm device with extremely low on-resistance.
was deposited by electron-beam evaporation. Finally, a 10 nm A120
3
passivation layer was
deposited by atomic layer deposition (ALD).
4.2.3.3. DC characteristics
Figure 4-6 shows the cross-sectional schematic of the fabricated device with regrown contact.
The parasitic resistance of the device is composed of four main components: Rci (metal-toregrown area contact resistance), Re (regrown area resistance), Rc2 (regrown area-to-2-DEG
contact resistance), and R2-DEG (2-DEG access resistance). In order to extract each resistance
component, two different Transmission-Line-Measurement (TLM) patterns were used. The first
TLM pattern (TLM 1) is completely fabricated on top of a regrown area. From the measurement
of TLM1, the sheet resistance of the regrown area (Rsh.regrowth) and contact resistance between
metal and regrown area (Rc1 ) were extracted from the slope and y-intercept, respectively as
shown in Figure 4-7(a). In spite of the low electron mobility of the regrown area (93 cm 2/ V-s),
the sheet resistance is very low thanks to its high doping level which gives the sheet charge
density of 1.68
x
1015 cm- 2. In the case of TLM2 pattern, the regrown area is formed only under
98
14
70
TLM1
TLM2
12
60
10
50
8
40
6
600
30
2-DEG"
Metan
4t20
2
0
5
MetalMet
Regrowth
Regrowth
area
area
10 15 20 25
Distance (pm)
30
0
5
10 15 20 25
Distance (gm)
(a)
30
(b)
Figure 4-7. (a) TLM 1 pattern and its measurement result. (b) TLM2 pattern and its measurement result.
the contacts, just like in actual devices. Thus, the slope and y-intercept of the TLM2
measurement are associated to the sheet resistance of 2-DEG area and sum of Rci, Rc2 , and Rrc as
shown in Figure 4-7(b). Based on the information from two TLM measurements, the parasitic
resistance components of the actual device were calculated: Re1 (2
0.043 0-mm), Rc2 (2
x
0.043 0-mm), and
R2-DEG
x
0.008 Q-mm), Rre (2 x
(0.20 - 0.21 Q-mm). Thanks to the regrown
ohmic contacts, low 2-DEG sheet resistance and close source-to-drain distance (LSD), the
transistor has an extremely low on-resistance of 0.4-0.5 1-mm as shown in Figure 4-8. In
addition, the drain current reaches 1 A/mm with less than 0.5 V drain voltage. Moreover, in spite
of the relatively thick top barrier
(tb= 11.8
nm), the extrinsic transconductance goes over 770
mS/mm in the 50-nm gate length device thanks to the small source resistance. The gm of sub-30
nm gate length device (680 mS/mm) is lower than that of 50-nm gate length device due to
degradation of the gate modulation efficiency, which is caused by relative thick top barrier for
sub-50 nm devices.
99
2.5
o
Lg= 50-nm
2i--
E
VGS= -6 ~0
1
E 0.8
V-
E
1.5-
0.6
Lg= 50-nm
3
VDS=
-
- - -
AVDS= 0.5 V
'" -
E
E
0.5-
00
0
R,,N0.42 0mm
2
1
VDS (V)
3
0.4
0.2
06
4t
-5
-4
-3
VGS (V)
-2
(a)
25
.
--
1
L = sub-30 nm
L = sub-30 nm
2-
Eo
VGS= -7 ~0
E
f)
1.5
E
0.8
0.6
VDs= 1 ~ 3 V
AVS= 0.5 V
E 0.4
1
CM
0.5
RON= 0.1-
0
0
1
2
VDS (V)
0.2
m
3
06
4
-5
-4
-3
-2
VGS (V)
(b)
Figure 4-8. DC characteristics of the devices with gate length of (a) 50-nm and (b) sub-30 nm.
4.2.3.4. RF characteristics
The RF performance of the transistors was characterized from 400 MHz to 40 GHz with an
Agilent N5230A network analyzer. The system was calibrated with an off-wafer line-reflectmatch (LRM) calibration standard, and on-wafer open and short patterns were used to de-embed
parasitic pad capacitances and inductances from the measured S-parameters [63]. Figure 4-9(a)
shows comparison of the peak fT between the devices in this experiment (RO, < 0.5 Q-mm) and
100
60
350
300 -
L
sub-30 nm
50
-
40
Technology with
<0.50-mm
R n250
\
Ih21
330
320 GHz
MSG
2
20 IMAG:
150
10
Technology with
Ron >I mm
R
>1
25
50
Qmm10
75 100 125
L (nm)
Vo=2.5 V il-
150
0
1
VGS=-3.7 V
(a)
10
100
Frequency (GHz)
400
(b)
Figure 4-9. (a) Comparison of the maximum fr between devices in this experiment and devices used in
section 3.5.3. (b) RF characteristic of sub-30 nm gate length device.
the devices used in the section 3.5.3 (Ron > 1 Q-mm). Thanks to the reduction of parasitic
resistances, the high frequency performance is improved especially in short channel range. In the
sub-30 nm gate length device, the fT of 320-GHz is achieved by extrapolating the measurement
data with a slope of -20 dB/dec as shown in Figure 4-9(b) [108], which is higher than the best
device in the previous study (fT= 300 GHz in section 3.5.3) [99].
In order to analyze the device more systematically, a delay analysis based on the small-signal
equivalent circuit parameters was conducted [74]. The extraction was performed at VDS
and Vet{.ov= 0.8 V (Velf.ov=VGS
-
VT
-
2.5 V
ID x Rs). As shown in Figure 4-10(a), the low parasitic
source/drain resistances achieved by the regrown contact and scaled source/drain distance reduce
the parasitic delay significantly. In the 30-nm gate length devices, about 50 % lower parasitic
delay is obtained, compared to the device with alloy contact and 1-pm source-to-drain distance
(fr= 300 GHz). This reduces the portion of the parasitic delay from 24 % to 13 % in the 30-nm
gate length device as shown in Figure 4-10(b). In spite of the significant decrease of the parasitic
101
0.8
1
L =30-nm
(Ron= 0.4 - 0.5 0-mm)
'O 0.8-
300 GHz
0)
GO
Tint
Q-
'
0.6
(
I
0.6 &Io
.0.4
320 GHz
mm)
(Ron< 0.5 f-mm)
710
>0.4--
ext
0.2
j
a0.2
----
A par
---------0
0
100
80
60
40
20
Gate Length L9 (nm)
(b)
(a)
Figure 4-10. (a) Delay analysis result of devices with regrowth contact and scaled source/drain distance
(LSD). (b) Comparison of delay analysis of 30-nm gate length devices with Rn > 1 Q-mm (alloy contact
and LSD > I ptm) and R0 n < 0.5 £-mm (regrowth contact and LSD < 0.7 tm).
delay, the improvement in the fr is relatively small (fT= 320 GHz) because of short channel
effects. As explained in chapter 3, the intrinsic delay is not scaled linearly in the short gate length
range (Lg< 50 nm) due to the decrease of the intrinsic transconductance. Moreover, the
degradation of device electrostatic also increases the parasitic delay. The total parasitic delay can
be divided into two components as follows:
Tpar = Cg(Rs + Rd) 1 +
1
Tpari = Cga
1 + cgs)
qj
C9 d )m.int
(4.7)
(Rs + Rd)
Tpar 2 = (Cgs + Cgd)(Rs + Rd)
102
(4.6)
]
(4.8)
9m.int
0.06
T
parl
0.04
Tpar2
.
0.02
0
20
40
60
80
Gate Length (nm)
100
Figure 4-11. Parasitic delay components depending on the gate length.
Generally, Trparl is a main component of the parasitic delay and T par2 is significantly smaller than
Tparl
because of the go/gm.int factor. As the gate length scales down,
Tparl
decreases slowly due to
Cgd scaling. However, the increase of go and degradation of gm.int with gate length scaling can
result in the increase of T par2. As shown in Figure 4-11, below 50-nm gate length,
T
par2
becomes
larger than Tparl, which increases the total parasitic delay. This shows that maintaining good
electrostatics is important not only to reduce intrinsic delay as shown in chapter 3, but also to
take full advantage of the small source/drain resistances achieved by the regrowth contact and
scaled source/drain distance process.
4.3. Extrinsic delay
4.3.1. Importance of extrinsic delay
The extrinsic gate capacitance, which is source of the extrinsic delay, is caused by the coupling
between gate and 2-DEG outside of the intrinsic channel. Due to this reason, it is not dependent
on the gate length. Generally, it is assumed that the intrinsic delay determined by the intrinsic
103
gate capacitance and transconductance is a fundamental limit of the device speed. However,
realistically, the extrinsic delay originated from the extrinsic gate capacitance limits the device
speed because the extrinsic gate capacitance still exists in the devices with gate length close to
zero. Even in the 30 nm gate length device, the extrinsic delay is 38 % of the total device delay
as shown in Figure 4-1, which makes it one of the most important limiting factors.
A systematic study on the extrinsic capacitance is not easy due to the challenges in formalizing
its impact. One of the main components of the extrinsic gate capacitance is the fringing gate
capacitance and it does not only depend on the heterostructure, but also on the passivation and
gate shape. Depending on the dielectric constant and thickness of the passivation layer, the
fringing gate capacitance can vary significantly. Also, in the devices with T-shape gate, foot
height and head size are closely correlated to the fringing gate capacitance. In this section, the
impact of the fringing gate capacitance on the device speed is investigated through both
experiments and simulations.
4.3.2. Device fabrication
The GaN epitaxial heterostructure used in this study was grown on a SiC substrate by metalorganic chemical vapor deposition (MOCVD). The heterostructure consisted of 10.8 nm
quaternary Ino. 13A10 .83 Gao.0 4 N barrier layer and 0.5 nm AlN interlayer as the top barrier, and 1.8
pim GaN buffer. A 2-dimentional charge density (2-DEG) of 1.77 x 1013 cm-2, an electron
mobility of 1774 cm 2/V-s and a sheet resistance of 199 Q/o were obtained from Hall effect
measurements using van der Pauw method.
The device fabrication process was very similar to the process used in section 4.2.3. A Si-doped
n+ GaN/InGaN regrowth technology was applied, which provides a total contact resistance of
104
GaN
Figure 4-12. Cross-sectional device structure used in this study.
0.12 Q-mm. Rectangular-shape gates with the length between sub-30 nm and 70 nm were
defined through e-beam lithography and subsequent Ni/Au (10 nm/90 nm) metal evaporation. 10
nm Al 2 0 3 passivation layer was deposited by atomic layer deposition (ALD) at 250 'C [57].
ALD was chosen due to the accurate control in the deposition thickness. After DC, pulsed I-V,
and RF characterization of the devices, an additional 10 nm Al 2 0 3 layer was deposited and the
devices were characterized again. This process was repeated until the total A12 0 3 layer thickness
became 40 nm [109].
4.3.3. Passivation effect on DC and pulsed-IV characteristics
Figure 4-13 shows a comparison of the output and transfer characteristics of devices with 10nm
and 40 nm passivation thickness. Generally, the A120 3 passivation increases the 2-DEG charge in
the access region due to the positive fixed charge effect in the layer, but its effect becomes
smaller with increasing the top barrier thickness. The heterostructure used in this study has a
barrier thickness over 10 nm, which makes the difference in the device characteristics almost
negligible, as shown in Figure 4-13. In the subthreshold characteristic, however, it is observed
that the drain-induced barrier lowering (DIBL) becomes larger with thick passivation as shown
105
21
tpass=40nm
L = sub-30 nm
1.5[
E
E
1
E
VGS= -5 ~0 V
E
0.8
SU
b-30 nm
VDs= 3 V
tpass= 40 nm
0.6-
II-
tpass= 1 On m
E
E
0.5[
0.2
tpassl10nm
0-
-6
4
3
2
1
/
0.4-
1* mdi
"00
Lg9=
VDS (V)
-5
-4
VGS (V)
-3
-2
(b)
(a)
Figure 4-13. DC (a) output and (b) transfer characteristics of sub-30nm gate length devices with A12 0 3
passivation thickness of 10 nm and 40 nm.
"UW
tpass= 40 nm
500
400
E
rumaI
300
200
tpass= 10
nm
100
VOI
20
40
60
80
100
L (nm)
Figure 4-14. DIBL in the devices with the passivation thickness of 10 nm and 40 nm.
in Figure 4-14. In the subthreshold bias condition, the electric field in the access region increases,
which increases the trapping effect in the surface of the access region between gate and drain. If
electron trapping occurs in this region, the effective channel length increases, which decreases
the DIBL [110]. The thick passivation suppresses the channel extension by reducing the surface
106
L =
Lg=
0-nm
j
DC
\
00 0 0 00 0000
0.
0 0
0 cpcn
,
10
0 1
-
21
Pulsed
1 .5- ps=0n
40
a30
0-n
E0
0 30050
2
3
VDs (V)
E20
2
0.5- Lg= 70-nm
1.5 tpas= 4O nm
0L
Pulsed
000O0
0000
000
0
0 100
0n1
-
DC
2
00
0
0
0
3
VDS (V)
Figure 4-15. Current collapse depending on the passivation thickness and comparison of the DC and
pulsed-IV characteristics of the devices with passivation thickness of 10 nm and 40 nm.
trapping, which increases the DIBL as shown in Figure 4-14. The larger DIBL is also the reason
for the lower threshold voltage in the device with thick passivation as shown in Figure 4-13.
Pulsed-IV measurement of the devices with the gate length between sub-30 nm and 70-nm was
performed with 100 Q2 load, 80 ps pulse width and maximum VGD= -16 V (VDs= 10 V, VGS= -6
V). The current collapse is calculated from the difference in current density between DC and
pulsed measurements at VGs= 0 V and VDs
Current collapse (%)
= ID.DC(VGS
2 V s follows.
OV>VDS=2V)-ID.pulsed(VGS-OVVDS=2V)x10(49
ID.DC(GS
0DS=2V)
107
350
10
VDS= 4 V
tPaSS= 10 nm
300-
tPa,,= 20 nm8A2O
0
-250
tpass=
30 nm
150
10
6-
2
VDS=
0
V
20
tpass=
40
60
Gate Length (nm)
-
- - GaN
0 nm
80
0
10-20
20-30 30-40
t ass (nm)
(a)
(b)
(c)
Figure 4-16. (a) fr as a function of the gate length depending on the passivation thickness (tpass). (b)
Degradation of fT with increasing the passivation thickness. (c) Cross-sectional image of the gate
fringing capacitance due to increase of the passivation thickness.
The current collapse decreases from 29.7 % to 13.7 % as the passivation thickness increases
from 10 nm to 40 nm as shown in Figure 4-15. This confirms that relatively thick passivation is
important for stable large signal operation, although it increases the gate fringing capacitance.
4.3.4. Passivation effect on RF characteristics
The RF performance of the devices was measured from 400 MHz to 40 GHz by using an
Agilent N5230A network analyzer. The system was calibrated with an off-wafer line reflect
match (LRM) calibration standard, and on-wafer open and short patterns were used to de-embed
parasitic pad capacitances and inductances from the measured S-parameters [63]. Figure 4-16(a)
shows the f- of the different gate length devices depending on the passivation thickness (tpass). A
significant decrease of 15-20 % in fr is observed when increasing the passivation thickness and it
is mainly caused by the increase in the gate fringing capacitance. In addition, the amount of the
108
decrease becomes more significant in short gate length devices. For example, in the devices with
Lg = sub-30 nm, the fT drops from 292 GHz
(fmax=
53 GHz) to 241 GHz (fmax= 42 GHz), while
that of devices with Lg = 70-nm changes from 177 GHz
(fmax=
147 GHz) to 154 GHz (fmax= 127
GHz). However, the change of fT is reduced as the total passivation thickness increases. Figure 416(b) shows the fT degradation rate as the total passivation thickness increases.
Degradationof fT (/)
__
*before - fT.after
x 100
(4.10)
fT.before
This is because the increase of the gate fringing capacitance caused by the additional passivation
layer decreases with increasing the total passivation thickness as shown in Figure 4-16(c).
4.3.5. Extraction of gate fringing capacitance
There are two approaches to extract the gate fringing capacitance. First, the total gate
capacitance including both intrinsic gate capacitance and fringing capacitance is extracted at ONstate condition (VGS >> VT and VDS= 0 V) from devices with different gate length. Then, the gate
fringing capacitance is obtained from the y-intercept in the extrapolation of the total gate
capacitance with gate length. A second approach is to extract the gate fringing capacitance
directly under pinch-off bias condition (VGS
0
VT
and VDS= 0 V). In this study, the second
method was used because it was challenging to accurately extract the gate capacitance at the ONstate bias condition (VGS= 0 V (VGS >> VT) and VDS= 0 V). As shown in Figure 4-17, different
from the extraction at saturation condition, the extracted Cgs and Cgd in the ON-state condition
varies signficantly with measurement frequency. At this bias condition, the same voltage (0 V) is
applied to both souce and drain which are electrically connected through the channel. Thus,
109
500
800
Lg= 50-nm
S400
E
300
0
L = 50-nm
600
C
E
Cgs
4C0
2
200
0
2 0
Cgd
(0
0,
-100
0
0
f
Cg
VDS= 3 V,VGS= -3.5 V
5
10
15
20
Frequency (GHz)
-200
0
25
VDS=O V, VGS= 0 V
5
10
15
20
Frequency (GHz)
(a)
25
(b)
Figure 4-17. Extracted Cgs and Cgd in (a) saturation bias condition
state condition (VDS= 0 V, VGS= OV).
(VT
-
GaN
3 V,
VGS=
-3.5 V) and (b) ON-
1) V
\j7
,/
(VDS=
-
CLg.dep
I
Figure 4-18. Gate capacitance distribution at the pinch-off bias condition.
theoretically, Cgs and Cgd should be almost same due to symmetry. However, in actual
measurement, a smalll potential difference between source and drain, caused by the measurment
noise during frequency scanning, can break the symmetry and result in nonneglibible error in the
extraction.
110
350
tpass= 40
E
300
iL
0
.
t
nm
30m
tpass=30
nm
'~'0'
4=250
C
Cfrin
200
tpass=10 nm
__
S150
100
tpass=
20 nm
pass
VGS= VT -1 V, VDS=O V
0
20
40
60
80
Gate Length (nm)
Figure 4-19. Extraction of the gate fringing capacitance at the pinch-off condition.
For the extraction of the gate fringing capacitance at the pinch-off condition, the following
process was performed with devices with different gate length and passivation thickness. First,
source and drain were grounded and a gate voltage of (VT -1)
V was applied as shown in Figure
4-18. Then, the gate capacitance is extracted from the measured S-parameters. At this bias
condition, the fringing capacitance dominates the gate capacitance because the channel is
pinched off. However, although the channel under the gate is depleted, a weak coupling between
the bottom of the gate electrode and access region still exists, which makes the extracted gate
capacitance at the pinch- off condition dependent on the gate length as shown in Figure 4-19.
The gate length-dependent capacitance (CLg.dep)
should not be included in the fringing
capacitance because it becomes negligible at the active bias condition due to the screening by the
electrons in the channel. To remove it, the gate fringing capacitance was extracted from the yintercept in the linear extrapolation of the extracted gate capacitance as shown in Figure 4-19.
111
VMS--0 VVVS=V
ON state
Gate
iL
2000
soure DainE
Gate
tpass
Passivation
KEA
nch-off state I
2500
,
-----.......
1500
=-----------
--
----
Passivation------
.. ...
..
8
7
6
V -
2
0
Figure 4-20. Gate capacitances extracted from the simulation results from different gate length.
However, this extraction process may have an error because the gate length-dependent
capacitance (CLg.dep) is not perfectly linearly proportional to the gate length.
In order to check whether the error in the extraction is acceptable, RF device simulation was
conducted with similar device structure. Since there is no noise effect in the simulation
environment, we can extract the gate fringing capacitance at both pinch-off and ON-state
conditions. The advantage of the extraction in the ON-state condition is that we can avoid the
effect of CLg.dep thanks to the screening by the channel electrons. Thus, by comparing the gate
fringing capacitance extracted in the pinch-off condition with that extracted from the ON-state
condition, we can estimate the error. For this, the gate capacitances (Cgg) are first extracted from
the RF simulation results of different gate length devices as shown in Figure 4-20. Then, the gate
capacitances at both pinch-off (VGs= VT - I V, VDS= 0 V) and ON-state (VGS= 0 V, VDs= 0 V)
conditions are plotted as a function of the gate length as shown in Figure 4-21. As pointed out in
the previous paragraph, the gate capacitance at the pinch-off condition is dependent on the gate
112
2500
600-:
.5S500-
2000
'
Cin= 246 fF/mm
W
>
1500
15
C n 209 fFlmm
4004-0
0 200
SVDS=
500
0V
VGS= VT- 1 V
0
-- - -
1000- _
EE
200
100
0
0
300
VGS (V)
VDS= 0 V
VGS= 0 V
200
100
300
VGSM
(a)
(b)
Figure 4-21. Gate fringing capacitance extraction from the simulated gate capacitance at (a) pinch-off
condition and (b) ON-state condition.
length, but it is not completely linear function of the gate length as shown in Figure 4-21(a). As
the gate length increases, the slope decreases due to the increased effective distance between the
bottom of the gate electrode and the edge of the access regions. However, in the short gate length
range below about 100 nm, it is approximately close to a linear function. Since the minimum
gate length used in the experiment is less than 70-nm as shown in Figure 4-19, a linear
extrapolation in the simulation results is also conducted in the gate length range below 70 nm
and the gate fringing of about 246 fF/mm is obtained. In the case of the extraction at the ONstate condition, the gate capacitance is a linear function of the gate length and the gate fringing
capacitance of 209 IF/mm is extracted from the y-intercept. This value is about 15 % different
from the result obtained from the pinch-off condition, which shows that the error caused by the
linear extrapolation in Figure 4-19 causes a slight over estimation, but it is in the acceptable
range. The difference in the gate fringing capacitance between the real measurement and
simulation result can be caused by the simplified simulation structure, difference in the material
dielectric constant, and extraction error.
113
200
...
180
160
--
140
120
0
10
20
30
tpass (nm)
40
Figure 4-22. Gate fringing capacitance extracted from the measurement depending on the passivation
thickness.
Figure 4-22 shows the gate fringing capacitance extracted from Figure 4-19 as a function of the
passivation thickness. The amount of increase in the gate fringing capacitance is large when the
passivation thickness changes from 10 nm to 20 nm, but it gets smaller as the total passivation
thickness increases, which is consistent with the trend observed in the fT. At about 40 nm range,
the increase of the gate fringing capacitance becomes almost saturated. However, the gate
fringing capacitance with 40 nm A120
3
passivation already reaches about 30-35 % of the total
gate capacitance extracted in the linear regime in the sub-35 nm gate length devices. It should be
noted that in real operating conditions (e.g. in saturation), the relative impact of the gate fringing
capacitance in Cgs and Cgd may change due to asymmetric charge distribution. In any case,
considering the rectangular-shape gate structure used in this study, the extracted gate capacitance
is close to the minimum possible value, although it can be affected by the exact barrier material,
thickness, and passivation layer. In devices with a T-shape gate structure, the fringing gate
capacitance becomes even larger due to additional coupling between the gate head and the access
region. Figure 4-23 shows the comparison of the fringing gate capacitances extracted from
114
Lhead
500T
50
500 nm
400
T
hgat= 100 nm
GateE
L9
Op
2h
hgaategat
200nm
rectangular
100
0
10
20
30
40
50
pass (nm)
(a)
(b)
Figure 4-23. (a) Simulation device structure for T-gate and (b) gate fringing capacitance depending on
passivation thickness and T-gate height.
simulation results of rectangular and T-shape gate devices with different gate height. The T-
shape gate with 200 nm height has about 15 % higher fringing gate capacitance than the
rectangular shape gate and the difference becomes significantly larger with lower height. These
results show the importance of thin low-k passivation technology to overcome the limit of the
extrinsic delay and to achieve extremely high device speed.
4.4. Projection of fT in deeply-scaled GaN HEMTs
The experiments shown in this chapter highlight the importance of the extrinsic device
components for high speed operation of deeply-scaled GaN HEMTs. In the sub-50 nm gate
length range, minimization of these components is as important as gate length scaling to increase
the device speed.
In order to estimate the improvement of the device speed as a function of the extrinsic/parasitic
components, an fT estimation model was built based on the delay analysis presented before and
115
8
0.8
VDs=
2V
E
E
E 0.6J
;d
'U"'VA
0.6
E)
2
0.2
VDS=
0
00
20 40 60 80 100
L9 (nm)
-
E
4
E
Parabolic trend
assumption
0.4
w 0.2
00
6
0.8
U-
0.4
0
'1\
Yo
2V
0
0
20 40 60 80 100
L (nm)
L9 (nm)
(c)
(b)
(a)
V=SV 2V
20 40 60 80 100
Figure 4-24. (a) Gate capacitance modeling. (b) Intrinsic transconductance model including short channel
effect. (c) Output resistance model including short channel effect.
600
SCE 50
50 %, C
30 %
xRt/R
500.SCE 50%, RS/Rd50%
400
SCE 50 %
300
200
Experiment data
100
n
10
_
_
-
_
__
L9 (nm)
100
200
Figure 4-25. fr projection depending on the technology improvement.
the experimental data obtained from the studies in this chapter [111]. For the gate capacitance
model, the linear extrapolation of the extracted gate capacitance is used as shown in Figure 424(a). For the intrinsic transconductance and output conductance model, parabolic and linear
trends are assumed, respectively in order to take into account the short-channel effects as shown
in Figure 4-24(b) and Figure 4-24(c). Opposite to the linear trend used for the gate capacitance,
116
the trends for the intrinsic transconductance and output conductance are a function of the specific
device structure.
Figure 4-25 shows the fr projection a function of gate length for different technologies.
First,
since the short channel effects in the data used in this model are relatively large due to the thick
top barrier
(tb >
11 nm), the two key limiting factors in the frequency performance are the
degradation of gate modulation efficiency and the output resistance. However, chapter 3 showed
that these can be effectively suppressed by a combination of top barrier engineering and back
barrier or vertical channel scaling. Once the short channel effects are suppressed, additional
boost in the device speed is possible with improving the extrinsic device components. A
reduction of the source/drain resistance by 50 % would yield a maximum fT of 30 nm gate length
device of about 370 GHz. Also, an additional reduction of the extrinsic capacitance by 30 %
would increase the device performance to 420 GHz, which clearly shows the significant
contribution of the parasitic and extrinsic delays in the total device delay. Following the
60
L
sub-30 nm
50
1h
2
:005
1
-40
-
00
30
20
10
10 20 30 40
Frequency (GHz)
375 GHz
MSG
/MAG
VDS= 2 V
VGS=
01
-2.9 V
10
100
Frequency (GHz)
Figure 4-26. RF characteristics of sub-30 nm gate length device.
117
400
projection, a combination of thinner top barrier, extremely thin passivation less than 5 nm and
low parasitic resistance technology was applied to the fabrication of a sub-30 nm gate length
device, which yielded a maximum
fT
of 375 GHz as shown in Figure 4-26. Based on the
projections described above, the reduction of the extrinsic/parasitic components with effective
suppression of the short channel effects can allow 20 nm GaN device to achieve an f1 above 500
GHz.
4.4. Conclusion
In this chapter, the impact of the extrinsic/parasitic components on the speed of the deeplyscaled GaN HEMTs was investigated. High source/drain resistances associated with high contact
resistance of the conventional alloyed contact and 2-DEG resistance of the access region
introduce non-negligible parasitic delays in sub-100 nm devices. Low temperature measurements
confirmed that there is a large room for improvement in device performance by reducing the
parasitic delay caused by these resistances. Diverse technologies were then introduced to reduce
these resistances, including heterostructure with low sheet resistance, scaled source-to-drain
distance and n+ InGaN/GaN regrowth contact, which reduced the Ron below 0.5 U-mm and
increased the maximum
fT
to 320 GHz. Based on the delay analysis, it was found that the
parasitic delay was reduced by about 50 % compared to the previous best device with fT of 300
GHz.
The fringing gate capacitance, which is another important extrinsic component, has also been
analyzed. One of the main sources of fringing gate capacitance is the sidewall of the gate
electrode, which is highly sensitive to the passivation layer. The decrease of the maximum
transistor frequency with increasing the passivation thickness is mainly caused by the increase of
118
the gate fringing capacitance. The gate fringing capacitance of the devices with different
passivation thickness was extracted from the RF measurements and device simulation. In the
sub-35 nm gate length devices, the gate fringing capacitance was more than 30-35 % of the total
gate capacitance, which showed the importance of the thin low-k passivation technology to push
the device further.
Based on the studies on the extrinsic/parasitic components, the projection model for the
maximum fT in a given technology has been proposed. This model shows that minimization of
the source/drain resistances and fringing gate capacitance with maintaining the good electrostatic
can push the speed of 30 nm gate length device above 400 GHz. Following the model, a GaN
transistor with a maximum fT of 375 GHz was experimentally demonstrated in a transistor with a
sub-30 nm gate length. The model further predicts that 20 nm gate length GaN HEMTs have a
potential to achieve an fT of 500 GHz.
119
Chapter 5. Delay under High Drain Bias: Drain Delay
5.1. Introduction
In the previous two chapters, the delay components that limit the maximum speed of deeplyscaled GaN HEMTs were studied by dividing the device into intrinsic and extrinsic regions. The
maximum device speed or maximum current gain cutoff frequency (fT), measured from the
small-signal microwave characteristics, is one of the most important parameters to show the
ultimate potential of the devices for RF applications. However, under large-signal operation,
maintaining the high device speed in a wide bias range is as important as reaching the maximum
speed in certain bias condition because the lowest
fT
in the target operating bias range is a
bottleneck in determining the actual operating frequency. This chapter will study the key limiting
factors for high speed operation under wide drain bias conditions, while chapter 6 will focus on
the impact of the gate bias range.
Compared to other semiconductor RF devices based on relatively narrow band gap materials
such as GaAs and InP, the main advantage of GaN HEMTs is the ability to operate under high
drain bias. However, as the operating drain voltage increases, the maximum operating frequency
of the devices generally decrease as shown in Figure 5-1 and it has been explained with the
expansion of the depletion region at drain-side access region. The depletion region results in the
increase of the effective gate length, which causes an additional electron transit time, so called
'drain delay' [40]. The drain delay has been studied in III-V transistors through various
approaches [40], [112]-[115], but it is more important in GaN-based HEMTs due to the larger
drain biases. In state-of-the-art high frequency GaN HEMTs with maximum
fT
above 300 GHz,
the highest fT is generally obtained at drain biases between 2 and 4 V [99], [108], [116], and
120
300
L =40-nm
250
200
=
150
_'
L=60-nm-
N
-A
L =100-nm
100
50
0
0
2
4
V
6
(V)
8
10
Figure 5-1. f1 as function of VDS in different gate length devices.
quickly decreases as the drain bias increases due to the effect of the drain delay. This decrease in
fT with increasing drain bias becomes even more significant in shorter gate length devices as
shown in Figure 5-1. Given that the main advantage of GaN-based RF devices over other III-V
HEMTs is their ability to operate under high drain bias and that the delay caused by the gate
extension is the main limiting factor in such bias range, it is very important to accurately
understand the drain delay. In this chapter, the drain delay in GaN HEMTs is systematically
studied through a small-signal equivalent circuit model. By using a new extraction method based
on the model, the drain delay is accurately estimated and it is compared with other extraction
methods reported in literatures. In addition, the origin of high drain delay in short channel
devices is investigated with analysis based on the model. Finally, several approaches to minimize
the decrease of the device speed at high drain bias are discussed.
121
IDiWG (mAlmm)
200 100
60
40
205
CONVENTIONAL
CONVENTIONAL
0CONVENTIONA
4
40
4
40
80
X-
42 -80
0
PSEUDOMORPHIC
2
00o
20PSEUDOMORPHIC
1
0
10
20
Wg/
0
30
40
so 1
100
0
50
(mmIA)
- 200
1
V0
(a)
4
2
3
I D (R + RD) (VOLTS)
5
(b)
Figure 5-2. N. Moll delay time analysis method [40]. Extraction methods of (a) channel charging delay
and (b) drain delay.
5.2. Drain delay extraction
5.2.1. Drain delay extraction method in literatures
The most popular delay analysis method for Field-Effect Transistors (FETs) is the method
proposed in the paper written by N. Moll et al. [40] (so called 'N. Moll method'). In this method,
the total device delay (Tt) is divided into gate transit delay, channel charging delay, and drain
delay. The gate transit delay is associated with the time needed by electrons to travel the channel
region, while the drain delay is defined as the extra transit time associated to crossing gate
extension region induced by the drain bias. The channel charging delay results from the channel
(device) resistance. In the extraction procedure, the channel charging delay is obtained from the
y-intercept of linear extrapolation in the plot:
't
vs drain current density (Wg/ID) as shown in
Figure 5-2(a). The reason behind this is that the channel charging delay should be zero when ID
becomes infinite. The drain delay is extracted from the dependence of Tt on the effective drain
122
bias (VDS.eff
VDS
- ID x
(Rs+Rd)) as shown in Figure 5-2(b). Finally, the gate transit delay is
calculated by subtracting the extracted parasitic charging delay and drain delay from the total
device delay.
The N. Moll method is a very useful tool for extracting each delay component directly from a
given device. Also, the procedure is simple and only one device is needed for the entire
extraction process. However, in spite of these advantages, there are several drawbacks. First of
all, although the logic behind the extraction method is intuitively understandable, the underlying
theoretical background in not straightforward. This makes it difficult to analyze each component
systematically. Also, the method was originally proposed in GaAs FETs which have very small
parasitic source/drain resistances. Due to this reason, the channel charging delay extracted from
this method focuses on the channel resistance rather than parasitic resistances coming from the
access region or contact resistance. This can result in a large error when applying the method to
devices with significant parasitic resistance like conventional GaN HEMTs. This issue was
pointed out in a few papers and the method was slightly modified to capture the parasitic
resistance effect [112], [115]. In addition, the drain delay extracted by the N. Moll method
includes all the effect caused by the high drain voltage. Based on the definition, the drain delay is
supposed to be the additional delay caused by the transit time in the gate extension region.
However, since the drain delay from N. Moll method is extracted from the change of the total
delay, there can be error between the extracted delay and true drain delay. To reduce the error,
instead of using the total delay, Shinohara et al. subtracted the parasitic delay component (Cgd (Rs+Rd)) from the total delay first and then extracted drain delay by using the left delay [117].
Although the method can reduce the error by excluding the effect of change of the parasitic delay
with drain bias, it still cannot solve the problem, completely.
123
Lg.ext
gint
GaN
I
I
Figure 5-3. Cross-sectional image of GaN device under deep saturation regime.
5.2.2. Small-signal equivalent circuit model including drain delay effect
In order to avoid the issues of N. Moll method, a new device delay model based on small-signal
equivalent circuit parameters is used in this study. Since the small-signal equivalent circuit
model has solid theoretical background, it can provide better understanding about each
component. However, the device delay model explained in the section 3.2.1 [74] does not
include the drain delay component. In this work, the drain delay component is added through the
theoretical derivation. In addition, a new extraction method for the drain delay is proposed based
on the model.
Figure 5-3 shows a simplified diagram of a GaN HEMT operating in saturation regime under
high drain bias. To support the drain voltage, a depletion region is formed at the drain-side of the
gate, extending through the drain access region. In this depletion region, the electric field is high
enough for electrons to move with saturated velocity. Thus, the total electron charge density in
this depletion region (QLg.ext) is given by
QLg.ext =
V
(Vsat
x
Lg.ext
(5.1)
where ID is the drain current, vsat is the saturation velocity, and Lg.ext is the effective gate
extension length or drain-side depletion region width. When the gate voltage changes, the drain
124
Gate Depletion region
Drain
Delto ein(Collector)
(Base)
-x
Gate
ion region (Collector)
(Base) IDpletio reolecDrai
x
(VGS + Vgs, ID + 3 d)
(VGS + aVgsI D +8 d)
P -VGS,
W)
(V(VGS
8
I
QLg.ext
D)
0.5-aQLg.ext '-(VGS,
q electron
EX
(a)
1.
(b)
Figure 5-4. (a) Lateral electric field and (b) electron charge distribution in the depletion region based on
the charge control model used for base-collector junction in BJT. (This model can be used for drain-side
depletion region in HEMT.)
current also changes and this is reflected in a change of the charge in the gate extension region.
From a small-signal perspective, the rate of change of this charge can be expressed by the
capacitance.
CLg.ext = (OQY(et N)-x
Lg.ext
(5.2)
However, different from the change of the intrinsic channel charge which is imaged to the gate
electrode entirely, that of the depletion region charge
(aQLg.ext)
is partially coupled to the gate
and the left is imaged to the edge of drain-side depletion region. This effect can be explained
based on a charge-control model commonly used to analyze a transit delay for base-collector
junction in a Bipolar Junction Transistor (BJT) [118]. As described in equation (5.2), the
incremental change of gate voltage (aVgs) increases the charge in the depletion region
(aQLg.ext),
which reduces the net positive charge in the drain-side depletion region. Due to this effect, the
slope of the electric field in the depletion region is reduced and the depletion region width (Lg.ext)
is expanded to support the same drain voltage as shown in Figure 5-4(a). In the base-collector
125
junction in BJT, the electric field is one-dimensional and the change of the charge at the edge of
the depletion region caused by the expansion can approximate to 50 % of aQLg.ext as shown in
Figure 5-4(b). Thus, only left 50 % of aQLg.ext needs to be supplied from the base. In the case of
the HEMT structure, although the electric field is two-dimensional, distribution of the lateral
electric field in the drain-side depletion region under high drain bias is very similar to that of
base-collector junction, which makes it possible to use the same approach. Here, it is assumed
that (1/a) of the total change of the depletion charge is imaged to the gate (or supplied from the
source) and the remaining portion is coupled to the drain-side depletion region edge. (In the case
of the base-collector junction in BJT, a= 2 [118].) There are several studies that use a of 2 in the
HEMT like BJT [119], while some others do not take into account the effect of the partial
coupling of the depletion region charge (a= 1) [112], [120], [121]. Also, Chung et al. claims that
a in the HEMTs is 3 based on the result from the simplified two-dimensional poison equation
solver [122].
Based on this, a small-signal equivalent circuit model including the gate extension effect can be
derived as shows in Figure 5-5 [123]. It is shown that of the gate extension capacitance is
connected between intrinsic gate and source nodes, so that it is included in the gate-to-source
capacitance (Cgs). That is, the gate extension effect can be captured from the Cgs. However, it
should be noted that the expanded gate extension region does not only increase Cgs through
(l/a)-CLg.ext
component, but also reduces the gate-to-drain capacitance (Cgd) by increasing drain-
side depletion region and this is why the Cgd decreases with increasing drain bias. However,
since the effect becomes minimal as the Lg.ext increases and the dependence due to the fringing
capacitance (Cgd.frin) is affected by device geometry, it is not included in the general model
shown in Figure 5-5.
126
Rg
Rd
CgCs
''T
Csfrin
D
1/a
ICgs~int
n~
-
CLg.exR
x
sd
~T
1 /igsd)
C
RS
gm.int exp(-jw( r
+
1/a x CLg.extlgm.int))
S =
Figure 5-5. Small-signal equivalent circuit model including the gate extension effect.
Based on the derived small-signal equivalent circuit model, the total device delay can be
expressed by the following equation.
(5.3)
Tt = Tint + Tfrin + Tcrain + Tpar
Cgs.int + Cgd.int
Cgs.frin + Cgd.frin
9m.int
9m.int
+(Rs + Rd) - [Cgd + (Cgs +
Cgs.int + Cgs.frin + (1)
9
- CLf.ext
C
+ 1
CLg.ext
a
9m.int
9)sd
9m.int]
+ Cgd.int + Cgd.frin
9m.int
m.int
+(Rs + Rd) - [Cg + (Cs + Cgd) -JgJ
9m.int]
127
gAd
Cgs
C+
9m.int
9m.int
9m.int]
In the above equation, the total delay can be separated by three components as follows:
C
T1 =
gs
(5.4)
9m.int
Cgd
S=
3=
(5.5)
9m.int
(Rs + Ra) - [Cga + (Cgs + Cga) -
sd
9m.int]
(5.6)
Figure 5-6 shows how each delay component changes depending on the drain voltage. As
explained above, with increasing drain voltage, mj increases due to the increase of Cgs while the
two other delay components decrease because of the decrease of
Cgd.
Since Cgs.int and Cgsfrin of
devices with good electrostatics stay almost constant in the deep saturation regime, the increase
2.1
0.12
0.18
A
2
0.16-
T1i
En
0.
(U
0
T2
5.0.14
-
0.1
C%
1.9
(U
0
UC%
Z 0.12 -
Ie
0
1.8
0.1L = 220-nm
1.7
U,
0.
4
6
8
0.08
C^
A
L0 = 220-nm
L= 220-nm
10 12
Effective VDS(V)
(a)
0
0.08-
4
6
8 10 12
Effective VDS(V)
(b)
0.06
4
6
8
(c)
Figure 5-6. Change of each delay component with increasing drain voltage. (a)t 1 1, (b) t 2 , (c)
128
10 12
Effective VDs(V)
-[.
of Cgs (= Cgs.int+Cgs.fin+(l/U)-CLg.ext) with increasing drain bias is mainly due to the increase of the
CLg.ext
caused by expansion of the gate extension region. Based on this, the drain delay can be
extracted by using the Cgs /
gm.int at
different drain bias. Since only Cgs is used for the extraction,
the error caused by opposite behavior of Cgd can be avoided. On the other hand, N. Moll's
method uses the total device delay for drain delay extraction [40]. Since the drain delay extracted
by N. Moll's method includes all the effects caused by change of Cgs and Cgd as a function of the
drain voltage, there is a difference between the extracted value and the real electron transit time
in the extension region. Especially, the value extracted from this method includes the effect of
the reduced parasitic delay (Cgd - (RS+Rd)) resulting from the lower Cgd at higher drain bias, thus
underestimating the actual transit time. In addition, the amount of this underestimation becomes
larger with higher parasitic source/drain resistances. To avoid this problem, reference [117]
extracts the drain delay after first removing the effect of the parasitic delay (Cgd - (Rs+Rd)) from
the total device delay. However, the reported delay still includes the Cgd /
gm.int
component,
which decreases with the increasing drain voltage. Thus, in order to capture the true electron
transit time caused by the expanded gate extension, we propose that the drain delay should be
extracted directly from Cgs /
gm.int.
5.2.3. Comparison to other extraction methods
The proposed drain delay extraction method was applied to experimental devices fabricated at
MIT. The transistors used in this study had a 10.8 nm In 0.13Alo. 83Gao.0 4N top barrier layer, a 0.5
nm AlN interlayer, and a 1 pm GaN buffer grown by metal organic chemical vapor deposition
(MOCVD) on a SiC substrate. The gate-to-drain distance of these devices was in the 300-500 nm
range, which was much larger than the expected gate extension length. A 30 nm A12 0 3
129
0 Ml: Total delay
2.4
A M2: Total delay * M3: C
2.2
Cgd
(R, + Rd)
/ gmnt
A
000
~2-
0
2
4
6
8 10
Effective V DS(V)
12
Figure 5-7. Drain delay extracted from 220-nm gate length device based on the different extraction
method.
passivation was applied to minimize surface trapping [57], [109]. Small signal-circuit parameters
of the devices were extracted analytically by using the measured S-parameters.
Figure 5-7 shows the drain delay, as extracted by three different methods, in devices with 220nm gate length. Method I uses the total device delay like N. Moll method, while method 2 is
based on the delay without the parasitic delay (Tt - Cgd - (Rs+Rd)) following reference [ 117].
Finally, method 3 is the one proposed in this study, and only uses Cgs / gm.int for the extraction.
The extracted drain delay rate (rdrain), obtained from the linear interpolation, is highest in method
3 because it excludes the effect of the Cgd on both the intrinsic and the extrinsic devices and only
captures the effect of increase in the electron transit time. There is about 26 % increase of the
extracted drain delay rate compared to the conventional N.Moll method. Also, considering that
the devices used in this study have very low parasitic resistances thanks to the combination of
low sheet resistance heterostructure, scaled source-to-drain distance and contact regrowth, the
difference can be larger in the devices fabricated with conventional process.
130
* Ml: Total delay
A M2: Total delay - Cgd (Rs + Rd)
ISM3: C
1.4
-
1.2
1[
0
0.
0
0
,
/ag
10 .
0JA
0.8
Cu
0
0
0.6
0.6
0.4
Lg=120-nm
C
Cu 2
4 6 8 10 12
Effective VDS (V)
L 60-nm
2 4 6
8 10 12
Effective VDS (V)
(b)
(a)
Figure 5-8. Drain delay extracted from the short channel devices. (a) Lg=120-nm, (b) Lg=60-nm.
5.3. Drain delay in short channel devices
5.3.1. High extracted drain delay rate
The drain delay becomes more important in the deeply-scaled devices because the relative
portion of drain delay becomes larger due to the lower total device delay. It should be noted that
independently of what specific extraction technique is used, the extracted drain delay rate value
in the shorter gate length device is larger than that in the longer channel device as shown in
Figure 5-8. In the case of the other extraction methods, it is challenging to analyze the cause of
the increase in drain delay in the short channel devices because there is no clear theoretical
connection between the extracted values and device physics. On the other hand, we believe the
proposed method can provide the theoretical understanding about the phenomenon. One possible
hypothesis to explain the high drain delay rate in the short channel devices is that the gate
extension is faster in these devices compared to the long channel devices. To check whether it is
131
75
>
E
E--
UU,
25--
L,=220-nm
-- -
L,=330-nm
15,-
00-I
-LL==23-nm
U)0
Ll =69- m
L060 -n
to -50
-75
Ve foy= 0.6 V
5
m 0.8
9
7
Effective VDS(V)
5
(a)
9
7
Effective VDS(V)
(b)
Figure 5-9. Change of (a) Cgs and (b) gm.int with increasing drain voltage in different gate length devices.
correct, the Cgs is extracted at the same effective gate overdrive (VeTOV= VGS - ID X Rs - VT)
with increasing drain voltage. According to the small-signal circuit model shown in Figure 5-5,
Cgs should increase with increasing the drain voltage because of the increased gate capacitance
associated to the gate extension ((l/ct)-Cg.ext). Figure 5-9(a) shows the difference between the
Cgs at different drain voltages and the Cgs extracted at VDS= 5 V in different gate length devices.
In the long channel devices (Lg > 200 nm), the extracted Cgs increases with increasing drain
voltage, which agrees with the model. However, as the gate length scales down, the trend
changes and the capacitance decreases with VDS, which shows that the higher drain delay rate in
the short channel devices is not caused by the faster gate extension.
Actually, the origin of the higher drain delay rate is the significant degradation of the intrinsic
transconductance as shown in Figure 5-9(b). This can be explained by the high lateral electric
field effect in short-channel devices, which limits the electron confinement in the channel and
results in the spreading of the channel electrons. This increases the punch-through current and
132
degrades the gate controllability at high drain bias, which results in the drop of the Cgs and
gm.int.
(The drop of gm in the short channel devices is also observed in DC measurements as shown in
Figure 5-10.) That is, the higher drain delay rate in the deeply-scaled devices is not originated by
the faster expansion of the drain-side depletion region, but by additional delay caused by the
degradation of the electrostatics at high drain bias. This delay component makes it more
challenging to accurately extract the drain delay in the short channel devices. To quantify this
effect, the measured drain delay in short channel devices is compared to the drain delay extracted
from devices where the gate length is long enough to suppress the degradation of the gate
controllability at the high drain bias as shown in the Figure 5-11 (i.e. Lg= 2 2 0 nm). At the shortest
gate lengths in the experiment, the delay due to poor channel modulation can account for up to
35% of the total "perceived" drain delay in the device. This result shows that decrease in the
speed of the deeply-scaled devices at high drain bias is originated from two factors: 1) additional
delay caused by the degradation of electrostatic, 2) real drain delay resulting from the gate
extension.
0.8-
.
00.
0.8
VDS
o=5
AVDS=
2V
EUO
E-E
0.46
EE
0.
E0.
- -0.21
0.2-- --L = 40-nm
-1.3
- 9 V,
-3.8
-313
-2.8
L = 60-nm
-. 1
-3.6
-3.1
-2.6
L = 330-nm
-4.6
-3.1
-2.6
VGS (V)
VGs (V)
VGS (V)
(a)
(b)
(c)
Figure 5-10. Change of DC gm with drain voltage. (a) L,=40-nm, (b) Lp=60-nm, (c) L,=330-nm.
133
-2.1
CL
Gate controllability degradation
with increasing VDS
0.06
0.05
4)0 .0 4
......... ........
0.03
Drain Delay Rate 0.038 ps/V
0
100
200
300
L9 (nm)
400
500
Figure 5-11. Extracted drain delay rate as a function of the gate length. The drain delay rate increases
rapidly as the gate length scales down below about 100 nm.
5.3.2. Suppression of gm.int Degradation at High Drain Bias
To improve the speed of short channel devices at high drain bias, it is important to reduce the
additional delay component resulting from the gm.int decrease as shown in the previous section.
The decrease in gm,.int with increasing drain voltage is caused by the degradation of the electron
confinement in the channel, which increases punch-through current. Since the punch-through
current flows through the path under the 2-DEG channel, the gate has a poor control of this
current. The portion of the punch-through current among the total drain current increases with
increasing the drain voltage, which decreases the gm,.it.
The gm.int degradation at high drain bias is basically due to short-channel effects. As explained
in chapter 3, it is generally accepted that top barrier scaling is the most effective method to
suppress short-channel effects. However, it is challenging to solve this problem only by scaling
the top barrier thickness due to the following reasons. First, top barrier scaling reduces the 2DEG charge density in the access region and increase the sensitivity to surface states, which
increases drain delay by expanding the depletion region width. Second, it is difficult to suppress
134
Sourc
ra
Passivation Gate
1The
-
-----
->SCC7/
<<095
0
Punch-through current
GaN
E
Sour
Passivation Gate
0.9
0.85
Drain
80-nm
L
Channel current
1
E
InGaN
0.8
4
GaN
(a)
6
8
Effective V DS(V)
10
(b)
Figure 5-12. (a) Blocking the path of punch-through current with structure of vertical channel scaling. (b)
Comparison of the gmin, degradation at high drain bias between the devices with vertical GaN channel
scaling and control structure.
the punch-through current under the ON-condition with the electric field from the gate electrode.
Since the 2-DEG channel is not depleted, most of the gate electric field is screened by the
channel electrons, so that the field cannot reach the region where the punch-through current
flows.
To overcome the above limitations, vertical GaN channel scaling should be combined to the top
barrier scaling [98]. As explain in the section 3.5.3, by inserting an InGaN layer underneath the
GaN channel and placing it close to the top barrier interface, the spread of channel electrons can
be limited as shown in Figure 5-12(a). Figure 5-12(b) shows the intrinsic transconductance (gm.int)
in sub-100 nm gate length devices with 8.3 nm top barrier and 10 nm GaN channel thickness.
Compared to the devices on the control heterostructure (10.8 nm top barrier and no InGaN back
barrier), the decrease in gm.int at high drain bias is effectively suppressed. Since the electrons
cannot go over the barrier formed by the InGaN layer, the path for the punch-through current is
135
1.4
Lg= 80-nm
1.2-
Control device
0.8
0.4
Q/
0.6
0.41
0
GaN channel scaling
2 4 6 8 10 12
Effective VDS (V)
Figure 5-13. Comparison of the drain delay rates in the 80-nm gate length devices with vertical GaN
channel scaling and control structure.
constrained, which reduces the gmint drop. This effect impacts the device speed and the increase
of the Cgs / gm.int ratio when increasing the drain voltage is reduced compared to the control
devices as shown in Figure 5-13. This result shows that improvement in charge confinement can
contribute to the improvement of frequency performance at the high drain bias range. However,
it should be noted that 10 nm GaN channel thickness is not enough to prevent serious
degradation of gm.int in deeply-scaled devices (Lg < 50 nm) at high drain bias. Heterostructures
with thinner GaN channel thickness [98] or high Aluminum-composition AlGaN back barrier
[94], [95], [117] should be used. In addition, N-face structures with a natural back barrier would
also be good candidates for wide bias high frequency operation [124], [125].
5.3.3. Scaling gate-to-drain spacing
As discussed in the previous section, a proper heterostructure design can reduce the degradation
of the device speed at high drain bias by minimizing the additional delay resulting from the
136
degradation of electrostatic. In this case, the operating frequency under high drain bias is mainly
limited by the real drain delay originated from the gate extension. To overcome this limit, the
expansion of the drain-side depletion region should be suppressed, which can be achieved by
scaling gate-to-drain spacing [125]-[127]. That is, by putting the highly-doped drain contact near
the gate electrode, the maximum width of drain-side depletion region can be physically defined.
Once the edge of the depletion region reaches the drain, the effective gate length cannot be
increased further in spite of the increased drain bias and the decrease of the device speed starts to
slow down. However, since additional potential drop with increasing the drain bias needs to be
supported in the fixed depletion region, the electric field in the region increases faster than the
devices with long gate-to-drain spacing. Thus, there is a tradeoff between device speed and
breakdown voltage in this approach. To improve the device speed at high drain bias without
seriously compromising the breakdown voltage, the gate-to-drain spacing should be properly
designed. For this, accurate estimation of the depletion region width is necessary.
The effective gate extension length (Lg.ext) or drain-side depletion width can be estimated by
using the drain delay rate. Based on the equation (5-2) and small-signal equivalent circuit model
shown in Figure 5-5, the drain delay rate
(rdrain)
extracted from the Cgs / gm.int method can be
interpreted as shown in the following equation.
= a 9m.int)
aVs
1
aCgs
aCLg.ext
_
9m.int
9m.int
gVs
9Vds
A g.ext
Vsat
(57)
dVds
From equation (5.7), the depletion region width as a function of the drain bias can be calculated
as follows:
137
Lg.ext(VDs)
a
Vsat * rdrain'
To estimate the depletion width with above equation, a,
Vsat
(5.8)
VDS(
and
rdrain
should be determined. As
explained in section 5.2.2, the value of a in Field-Effect Transistors (FETs) varies from 1 to 3 in
the literature [112], [119]-[121], [128]. Since the drain-side depletion region in FETs becomes
similar to base-collector junction in BJTs as the depletion region width increases [118], the a of
2 is assumed in this work [123]. In the case of vsat, 1.5
average electron velocity (Ve) of 1.4 ~ 1.5
x
x
107 cm/s is assumed because the
107 cm/s is generally measured in the properly-
designed deeply-scaled GaN HEMTs [99], [129] and the average velocity in the these shortchannel devices is close to the saturation electron velocity
(vsat).
Finally,
rdrain
can be extracted
from the Cgs / gm.int method in devices whose gate length is long enough to avoid the effect of the
gm degradation and the gate-to-drain distance is long enough to prevent the expanded depletion
region from hitting the drain contact at high drain bias.
In order to apply this estimation method experimentally, devices were fabricated on a
heterostructure consisting of 10.3 nm Ino. 13A10. 83Gao.0 4N top barrier, 0.5 nm AlN interlayer, and 1
ptm GaN as shown in Figure 5-14(a). The basic fabrication process of the devices was consistent
with that of the devices described in the section 4.2.3 [108] and 30 nm A12 0 3 passivation was
applied. The main difference in the process was the variation of the gate-to-drain spacing
between 100 nm and 550 nm. First, the drain delay rate
(rdrain)
of 0.04 ps/V was measured from a
device with about 225 nm gate length and gate-to-drain spacing (Lgd) of 550 nm. Based on the
measured drain delay rate, the drain-side depletion width in the devices can be estimated based
on the following equation.
138
200
20 L g 80-nm
Gate
0.
.
L =100 nm
04
S
n+ InGaN
G
Phwem
d~de
2--------LLgd 350
120
30nnm --------
n+InGaN
---- -GaN
100,
0%24
6 8 10 1214
Effective V
(V)
(a)
(b)
Figure 5-14. (a) Schematic and top view SEM image of the device with scaled gate-to-drain spacing. (b)
Comparison of the f1 trends at high drain bias between devices with Lgd= 100-nm and Lgd= 350-nm.
Lg.ext(VDS)
'
rsatr
V
12 (nm/V) VDs
(5.9)
To check the accuracy of the estimation, microwave characteristics of 80-nm gate length
devices with gate-to-drain spacing of 100 nm and 350 nm were measured with varying drain bias.
Figure 5-14(b) shows the comparison of the maximum f1 of these devices in the wide drain bias
range. In the device an Lgd of 350 nm, the fr keeps decreasing with almost the same slope as the
drain bias increases. In contrast, in the device with Lgd of 100 nm, the decrease of the fr starts to
slow down for drain biases above about 8 V. This is because the edge of the drain-side depletion
begins to hit the highly-doped drain contact, which limits the further expansion of the depletion
region. Similar trend is also observed in Cgd. With increasing the depletion region, Cgd
continuously decreases as shown in Figure 5-15(a). However, once the expansion of the
depletion region begins to be confined, the change in capacitance slows down as shown in Figure
139
0.04
L9= 80-nm
L0 0.03-!::
E
E
GaN -
Lgd=
-- 0.02
350-nm
FAr
Lgd= 100-nm
Cgd
S
A1203
G
GaN
D
2
0.01
0
gx
2
(a)
8 10 12
4 6
Effective VDS (V)
(b)
Figure 5-15. (a) Expansion of the depletion region width and (b) change of
Lgd=1
00
14
Cgd
in the devices with
nm and 350 nm.
5-15(b). Equation (5.9) gives a depletion region width of 96 nm at VDS= 8 V which is very close
to the Lgd of the device. This result confirms that the estimation based on the extracted drain
delay can provide a good first-order estimation of the depletion region width and it can be very
useful to design devices with optimum gate-to-drain distance.
5.4. Conclusion
In this chapter, the origin of the decrease in the frequency performance of the deeply-scaled
GaN HEMTs at high drain bias was investigated. In order to analyze it systematically, the smallsignal equivalent circuit model including the drain delay was derived and a new extraction
method (Cgs / gm.int method) based on the model was proposed. Compared to other methods
reported in the literature, the proposed method provides a solid theoretical background, which
allowed us to link the extracted results directly to the physics of the device. Also, it provided
more accurate estimation of the drain delay rate by excluding the dependency on Cgd or Rs/Rd.
140
In addition, it was found that regardless of the extraction method the drain delay rate became
higher as the gate length scales down. The analysis based on the proposed method showed that
this increase results from the decrease in the gm.int at high drain bias. As the drain bias increases,
the electron confinement in the channel is degraded and the punch-through current becomes
larger. The increase in the relative portion of the punch-through current decreases the gate
modulation efficiency on the total drain current, which causes the decrease in the gm.int at high
drain bias. This result showed that the rapid decrease in the speed of the deeply-scaled devices at
high drain bias does not results from only real drain delay, but also additional delay caused by
the degradation of electrostatic.
Based on the analysis, technologies to reduce each delay component (i.e. additional delay due
to degradation of gate electrostatic and real drain delay) were investigated to improve the
frequency performance at high drain bias. First, to suppress the decrease in gm.int, both top barrier
and channel thickness were scaled down, which effectively reduced the punch-through current
and improved the electrostatic. Thanks to this effect, the devices with vertical scaling showed the
expected lower drain delay rate compared to the control devices. As another approach to improve
device speed at high drain bias, the scaling of gate-to-drain spacing was studied. By forming the
highly-doped drain contact close to the gate electrode, the expansion of the drain-side depletion
region was limited. The fixed depletion width prevented increase of the drain delay, which
slowed down the decrease of the device speed with increasing drain bias. In addition, the
expansion of the depletion width was estimated from the drain delay rate and it was confirmed
with experimental data. This can be very useful to design devices with scaled source-to-drain
spacing and to analyze their breakdown voltage.
141
Chapter 6. Nonlinearity of Deeply-Scaled GaN HEMTs
6.1. Introduction
In previous chapter, the delay components which limit the maximum speed of GaN HEMTs at
high drain bias were discussed. For high speed operation under a wide drain bias range, it is
required to minimize the increase in the delay caused by the gate extension and degradation of
the gate controllability. At the same time, in high power RF applications, maintaining the high
frequency performance at high gate bias is as important as doing it at high drain bias because it
allows a large dynamic input signal range. To achieve this, it is critical to maintain a high
transconductance (gm) under a wide gate bias range.
According to basic device physics for ideal transistors, the gm should increase with increasing
the gate voltage and then it should become flat after it reaches its maximum point [130]. The
0.8
VDS=
0.6
E
E
250
5V
5V
-
-
200
L,= 120-nm
L 9 70-nm
VDS=
-
-Lg=
70-nm
150
0.4
N.
0O
-
0.2
-5
L,= 230-nm
-4
-3 -2
VGS (V)
-1
100
Lg= 120-nm
50
-i
0
(a)
M
L= 230-nm
-4
-3
-2
VGS (V)
(b)
Figure 6-1. Nonlinearity of (a) g,, and (b) fT in GaN HEMTs with different gate length.
142
-1
0
current gain cutoff frequency (fT) also follows this trend, so that ideally it should be almost
constant after it reaches the maximum point. However, conventional GaN HEMTs show a
nonlinear behavior of the extrinsic transconductance, which becomes more serious as the gate
length scales down as shown in Figure 6-1(a). In the deeply-scaled HEMTs, gm reaches its
maximum value at 30-50 % of the maximum drain current level and then it decreases quickly.
Due to this nonlinearity in gm, the
fT
also drops quickly as the gate voltage (or drain current)
increases above the maximum gm point as shown in Figure 6-1(b). This chapter studies the gm
nonlinearity issue in deeply-scaled GaN HEMTs and solves the problem by developing a novel
nanowire channel device structure.
6.2. Nonlinearity of g. in GaN HEMTs
6.2.1. Current understanding in the literature
Several theories have been proposed to explain the gm drop at high drain current (or high gate
voltage) in GaN HEMTs. For example, Liu et al. claims that the increased vertical electric field
at high gate bias pushes the electrons in the channel toward the interface between GaN and top
barrier layer (or interlayer), which increases the interface scattering and reduces the effective
electron velocity [131], [132]. Actually, this is one of the main reasons for the gm drop in Si
MOSFETs [133], but it is doubtful that the same explanation can be applied to GaN HEMTs
because the AlGaN/GaN heterostructure has a high quality interface thanks to in-situ growth. In
addition, the gm drop is observed in both GaN heterostructures grown by MBE and MOCVD in
spite for sharper interface in the structure grown by MBE [22], [33], [134], [135].
Another theory claims that self-heating effect results in the decrease in gm at high drain current
level [136]. The current of GaN HEMTs on Si substrate decreases at both high drain current and
143
5 -
3
4U
'
intrin
-
i
E
3
et]2
(b)a
g1.0
-I
27
1
C
(a
(b)
%
0 -0
0
200
400
600
IDS
igdan
800
1000
1200Vg(Ot
(mA/mm)
(a)
reio
beas
h
hne0tmeaueicese
1otg
0.0
VS(ot
(b)
u
ohg
oe
Figure 6-2. Two different explanations about origin of g. nonlinearity. (a) Non-linear source access
resistance [ 139]. (b) Optical phonon scattering [143].
high drain voltage region because the channel temperature increases due to high power
dissipation and low thermal conductivity of Si substrate. However, the gm drop issue is still
observed in devices fabricated on SiC substrate, which indicates that the self-heating effect
cannot be the main reason [33], [88], [137], [138].
One of the most promising explanations of the drop in gm is the "non-linear access resistance
effect". Palacios et al., DiSanto et al., and Trew et al. proposed that the increase of the source
access resistance with drain current is the cause of the gm drop in GaN HEMTs as shown in
Figure 6-2(a) [139]-[141] . Actually, Greenberg et al. first reported this effect in InGaAs HFET
and predicted it can be the important limiting factor in HFETs with large insulator band gap
[142]. Finally, Fang et al. argued that the emission of optical phonons at high drain current levels
results in the decrease of the gm [143]. That is, with increasing the gate bias, the number of
electrons having enough energy to emit optical phonon increases, which decreases the average
electron velocity in the channel due to the increased phonon scattering. According to this
144
explanation, the gm drop is not the effect of the extrinsic device component, but an intrinsic
property of GaN as shown in Figure 6-2(b).
These two explanations (i.e. increase in access resistance and emission of optical phonons) also
agree to the trend that the gm drop becomes more serious as the gate length scales down.
However, the intrinsic origin of the gm drop, claimed in each theory, is completely different. The
former is the extrinsic source resistance, while the latter is an intrinsic device property. Thus,
finding the main cause of the gm nonlinearity is important not only for understanding the
phenomenon, itself, but also for evaluating the potential of GaN HEMTs accurately.
6.2.2. Self-aligned GaN HEMTs
One of the direct methods to evaluate the intrinsic GaN device performance is to make a selfaligned device structure. In the perfect self-aligned device without access region and contact
resistance, there is no effect of extrinsic resistances, so that intrinsic device performance can be
exposed. In 2012, Shinohara et al. demonstrated a short-channel GaN device with very small
-
Lal - - d A n m
-- -
nm3
223
Lg|La=6010
L
HOavIly-doped n-GN ohmic
concts regrown by MBE
7irD43
ir 3D -E21
35
30
o p
0 Lg;Ls . 60140 nni
s.4
VRw*V772in
SiN L,_
D- 2
20--5s
E2
--
A10LUNDH iE_____
(a)
Vds (V)
V9(V)
(b)
(c)
Figure 6-3. (a) Device structure of self-aligned GaN HEMTs and DC (b) output and (c) transfer
characteristics of the device [127].
145
access region by using n+ GaN contact regrowth technology. The device shows a flat extrinsic gm
and very high current (above 3 ~ 4 A/mm) as shown in Figure 6-3 [127]. This result supports the
hypothesis that the gm drop in the GaN HEMTs is caused by extrinsic causes and the intrinsic
devices have a potential to provide a flat gm and very high current. However, since the selfaligned structure with almost no access region was used, explanation about the gm drop in
reference [127] focused on the current supply from the regrowth contact rather 2-DEG access
region and this cannot apply to the conventional non-self-aligned devices having access region
between contact and intrinsic channel. In addition, a significant decrease of the breakdown
voltage was observed in the reported devices because there is no access region between gate and
drain, which can support a high drain voltage.
6.3. Nanowire channel GaN HEMTs
6.3.1. Limitation of source access region
Figure 6-4(a) shows the schematic of the non-self-aligned short channel GaN HEMT under
current saturation regime. At high gate bias, the maximum current drivability of the intrinsic
device can be approximately estimated as
'D.max.int =
- q
where q is electron charge (1.6
2),
x
ns
-
Vsat
~
4
-
10-19 C), ns is 2-DEG sheet charge density (1.5 ~ 2.0
and vsat is saturation velocity (1.5 ~ 2.0
x
(6.1)
6 A/mm
x
10" cm~
107 cm/s). In this estimation, vsat is used for the
electron velocity because the electric field in the intrinsic channel is high enough to reach the
velocity saturation regime (E >> 100 kV/cm). In the case of the source access region, however,
146
Source access region
S
........
.. Intrinsic device
.
G
(a)
Region of
interest for r,
3.0 ( _ A-
300
-50
VDs = 10 V
I
250
/-
-40
-II
4L
0,
E
200
A
2,5 - AA
k,
-30
150
'C
-
-20
-
W
'/
100
*-
10
.5
50
-10
Monte Carlo simulation
(after [6)
a Pulsed IVmeasurements
,m
A
N
0
n
-8
-6
-4
-2
GaAs-Oike transport with
00and v
0
0
50
100
150
from GaN
200
250
Electric Field (KV/cm)
VGS (V)
(b)
(c)
Figure 6-4. (a) Cross-section schematic of short channel GaN device under saturation. (b) Simulation of
longitudinal electric field and resistance in the source access region [139]. (c) Electron velocity
depending on electric field in the different transport model [139].
the electric field is smaller as shown in Figure 6-4(b), limiting the electron velocity only in
"quasi-saturation" regime (10 kV/cm < E <K 100 kV/cm) [139]. In other semiconductors like
GaAs, it cannot be distinguished from the standard saturation because the velocity saturation
occurs under much lower electric field as shown in Figure 6-4(c) [139]. In GaN HEMTs,
nonlinear relation between electric field and electron velocity in the quasi-saturation limits the
current supply to the intrinsic device and increases the source access resistance with increasing
147
the drain current. Moreover, once the device goes into saturation, the drain side channel potential
is almost fixed and most of the additional drain voltage drop occurs in the depletion region
formed between gate and drain. Thus, it is not easy to increase the electric field in the source
access region. Due to this effect, the current of the device at the high gate bias is limited not by
the intrinsic device, but by the source access region.
In order for the intrinsic device to recover the controllability, the current supply from the source
access region should be enhanced and there are two possible approaches in non-self-aligned
devices: 1. increase of the electron velocity of the source access region, 2. increase the number of
the electrons in the source access region with respect to the intrinsic channel. In this study, the
second approach is selected and it is realized by using a nanowire channel structure.
6.3.2. Device structure
Figure 6-5 shows the device structure of the nanowire channel GaN HEMT developed in this
study [ 144]. In order to overcome the limitation of the current supply in the source access region,
the nanowires are formed only under the sub-100 nm gate electrode in a self-aligned way and the
0
A
-E
I
IIIA
Figure 6-5. Device structure of the nanowire channel GaN HEMT.
148
(a)
(b)
(c)
Figure 6-6. Previous studies about nanowire channel GaN devices. (a) [145], (b) [146], (c) [147].
access region is, therefore, maintained as in the planar device. This is very different from other
nanowire device studies where the nanowires are formed along the entire area between source
and drain, effectively working as multiple nanowire transistors in parallel as shown in Figure 6-6
[145]-[147]. On the other hand, in the device structure used in this study, the source access
region has higher current capability than the channel due to the larger effective width, so that it
can act as a more ideal source to the intrinsic nanowire-patterned transistor. A similar device
structure was demonstrated in [148], [149], but the device had relatively long channel length and
low drain current, which made the non-linearity behavior not an issue. Also, it is very
challenging to scale down the gate length by using the process described in [148], [149] because
the alignment process between nanowire channel and gate should be conducted in a separate
lithography step. In this study, a new fabrication process was developed to demonstrate nanowire
channel device with sub-100 nm gate length.
6.3.3. Device fabrication
The wafer used in this study was grown on a SiC substrate by metal-organic chemical vapor
deposition (MOCVD). The heterostructure consisted of 9.8 nm Ino. 17A10. 83N lattice-matched to
149
GaN and 1.0 nm AIN interlayer as the top barrier, and 1.8 pm GaN buffer. In a sample with 30
nm A12 0 3 passivation, a 2-dimentinal charge density of 1.76 x 1013 cm-2 , an electron mobility of
1233 cm2/V-s, and a sheet resistance of 288 Q/o were obtained from van der Pauw Hall
measurements.
Gate pattem
S13 N4Nanowire pattem
(a)
(b)
(c)
Gate pattem
Gate pattem
SIN 4 Nanowire pattern
GaN
(d)
(e)
(g)
(h)
(f)
Figure 6-7. Fabrication process of the nanowire channel GaN HEMT. (a) Mesa isolation and ohmic
contact formation, (b) Si 3N 4 deposition and nanowire patterning with e-beam lithography and selective
dry etching with CF 4 plasma, (c) gate e-beam patterning with ZEP520 resist, (d) top barrier and GaN
channel dry etching with BCl 3/Cl 2 plasma, (e) Si3N4 pattern removal with dry etching with CF 4 plasma,
(f) gate metal deposition and lift off, (g) removal of SiN 4 pattern on the access region with BOE wet
etching, (h) Al 20 3 passivation layer deposition with ALD.
150
The device fabrication process begun with the selective growth of n+ InGaN/GaN source/drain
contact layers (R,= 0.2 Q-mm) which was described in the chapter 4. After mesa isolation as
shown in Figure 6-7(a), the 50 nm thick Si 3N4 was deposited by plasma-enhanced chemical
vapor deposition (PECVD) and the nanowire patterns were formed through the e-beam
lithography with ZEP520 resist and subsequent dry etching in CF 4/0 2 plasma as shown in Figure
6-7(b). Figure 6-8(a) shows SEM image of the Si 3N4 nanowire patterns on the device. Then, a
(a)
(b)
Figure 6-8. Top view SEM image of (a) Si3N 4 nanowire pattern and (b) device after gate lift off process.
Only under the gate, the channel is etched.
0
r. 10
-20
--------------- ---------------------------------
----------- -----
....... ....
----------------
...
......... .....
------------------
0
-30
-- -------- ......
C
200
---
400
600
Distance (nm)
(b)
(a)
Figure 6-9. (a) SEM and (b) AFM images of the test structure after removing gate metal.
151
800
second e-beam lithography was conducted to define the gate electrode as shown in Figure 6-7(c).
By using e-beam resist as a mask, the top InAlN and AlN barrier layers, as well as the first few
nanometers of the GaN channel were etched to a 20-30 nm depth by BCl 3/Cl 2 plasma dry etching
as shown in Figure 6-7(d). During this etch process, the Si 3N4 nanowire patterns protected the
region where the nanowire channel would be formed. After the channel etching, the Si 3N4
nanowire hard-mask was removed with CF 4/0 2 plasma to expose the protected channel area as
shown in Figure 6-7(e).
Then, a Pt/Au gate metal was deposited and lifted off using the
remaining e-beam resist as shown in Figure 6-7(f). The SEM image in Figure 6-8(b) shows the
top view of the device after gate metallization. Since both nanowire channel and gate electrode
were form based on the same e-beam resist mask, they were perfectly aligned. In order to
confirm the formation of the isolation trench under the gate, SEM and AFM images were also
obtained after removing the gate metal in the test structure. As shown in Figure 6-9, about 20-30
nm deep trench was formed only under the gate region while the channel region with Si 3N4
pattern was protected. After removing the Si 3N 4 nanowire hard-mask from the access region with
BOE wet etching, an oxygen plasma was applied to this region as shown in Figure 6-7(g).
Finally, a 30 nm A12 0 3 passivation layer was deposited by atomic layer deposition as shown in
Figure 6-7(h). For comparison, conventional planar devices were also fabricated right next to the
nanowire channel transistors by skipping the Si 3N4 nanowire patterning step.
6.3.4. DC characteristics
The DC transfer and output characteristics of the Lg=70-80 nm nanowire channel device and of
the conventional planar transistor are compared in Figure 6-10. The DC characteristics of the
nanowire channel device is normalized with respect to the effective channel width (Weff =
152
0-
E
2
.4
L = 70-80 nm
L = 70-80 nm
3 GS -5 ~ 1 \
VDS= 3 V
nanowire
06
1
E
....
planar
2
E 0.5
-5
"0
4
-2
-1
0
0
0
1
VGS (V)
(a)
2
3
V
(V)
(b)
Figure 6-10. DC (a) transfer and (b) output characteristics of 70-80 nm gate length nanowire channel
device and conventional planar device. The nanowire channel device characteristics are normalized
based on the effective channel width.
Wchannel x Nwire,
where
Wchannel
is nanowire channel width and Nwire is total number of wires) in
order to compare the intrinsic device performance. The device has 490 nanowires of 88-nm
width (Weff = 43.1 Vim) and the spacing between nanowires (Wisoi) is I 10-nm. As shown in
Figure 6-10(a), the nanowire channel device has much flatter extrinsic transconductance (gm)
than the planar device thanks to the relatively larger current drivability of its source access
region. That is, even at high drain current, the increase in the access resistance is suppressed, so
that the voltage drop across the source access region remains small.
In order to confirm this, the source access resistance was measured as a function of drain
current by using the gate current injection method [150]. As shown in Figure 6-11(a), constant
current was applied to the gate electrode and the gate voltage was measured as the drain current
increases. Since the gate Schottky contact is forward biased and the gate current is fixed, the
voltage drop across the gate Schottky contact is constant. Thus, the gate electrode voltage
follows the channel potential. The source resistance was obtained by differentiating the gate
153
G
Eplanar
ID
S
Q
D
VIDS
w
Ra= dVGS/ dID
nanowire
0
0
0.5
1.5
1
1D (A/mm)
2
2.5
(b)
(a)
Figure 6-11. (a) Gate current injection method and (b) source resistance extracted by the method.
potential with the drain current as shown in Figure 6-11(b). The measured source resistance is
almost constant in the nanowire device while it increases rapidly with increasing the drain
current in the planar device. This result suggests that the main cause of the peaky behavior of gm
in the convention al planar GaN devices is the increase of the source resistance rather than
optical phonon scattering even at short-channel devices with sub-100 nm gate length. The
extrinsic g,, of the nanowire channel device is larger than that of the planar device due to about
50 % lower access and contact resistances resulting from the normalization based on the
effective nanowire channel width. However, the intrinsic transconductance is almost similar in
both devices. The threshold voltage (VT) is shifted by about 1.4 V at VDS= 3 V in the positive
direction due to the side gate effect.
Moreover, the suppression of the increase in the access resistance of the nanowire channel
device exposes the real potential of high current drivability in GaN HEMTs. In conventional
planar GaN HEMTs, the maximum drain current is about 2 ~ 2.5 A/mm even in the short
channel devices. Although this value is very large compared to Si devices, it is still far below
154
2
-
E
o:2 1.5
2.5
L= 70- 8 0 nm
VDS= 3 V
2
VGS= -5 - 1 V
nanowire
EE 1.5
E 0 .5
-.
-4
-3
-2
-1
0
nowr
0.5
----------
-5
planar
nanowire
planar
E
Lg = 70-80 nm
0
1
VGS (V)
1
2
3
4
5
VDS (V)
(b)
(a)
Figure 6-12. DC (a) transfer and (b) output characteristics of nanowire channel device and conventional
device based on the entire device width normalization.
theoretical expectation. Based on the material properties such as sheet charge density and
saturation electron velocity, the maximum current of GaN HEMTs is expected to be about 4 ~5
A/mm. The non-linear access resistance effect shown in this experiment explains the reason why
the maximum current of the conventional GaN HETMs cannot reach this level. As the gate bias
increases, the increase of the source resistance with drain current limits the effective gate
overdrive (VOV.eff= VGS.eff - VT - ID x Rs), so that the channel charge cannot increase linearly
with the extrinsic gate bias (VGS). As shown in Figure 6-10(b), the maximum current density of
the nanowire channel device goes above 3.5 A/mm (VGs=1 V) thanks to the constant source
resistance even at the high drain current conditions. This shows that the intrinsic GaN device
with proper source design can support such a high current density. Moreover, even with the
normalization based on the total device width including both nanowire channel and isolation
regions, the current reduction compared to the planar device is only 31 % in spite of about 57 %
channel removal and higher VT as shown in Figure 6-12. This shows that the device structure
155
R=2.25
R = 1.83
0.8
R =1.23
EAY,
SD
0.6
$
R\
0.4
Ilk
0.2
Wchannel
88, 132, 380 nm
VDs=
Woi= 110 nm (fixed)
-4
-3
-2
-1
5V
0
VGS (V)
(a)
(b)
Figure 6-13. (a) Variation of nanowire channel width in the device layout. (b) Extrinsic gm, as a function
of the gate voltage in the devices with different width ratio.
used in this study is not only useful to study intrinsic device performance, but also can be used in
real applications which require high linearity.
6.3.5. Effect of channel width and width ratio
In terms of the device design, the widths of the nanowire channel and isolation region are most
important parameters as shown in Figure 6-13(a). In this experiment, the nanowire channel width
is changed with fixed isolation width. With these two parameters, a width ratio (Rwidth) can be
defined as
Wchannel
+ Wiso
Wchannel
156
_
Waccess
Wchannel
As shown in the equation, the width ratio indicates the ratio between channel width (Wehannel) and
access region width (Waccess). That is, in the conventional planar device, the width ratio is 1 and it
becomes higher than I in the nanowire channel devices. Figure 6-13(b) shows the extrinsic
transconductance as a function of the gate voltage in the devices with different width ratio. The
devices with higher width ratio show the flatter extrinsic gm and this can be explained by two
reasons. First, the higher width ratio indicates that the access region is much wider than the
nanowire channel, so that the access region can act as more ideal source to the intrinsic channel.
Thus, with higher width ratios, the device becomes closer to the self-aligned device or intrinsic
device. Second, in this experiment, a decrease in the width ratio indicates an increase in the
nanowire channel width. As the width of the channel increases, the effective distance between
the nanowire channel and additional access region increases, which degrades current flow from
the additional access region to the nanowire channel.
In order to confirm the effect of the channel width, a test structure was fabricated as shown in
Figure 6-14. In this structure, the channel width is about 20 ptm, while the access region width is
about 50 jam, which makes the width ratio of 2.5. Figure 6-15 shows DC transfer and output
characteristics of the test device, normalized by the channel width (20 pm). Although the width
ratio is even larger than that of the best nanowire channel device shown in Figure 6-10, the gm
GaN
Figure 6-14. Test device structure to study the effect of the nanowire width.
157
V
2.5
0-100 nm
. .
E
VDS= V
VDS= 3 V
%..W 1.5
2-
0)E
1I[
-3
test
test
1
0.5
V
-2
VGS=-3~-1 V
planar
-----
E 1.5
planar
E 0.5[
Lg= 90-100 nm
-1
VGS (V)
0
0
C
1
(a)
1
2
V
3
(V)
4
5
(b)
Figure 6-15. DC (a) transfer and (b) output characteristics of the test structure and planar device.
;L
;L ;
Lgg
(a)
(b)
Figure 6-16. Current flow in (a) nanowire device and (b) test structure with wide channel width.
drop occurs just like in planar devices. Moreover, both output and transfer characteristics of the
test device are very similar to the planar device, which shows almost no effect of the wider
access region. This is because, unlike the nanowire channel device, the channel of the test device
cannot take advantage of the increased current supply from the additional access region due to its
wide width as shown in Figure 6-16. Thus, in terms of the device design, both the nanowire
channel width and the width ratio are key parameters to achieve high linearity.
158
GaN
Figure 6-17. Test device structure to study the surrounding gate effect
E
2
1 .5F
0)
E
2.5
Lg= 70-80 nm
2
VDS= 3 V
E 1.5
test
planar
1[
E
M0 0.51
0!
test
Lg= 70-80 nm
VGS=-
~
planar
1
0.5
-3
94-3
-2
-1
VGs (V)
0
0)
(
1
(a)
3
1 122
3
VDS (V)
4
5
(b)
Figure 6-18. DC (a) transfer and (b) output characteristics of the test structure and conventional planar
device.
6.3.6. Surrounding gate effect
In addition to the width ratio, the main difference between the nanowire channel devices and
conventional planar devices is the side gate effect. The gate of the nanowire channel devices
surrounds the channel, so that the gate electric field controls the channel through both top and
sidewall contacts. In order to check whether the surrounding gate effect has any influence on the
g. linearity, a test structure device like the one shown in Figure 6-17 was fabricated. Different
from the demonstrated nanowire channel device, the test device has the nanowire channel in the
159
entire area between source and drain. As shown in Figure 6-18, a gm drop at high drain current
region is observed in the test device like the planar device, which shows that the surrounding
gate structure has no impact on the linearity. The V1 is shifted in the positive direction like in the
case of the nanowire channel structure due to the side gate effect. This result confirms again that
the flat gm in the nanowire channel device is due to the wider access region compared to the
planar channel device.
6.3.7. RF characteristics
The RF characteristics of the nanowire channel devices were measured from 100 MHz to 40
GHz using an Agilent N5430A network analyzer. Figure 6-19 shows the current gain cutoff
frequency (fT) as a function of the gate voltage in both nanowire channel and planar devices.
Thanks to the flatter gm, the fj- drop at high gate bias is significantly suppressed in the nanowire
channel device, while a serious degradation of fT is observed in the planar device. The uniform
RF characteristics over a wide range of bias condition in the nanowire devices can be very useful
200
150
OO-
Lg= 70-80 nm
VDS=
planar
3V
100-
50
95
nanowire
-4
-2
-3
VGS (V)
-1
0
Figure 6-19. f1 as a function of the gate voltage in the nanowire channel device and conventional planar
device.
160
Gate
frin
C
aN
GaN
CCfn__________
_
(a)
____
____
____
____
(b)
Figure 6-20. Fringing capacitances in the nanowire channel device. (a) Fringing capacitance between
gate and sidewall of the nanowire. (b) Fringing gate capacitance between gate and additional access
region.
to improve the linearity of these devices with respect to traditional GaN HEMTs. However, the
nanowire channel device has about 35 % lower maximum current gain cutoff frequency (f ) than
1
the planar device due to the larger fringing capacitance. The additional fringing capacitance
comes from the sidewall and additional access region as shown in Figure 6-20. Since the gate
covers the sidewall of the nanowire channel, it results in the increase in the gate capacitance.
Also, the electric coupling between gate and additional access region causes the additional
fringing capacitance. This issue can be reduced by using implantation for the fabrication of
nanowire channels instead of dry etching and by applying air bridge technology for the gate
electrodes.
6.3.8. Breakdown Voltage
High linearity can be achieved by using self-aligned device structure having no access region as
explained in the section 6.2.2. However, one of the main advantages of the nanowire channel
structure compared to the self-aligned structure is a large break down voltage. In the nanowire
channel devices, the high linearity is obtained without removing the access region and the access
161
region can thus support a large breakdown voltage. In fact, the access region length can be easily
changed based on the target breakdown voltage in this structure without losing high linearity.
Moreover, electric field engineering is possible in the nanowire channel devices, which can
provide the higher breakdown voltage compared to the conventional planar devices with same
gate-to-drain distance. Although more systematic study is necessary, the surrounding gate effect
can reduce the electric field at the drain side gate edge, which improves the breakdown voltage.
Thus, the nanowire channel structure has a huge potential to provide both high linearity and large
breakdown voltage.
6.4. Conclusion
In this chapter, the gm and fT nonlinearity in highly-scaled GaN HEMTs was addressed. There
has been controversy about whether the problem is associated with an intrinsic GaN property or
a limitation of the extrinsic device elements. This study focused on the impact of non-linear
access resistance on the linearity and developed a nanowire channel device structure in order to
overcome the limitation of the current supply in the source access region. To combine the
nanowire channel and sub-100 nm gate, a novel fabrication process was developed, which
allowed the perfect alignment between the channel and gate without additional alignment process.
The device showed a flat extrinsic transconductance thanks to the higher current drivability of
the access region relative to that of the intrinsic channel, which confirmed that the limited current
supply from the source access region is the main cause of the gm drop at high drain current. The
source resistance measured from the nanowire channel device through the gate injection method
was maintained almost constant while it increased rapidly with increasing drain current in the
conventional planar device. The suppression of the increase of the source resistance exposed the
162
intrinsic GaN device performance, which allowed a drain current of over 3 A/mm. In addition,
thanks to the flat extrinsic gm, the fT of the nanowire channel device showed a high linearity over
a wide gate bias range although the maximum value was lower than that of the planar device due
to the additional gate fringing capacitance. The issue about the gate fringing capacitance is
expected to be suppressed by using implantation and air bridge technologies. Thanks to the high
device performance that has been demonstrated in this chapter, the proposed nanowire channel
structure is not only useful for studying the intrinsic device performance, but also can be used for
real applications which require both high linearity and large breakdown voltage.
163
Chapter 7. Conclusion and Future Work
7.1. Summary
In this thesis, two important issues of deeply-scaled GaN HEMTs have been studied. First, in
spite of the outstanding performance promised by GaN material properties, the maximum current
gain cutoff frequency (fT) of GaN transistors demonstrated in the literature has been lower than
the theoretically expected values and the gap between the expectation and experimental data
becomes larger in the shorter gate length devices. The second issue is the degradation of the
frequency performance at high drain and gate bias. The significant drop of fT at these bias ranges
is the critical limitation for the large-signal high speed operation of short channel devices.
In the first part of this thesis, we have investigated what limits the maximum speed of short
channel devices. For systematic study, the device has been divided into intrinsic and extrinsic
sections, and the limiting factors in each have been addressed.
In the intrinsic device, the channel control by vertical electric field from the gate electrode is
the most important factor. In the deeply-scaled devices, however, the increased lateral electric
field degrades the electrostatics and causes short-channel effects including degradation of the
gate modulation, increase in the output conductance and DIBL, and poor pinch-off. In order to
overcome these issues, three technologies have been applied and their impacts have been studied.
First, in order to improve the gate modulation efficiency, InAlN/GaN heterostructures with thin
top barrier and high sheet charge density were applied to the deeply-scaled devices. A 30 nm
gate length InAlN/GaN HEMT showed a significant improvement in the gate controllability
compared to the same gate length AlGaN/GaN HEMTs. Moreover, the speed of the device
164
reached a current gain cutoff frequency of 245 GHz, which was higher than any other GaN
HEMTs demonstrated previously [92].
However, in spite of the thin top barrier thickness
(tb=
6.5 nm), the degradation of pinch-off
and subthreshold characteristics was still observed in the deep sub-50 nm gate length devices. To
solve this issue, an AlGaN back barrier structure was combined with an InAlN/GaN transistor
heterostructure [95]. The AlGaN back barrier structure induces a polarization field in the GaN
layer, which improves the channel charge confinement by raising the conduction band.
Compared to the control structure, significant reduction of the DIBL was observed in the
structure with back barrier and a complete pinch-off could be obtained even in the sub-30 nm
gate length device. Also, the maximum GaN device current gain cut-off frequency was pushed to
270 GHz.
As an alternative approach to the AlGaN back barrier structure, vertical channel scaling
technology was also investigated. Through the insertion of an InGaN layer in the middle of the
GaN layer, the vertical channel thickness was scaled down from 26 nm to 3.4 nm. With the
scaled channel thickness, the degradation of the pinch-off and subthreshold characteristics could
be suppressed effectively thanks to the increased charge confinement of the 2-DEG channel [98].
However, it was observed that excessive channel scaling could result in the degradation of the
transport properties due to the increase of the interface/alloy scattering. Due to this trade-off, the
best RF performance with an fT of 300 GHz was achieved in the devices with 26 nm [99], which
showed that the optimization of the channel thickness to maximize transport properties was key
in this technology.
In the deeply-scaled devices, the optimization of the extrinsic device is as important as the
intrinsic device design. According to the delay analysis of 300-GHz class devices, about 60-70 %
165
of the total device delay was caused by the extrinsic device. The origin of the delay in the
extrinsic device can be divided into parasitic delay and extrinsic delay. In order to reduce the
parasitic delay, the source/drain resistances should be minimized. With the conventional
fabrication process, the total resistance of the devices is generally above 1 0-mm. In order to
achieve an on-resistance below 0.5 f-mm, a low sheet resistance heterostructure, scaled sourceto-drain distance, and contact regrowth technologies were combined, which made it possible to
demonstrate transistors with RO, of about 0.4 f-mm and fT of 320 GHz [108].
In the case of the extrinsic delay, one of the main sources of delay is the fringing gate
capacitance through the passivation layer. Since a relatively thick passivation layer is generally
required to reduce surface trapping effect, its impact on the device speed needs to be analyzed.
From the study of transistors with different passivation thickness, it was shown that the fringing
capacitance could be about 35 % of the total capacitance in sub-40 nm gate length devices with
40 nm passivation thickness [109]. Moreover, considering that the experiments were performed
with the rectangular shape gate devices, its impact could be larger in real applications where a Tshape gate structure is needed. These results showed that development of the low-k passivation
and optimization of its thickness is as important as device scaling to overcome the limitation
coming from the extrinsic delay and to achieve extremely high frequency performance. Based on
this study, a maximum fT of 375 GHz was demonstrated in the sub-30 nm gate device with thin
passivation [111].
In the first part of this thesis, several approaches have been investigated to improve the
maximum speed of the deeply-scaled GaN HEMTs. Thanks to this work, the speed of 30-nm
gate length GaN HEMTs was increased from 171 GHz to 375 GHz as shown in Figure 7-1. The
fT
projection model based on the delay analysis showed that 500-GHz class GaN HEMTs can be
166
400
400
Lg =26 - 30 nm
K(
350-
/360
-'
300
I
0
4-
Regrowth contact
& scaled LSD[108]
270
250
I-
4
--
200
*-
-
171 *
50-
Conventional AIGaN/GaN HEMT
100,
250
100
InAIN/GaN HEMT [92]
150
*--
150
AIGaN back barrier [96]
200
0-
N-
Vertical channel scaling [99]
245
300
Mild gate recess
320
300
I:;.
350
375
\ Thin
passivation [110]
1
2
3
4
5
6
7
00
8
50
100 150
Development Stage
L9 (nm)
(a)
(b)
200 251
Figure 7-1. (a) Improvement in f1 of deeply-scaled GaN HEMTs through this work. (b) Comparison of
the frs in this work with those of AlGaN/GaN HEMTs reported in literatures (Figure 3-2).
achieved in 20 nm gate length devices by ensuring good electrostatics and by minimizing the
parasitic delay and gate fringing capacitance.
The second part of this thesis has focused on the roll-off of the device frequency performance
under wide bias range operation. Compared to other high speed semiconductor devices, the main
advantage of the GaN HEMTs is their capability to handle large output power at high frequency.
For this, a frequency performance needs to be maintained under both wide drain bias and wide
gate bias range. However, the device speed typically decreases with increasing drain bias or gate
bias. In the second part of this thesis, the origin of the roll-off in the transistor speed was studied.
The decrease of fl- at high drain bias has been observed in many other semiconductor devices.
At high drain bias, the extension of the depletion region at the drain-side of the channel results in
167
the gate extension, which increases the electron transit delay. To measure the additional transit
delay, which is called as drain delay, the N. Moll method has been widely used [40]. However,
there is error between the extracted values and true drain delay because the method assumes that
all the increase of the device delay at the high drain bias is caused by drain delay. In this thesis, a
new drain delay extraction method based on the small-signal equivalent circuit analysis was
proposed [123]. The new extraction method, based on
Cgs/gm.int,
only captures the gate extension
effect, removing all other effects, which allows more accurate extraction of the drain delay. In
addition, it was observed that the extracted drain delay rate increased with scaling the gate length.
Through the analysis based on the new model, it was found that the increase of the extracted
delay in short channel devices was not caused by the faster gate extension, but by the
degradation of the electrostatics at high drain bias. That is, the speed of the short channel devices
decreases at high drain bias because of a combination of additional delay resulting from
degradation of electrostatic and real drain delay due to expansion of the drain-side depletion
region. To reduce each delay component, GaN transistors with vertical channel scaling and
lateral gate-to-drain scaling were tested, which showed the effective suppression of the device
fT
roll-off at high drain bias.
The degradation of the device speed at high gate bias is more significant in the short gate length
devices. The decrease of fT is directly connected to the nonlinearity of the gm. There have been
many different theories to explain this gm or fT decrease at high gate bias. In this thesis, we
focused on understanding the impact of the nonlinear source access resistance [139]-[141]. In
GaN HEMTs with non-self-aligned structure, the low current drivability of the source access
region can limit the maximum current flow of the device. In order to prove this hypothesis and
develop a solution, nanowire channel GaN HEMTs were demonstrated [144]. The uniqueness of
168
the proposed device structure was that the nanowire channel was formed only under the gate,
while the access region was maintained as in the planar device. Thanks to the wider access
region than the channel, enough current could be supplied from the source access region to the
intrinsic channel even at high gate bias. The device showed a flat gm and f1 in a wide bias range,
which demonstrated that the source access region is the main cause of the drop. Moreover, the
current density in the devices became larger than 3 A/mm approaching the theoretical
expectations. These results clearly showed that an appropriate source design is critical to expose
the real potential of deeply-scaled GaN HEMTs.
In summary, this thesis has explored deeply-scaled GaN HEMTs by focusing on the device
frequency performance. Through systematic analysis and novel device technology, it has
proposed solutions for key challenges, demonstrated the state-of-the-art in high frequency GaN
HEMTs, and improved the understanding of these devices. The following list summarizes the
main contributions of the work.
" Demonstration of 30 nm InAlN/GaN HEMTs with record frequency performance
" Combination of InAlN heterostructure and AlGaN back barrier structure
"
Study on impact of the vertical channel scaling in the deeply-scaled devices
" First demonstration of 300-GHz class GaN HEMTs
"
Study on the impact of extrinsic device components on speed of short channel devices
*
Demonstration of one of the state-of-the-art low on-resistance GaN HEMTs
" Proposal of new drain delay extraction method based on small-signal model
" Demonstration of nanowire channel device with high linearity of gm and
169
fT
7.2. Future work
Based on the work of this thesis, the following research directions are suggested to push GaN
transistor technology further.
7.2.1. Channel engineering to increase the electron velocity
According to Monte Carlo simulations on the carrier transport of GaN channels, the electron
velocity reaches its maximum point at the electric field of 100-200 kV/cm, and then it decreases
to about 1.5 ~ 2 x 107 cm/s. In short channel GaN HEMTs, the electric field in most of the
channel region is higher than 100-200 kV/cm, so that it is difficult to take advantage of the
maximum electron speed in GaN. Channel electric field engineering thanks to a novel gate
structure or access region design may boost the electron velocity, which would provide a
significant improvement in device speed.
In addition, as another approach for channel engineering, a new channel material can be used.
In the last few years, several heterostructures have been proposed for advanced high speed GaN
electronics, including InAlN/GaN [84], [85], AlN/GaN [82], [83], and N-face heterostructures
[124], [151]. In these innovations, the main focus has been the top barrier material or its location,
while the channel material has been fixed to GaN. There have been several studies about other
channel materials such as InGaN [152]-[154] and InN [155]-[157]. Although there are still
many challenges such as high quality material growth, strain management, and process
development, these materials have a great potential to improve the device speed significantly
thanks to their high electron saturation velocity [158]. It is believed that combination of the good
material growth and novel heterostructure/device design can make it possible to realize InN or
InGaN channel devices having superior performance than conventional GaN channel devices.
170
7.2.2. Technologies to minimize the extrinsic delay
In highly-scaled devices (Lg < 40 nm), the performance is limited by the extrinsic device
components. In the case of the parasitic resistance, the technologies to minimize the contact and
access resistances have been investigated and devices with on-resistance below 0.5 f-mm have
been reported [108], [127], [159]-[161]. On the other hand, there are relatively few studies to
reduce the fringing gate capacitance effect [109]. As shown in this thesis, the fringing gate
capacitance is directly related to the passivation technology. In order to develop a good
passivation technology with minimal fringing capacitance effect, a solid understanding on the
surface states and passivation mechanisms are required. Although traditionally the study of these
topics has been regarded as device reliability research, their results can have a huge impact on
high speed GaN electronics by providing a good solution for reducing extrinsic delay.
7.2.3. Effect on device design on drain delay
In this thesis, a new extraction method for drain delay has been proposed, which helps to
capture the delay caused by the gate extension [123]. By using this tool, a detailed study of the
drain delay in different heterostructures and device designs is possible. The drain delay or the
gate extension can be affected by many different factors such as sheet charge density, passivation
technology and gate recess depth. Study on these topics allows us to design the device with
minimal gate extension effect, which makes it possible to increase the device speed in the
operation under high drain bias. Furthermore, research about novel device structures which can
provide higher breakdown voltage under same drain delay effect can be very useful to expand
the potential of GaN RF power amplifiers.
171
7.2.4. Advanced nanowire channel devices
Nanowire channel GaN HEMTs have been developed in this thesis to prove the origin of the gm
and
fT
drop at high drain bias [144]. Although the prototype devices were just designed for
demonstrating the concept, the devices showed outstanding performance with high linearity, high
current and large breakdown voltage. There is however a large room for improvement in both
DC and RF performance. For example, the nanowire channel width can be optimized to achieve
the maximum current drivability with maintaining the linearity. Also, instead of the rectangular
shape gate, a T-shape gate process can be applied to deliver high output power with small gate
resistance. To decrease the fringing capacitance through sidewall for the nanowire channel,
implantation technology can be used instead of the etching process for isolation. Finally, a
systematic study of the electric field distribution in the nanowire channel structure needs to be
conducted to study the potential of high breakdown voltage.
172
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