FPGA Control on CompactRIO Sample Project Documentation
Publish Date: Apr 15, 2015
Overview
The FPGA Control on CompactRIO sample project implements deterministic, hardware-based control of a plant. The control
algorithm, which was written with the LabVIEW FPGA Module, runs on the FPGA inside the CompactRIO device. You send
commands and setpoint changes to the FPGA from the user interface, running on a desktop computer, by way of the real-time
controller in the device. This controller also monitors the status of the application, such as CPU load and memory usage.
Table of Contents
1.
2.
3.
4.
5.
6.
7.
8.
Developer Walkthrough
Features
Basis
System Requirements
Overview
Running this Sample Project
Modifying this Sample Project
Additional Resources
1. Developer Walkthrough
See a developer walkthrough (http://zone.ni.com/wv/app/doc/p/id/wv-3378) of the RIO sample projects.
2. Features
High-performance control—The control loop can run faster than 10 kHz and features four control algorithms operating in
parallel, all with minimal jitter.
Hardware-based control—Running the control algorithm and safety logic on the FPGA provides maximum reliability.
User interface with headless option—The user interface VI interacts with the CompactRIO device and displays data. This VI
can connect and disconnect from the device at any time without affecting the control loop.
Error handling—The application reports and logs all errors from the CompactRIO device, shutting down on any critical error.
3. Basis
This sample project is based on the Simple State Machine (http://www.ni.com/white-paper/14120/en) and Queued Message
Handler templates (http://www.ni.com/white-paper/14119/en). Refer to the Simple State Machine and Queued Message Handle
templates and their documentation, available from the Create Project dialog box, for information about how these templates w
4. System Requirements
Development System
LabVIEW Full or Professional Development System
LabVIEW FPGA Module
LabVIEW Real-Time Module
NI-RIO device driver software
NI CompactRIO Device in FPGA Interface Mode
This sample project is designed for an NI cRIO-9074 with the following components:
Software:
LabVIEW Real-Time
Network Streams
Network Variable Engine
NI System Configuration
NI-RIO
NI-Watchdog
I/O modules:
NI C Series analog input module. This sample project is designed to read four channels of analog input from an NI 9201
module in slot 1.
NI C Series analog output module. This sample project is designed to write four channels of analog output to an NI 9263
module in slot 2.
5. Overview
This sample project consists of nine parallel loops across three execution targets. The following loops run in parallel on the
desktop computer:
Handling events from the user interface (UI Main.vi - Event Handling Loop)—Produces messages to the UI Message Loop
based on front panel events.
Handling messages from the user interface and the real-time controller (UI Main.vi - UI Message Loop)—Receives and
responds to messages from the Event Handling Loop and, using network streams, the RT Message Handling Loop.
Displaying messages and data from the CompactRIO device (UI Main.vi - Monitoring Loop)—Displays the latest values of
information acquired from RT Loop - System Health and FPGA Monitoring.vi.
The following loops run in parallel on the real-time controller:
Handling commands from the user interface (RT Loop - UI Commands.vi)—Reads commands that are sent from UI Main.vi,
using network streams, and produces the appropriate messages.
Handling messages from all loops on the real-time controller (RT Main.vi - Message Handling Loop)—Consumes messages
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Handling messages from all loops on the real-time controller (RT Main.vi - Message Handling Loop)—Consumes messages
from all loops that run on the real-time controller.
Ensuring the FPGA can communicate with the real-time controller (RT Loop - Watchdog.vi)—Pets the watchdog, which tells
FPGA that the RT controller still is running, by asserting a register on the FPGA.
Monitoring diagnostic information from the real-time controller and data from the FPGA (RT Loop - System Health and FPGA
Monitoring.vi)—Monitors CPU and memory usage of the real-time controller and data from FPGA Main.vi. This information is
written to network-published shared variables and appears on the Data Monitoring and System Monitoring tabs of UI
Main.vi.
The following loops run in parallel on the FPGA:
Controlling the plant (FPGA Main.vi - Control Loop)—Reads from the NI 9201 inputs, applies a control algorithm to each
channel, and writes to the NI 9263 outputs. The control algorithm uses setpoint data and PID gains sent from the user
interface.
Ensuring the FPGA can communicate with the real-time controller (FPGA Main.vi - Watchdog Loop)—Checks the watchdog
register, set by RT Loop - Watchdog.vi, to ensure the real-time controller is communicating with the FPGA. If communication
cannot be established, the Watchdog Loop sets the FPGA to a safe state and reboots the device.
General sequence of steps:
1. A user changes the value of a setpoint; for example, changing the Channel 0 Setpoint control from 0 to 3. This change cau
LabVIEW to register an event.
2. The Event structure in the User Interface Event Handling Loop triggers the appropriate message diagram, which produces th
Update Setpoints message to the message queue. The values of all four setpoint controls, including the changed value, are
enqueued as data along with the message.
3. The UI Message Handling Loop consumes the message and data, dequeuing it and executing the corresponding message
diagram.
4. The message diagram contains code that writes the Update Setpoints message and data to a network stream.
5. On the real-time controller, the UI Commands loop reads the message and the data from the network stream.
6. The UI Commands loop relays the same Update Setpoints message and data to the RT Message Handling Loop that is also
running on the real-time controller.
7. The RT Message Handling Loop consumes the message and data, dequeueing it and executing the corresponding messag
diagram.
8. The message diagram contains code that writes the data to the front panel of the FPGA VI, using the Read/Write Control
function.
9. On the FPGA, the Control Loop uses the data in its control algorithm.
6. Running this Sample Project
1. Adapt the sample project to your hardware.
2. In the Project Explorer window, run RT CompactRIO Target»RT Main.vi. This VI initializes the FPGA and runs FPGA
Main.vi.
3. Open and run My Computer»UI Main.vi.
4. Enter the IP address of the CompactRIO device in the Controller Address text box and click Connect.
5. After you are connected, click either Run Control (on the Control Settings page) or Run Manual (on the Manual Settings
page).
6. Adjust the channel values as necessary and view the outputs on the Data Monitoring page. Until you define a control
algorithm, all Output Values will read 0.
7. Click Exit to exit the application.
7. Modifying this Sample Project
Adapting the Sample Project to Your Hardware
The FPGA VI in this sample project is compiled for specific FPGA and I/O hardware. If you have a different FPGA or different C
Series modules, you must adapt this sample project to your hardware. The following steps refer to NI CompactRIO devices, bu
you also can adapt this sample project to an NI Single-Board RIO device.
1. Ensure all devices are configured and connected to the same network as the development computer.
2. In the Project Explorer window, add or discover your RT CompactRIO target to the to the top-level project item.
3. Add or discover your CompactRIO chassis to the RT Compact RIO target you added in the previous step. Ensure the chass
set to LabVIEW FPGA Interface mode.
4. Add or discover your FPGA target to the CompactRIO chassis you added in the previous step. When prompted to deploy
settings, click Deploy Later.
5. Add or discover your C Series input and output modules to the FPGA target you added in the previous step.
6. Drag the following project items from the default RT CompactRIO target to the one you added in step 2:
Error Handlers folder
Globals folder
Support VIs folder
RT Loops folder
Type Definitions folder
Shared Variables.lvlib
RT Main.vi
7. Drag the following project items from the default FPGA target to the one you added in step 4:
Support VIs folder
Type Definitions folder
FPGA Main.vi
Variable References.ctl
8. Delete the default RT CompactRIO Target project item that no longer has any VIs associated with it.
9. Re-establish the link between RT Main.vi and the bitfile:
1. Open Initialize and Run FPGA VI.vi, located in the Support VIs folder on the RT CompactRIO Target.
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9.
1. Open Initialize and Run FPGA VI.vi, located in the Support VIs folder on the RT CompactRIO Target.
2. Drag FPGA Main.vi from the Project Explorer window to the Open FPGA VI Reference VI function.
10. Open FPGA Main.vi and ensure the FPGA I/O Nodes use the input and output channels you want. For example, you may w
an FPGA I/O Node to read from Mod2/AI5 instead of Mod1/AI2. The actual channels you read from and write to depend on
your application.
By default, the FPGA I/O Nodes in this VI read from Mod1/AI0–3 and write to Mod2/AO0–3.
11. To minimize time spent compiling, make necessary changes, such as defining a control algorithm and defining a safe state,
now. You can compile and run the FPGA before making these changes; however, you will have to compile the FPGA VI aga
afterwards.
Defining a Control Algorithm
Locate the Control (PID) subdiagram of the Case Structure in FPGA Main.vi and modify this subdiagram to apply a control
algorithm. This sample project is designed to implement a PID algorithm. By default, this algorithm returns a constant value of 0
all output channels. You can perform a different algorithm on each individual channel
Defining Safe Values for Hardware Connected to the C Series Modules
Modify the Safe State, Default subdiagram of the Case structure in FPGA Main.vi to write safe values to the output channels. T
values you write here should be ones that you know the connected hardware can safely handle. By default, this subdiagram wr
a value of 0 to all output channels.
This subdiagram executes in the following situations:
When FPGA Main.vi first runs
The watchdog algorithm times out
An error occurs while reading from or writing to an FPGA I/O channel
A "Critical" or "Non-Critical" error occurs on the desktop computer or real-time controller
You click the Switch Target to Safe State, Stop Control, Stop Manual, or Exit button in UI Main.vi
Configuring the Application
In the Project Explorer window, open My Computer»Globals»Global - Configuration Options.vi. Use this VI to configure th
following settings:
If you are programming or testing the application, leave Debugging as TRUE. If you are building an application for deploym
set Debugging to FALSE.
To change how the often the control algorithm executes, change the Control Period (ticks). The default is 40000 ticks of th
FPGA clock.
To change the time period during which both endpoints of a network stream must be established, change the Network Stre
Connect Timeout (ms). The default is 5000 ms.
To change how often the real-time controller polls the user interface for commands, change the Network Stream Polling
Timeout (ms). The default is 500 ms.
To change how often the real-time controller pets the watchdog, change the Watchdog Pet Rate (ms).The default is 100 m
To change how long the FPGA has to respond to a watchdog pet, change the Timeout Period (ticks). The default is 40000
ticks of the FPGA clock.
To change how often the user interface updates with monitoring and health information from the CompactRIO device, chang
the Monitoring Loop Rate (ms). The default is 200 ms.
To change the time period during which identical errors are considered duplicates, change the Error Log Duplicate Interva
(ms). This control defines the interval of time during which only the first in a series of identical errors will be logged. For
example, if an error occurs after 2000 ms have elapsed and occurs again after 5000 ms have elapsed, and Error Log
Duplicate Interval (ms) is 6000 ms, the second occurrence is considered a duplicate and not logged. Only 3000 ms have
elapsed, not the 6000 ms required to treat the second error as unique.
The default is 5000 ms.
To change the names of the network streams, modify the UI Stream Name or RT Stream Name controls. These names affe
the endpoint URLs but otherwise have no impact on the application.
To change the location of the error log file, set the RT Error Log control. The default is c:\logs\logs.txt.
To change the maximum size of the error log, change the Error Log Max Size (bytes) control. The default is 100000 bytes.
8. Additional Resources
LabVIEW FPGA Control Sample Project Detailed Documentation (https://decibel.ni.com/content/docs/DOC-23262)
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