Nano-scale Metal Contacts for Future III-V CMOS
by
Alex Guo
B.S. Electrical Engineering and Computer Sciences, University of California, Berkeley, 2010
Submitted to the Department of Electrical Engineering and Computer Science
In Partial Fulfillment of the Requirements for the Degree of
Master of Science in Electrical Engineering
at the
TL
Massachusetts Institute of Technology
September 2012
C 2012 Massachusetts Institute of Technology
All Rights Reserved.
The author hereby grants to MIT permission to reproduce and distribute publicly paper and
electronic copies of this thesis and to grant others the right to so.
Author
Department of Electrical Engineering and Computer Science
August 30, 2012
Certified by
Jesn's A. del Alamo
Professor of Electrical Engineering
Supervisor
A 4Thesis
Accepted by
2ies
e A. Kolodziejski
Chair, Department Committee on Graduate Students
1
2
Nano-scale Metal Contacts for Future I-V CMOS
by
Alex Guo
Submitted to the Department of Electrical Engineering and Computer Science
August 30, 2012
in Partial Fulfillment of the Requirements for the Degree of
Master of Science in Electrical Engineering
ABSTRACT
As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical
limits and alternative technologies are needed to extend Moore's law. Among different candidates,
MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs
with an InGaAs channel have shown promising results for N type MOSFETs.
In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while
improving transistor's electrical performance. For future technology nodes, the gate length of
MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a
comparable dimension. A concern about contact scaling is the increase of source resistance. It is
predicted that the source resistance will increase exponentially when the contact length is decreased
to the nanometer scale regime.
In order to understand the issues associated with source contact scaling to the nanometer regime, we
have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs
heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit
network. After measuring the fabricated devices, the model has been used to extract the relevant
electrical parameters that characterize these structures. We have obtained a specific contact
resistivity of (0. 116 +/- 0.058) Q -um 2 . For Mo/n+-InGaAs contacts, to the best of our knowledge,
this is the lowest value reported to date. The fabrication process and the theoretical model presented
in this study should help future 111-V CMOS scaling research and development.
Thesis supervisor: Jesu's A. del Alamo
Title: Professor of Electrical Engineering
3
4
Acknowledgements
First of all, I would like to thank my research adviser Jesn's A. del Alamo for giving me the chance to
work in his research group, and for introducing me to this very interesting project. His passion and
invaluable knowledge in our research field continue to inspire me to do good research. I am grateful
for his excellent guidance, constant encouragement and his patience, from which I learned research
techniques and continue to grow as a researcher. I am extremely lucky to be his student!
I would also like to thank Jianqiang Lin for his help with the development of the fabrication
processes. Jianqiang has always given me great advice and shared his expertise in the cleanroom.
He also went out of his way to help me with issues occurred during fabrication and gave me great
suggestions in varies occasions. I will always remember those nights when we worked together in
TRL to keep each other motivated.
I appreciate the help from Dr. Tae-Woo Kim and Dr. Jorg Scholvin, especially at the beginning stage
of this project. Dr. Tae-Woo Kim helped me draft the first fabrication process and provided valuable
insights during the first year of the project. Dr. Jorg Scholvin shared with me his program that
automated the mask drawing in Cadence, and I thank him for all the meaningful discussions on this
project and graduate school in general.
It has been a great pleasure to work with the rest of the members in del Alamo's research group. Dr.
Ling Xia was the first person I talked to from the group and has always been supportive and helpful.
I also thank Dr. Jungwoo Joh and Dr. Usha Gogineni for the chats and motivational discussions. I
appreciate all the help from Xin Zhao, who joined the group at the same year as me, who is always
willing to help and share his knowledge. I am also thankful for Shireen Warnock and Luke Guo, and
looking forward to more ice cream trips with them in the future.
I appreciate all the help from TRL stuff members. They are extremely professional and helped me
through many fabrication issues. This project will not be possible without their support.
I would like to thank my friends who helped me professional and personally throughout the past two
years. Leila Pirhaji, Wardah Inam, Moojan Daneshmand, Mohamed Azize, thank you for all the fun
time and chats, movies, outings, and your constant support!
5
Finally, I appreciate my grandparents for their love and faith in me, and the support from the rest of
my family in China.
This work was sponsoredby FCRP-MSD Center.
6
Contents
LIST O F FIG URES ..............................................................................................................................................
9
LIST O F TAB LES ..............................................................................................................................................
11
C H A PTER 1. IN TR O DUC TIO N ................................................................................................................
13
1.1.
1.2.
1.3.
1.4.
Introductionto III-V CM OS .....................................................................................................
Motivation - Resistance Scaling in III-V MOSFET .............................................................
N ano-TLM for I I-V CMOS.....................................................................................................
Thesis Outline................................................................................................................................
13
15
17
19
CHAPTER 2. THEORETICAL MODEL FOR DESIGNED NANO-TLM STRUCTURE.................21
2.1 Introduction........................................................................................................................................
2.2 Simple TLM Modelsfor Metal to Semiconductor Contacts ......................................................
2.3 ProposedTLM Structure andM odel................................................................................................
2.3.1
N ano-TLM Structure D esign.....................................................................................................
2.3.2
TLM Equivalent Circuit M odel and A nalysis ..........................................................................
2.4 D iscussion...........................................................................................................................................
2.5 Summary.............................................................................................................................................
CHAPTER 3. NANO-TLM FABRICATION.............................................................................................
3.1 Introduction........................................................................................................................................
3.2 StartingH eterostructure...............................................................................................................
3.3 ProcessF low ......................................................................................................................................
3.3.1
Ohm ic Metallization ..............................................................................................................
3.3.2
Mesa Isolation............................................................................................................................
3.3.3
Pad D eposition...........................................................................................................................
3.4 SEM A nalysis .....................................................................................................................................
3.4.1
Estimation of M etal Contact Length and Spacing................................................................
3.5 Summary.............................................................................................................................................
CHAPTER 4. NANO-TLM MEASUREMENT AND ANALYSIS.........................................................
21
21
25
25
25
33
36
37
37
37
38
40
41
43
44
44
45
47
4.1 Introduction........................................................................................................................................
4.2 M easurement of ConventionalTLM ...........................................................................................
4.3 M easurement andA nalysis of nano-TLM ....................................................................................
4.3.1
M easurem ent of nano-TLM ..................................................................................................
4.3.2
Interpretation of Sheet Resistances and the Contact Resistivity .........................................
4.3.3
C ontact Resistance and Its Scaling........................................................................................
4.4 Key FindingsandPossible Sources of Discrepancies................................................................
4.5 Summary.............................................................................................................................................
47
47
48
49
52
55
57
60
CHAPTER 5. CONCLUSIONS AND SUGGESTIONS.......................................................................
61
5.1 Conclusions........................................................................................................................................
5.2 Suggestionsfor F uture Work.......................................................................................................
7
61
62
8
List of Figures
Figure 1-1. Electron and hole mobility of group III-V compounds, in comparison with Si. [Fig. taken
from J.A . del Alam o [3]]...........................................................................................................................14
Figure 1-2. Cross section view of the source region of a typical source contact and its resistant
c o m pone nts...................................................................................................................................................16
Figure 1-3. Effect of contact-length scaling on overall contact resistance (Re=Rs.Rext in Eq. 1),
predicted using trilayer transmission line model. Fig. taken from N. Waldron [9]...............17
Figure 1-4. A Transmission Line Model (TLM) test structure with contact length Le, contact spacing
18
Ld and contact w idth W . .............................................................................................................................
spacings
lengths
(Le)
and
contact
with
various
structures
view
of
nano-TLM
1-5.
Top
down
Figure
(L d). Draw in g is not to scale.....................................................................................................................18
Figure 2-1 (a) Cross sectional view of a planar metal to thin-film semiconductor contact, and current
flow at the contact region. (b) The equivalent circuit model for the contact at one end of the
structure, assuming a very thin active layer characterized by sheet resistance Rsh..................22
Figure 2-2. Contact resistance - width product as a function of contact length for different specific
contact resistivity for Rsh = 200 Q /o . .....................................................................................................
24
Figure 2-3 A plot of total resistance of a TLM test structure.........................................................................24
Figure 2-4. (a) Top down view of a single nano-TLM test structure. (b) The 2D distributed resistive
26
circuit netw ork that illustrates (a) ....................................................................................................
Figure 2-5. Cross sectional view of nano-TLM with equivalent circuit network.............27
Figure 2-6. Four possible Kelvin measurement schemes to characterize nano-TLM test structures... 28
Figure 2-7 Current and voltage definition for the analysis of the 2D nano-TLM circuit network.......29
Figure 2-8. Contact resistance width product as a function of contact length for different specific
contact resistivity for Rsh = 200 f2/o, Rshm =0, using the 2D nano-TLM circuit model. RAB CD
34
= RAD _CB in th is case ...................................................................................................................................
Figure 2-9. The effect of Rsh, to the contact resistance scaling.................................................................35
Figure 2-10. The effect of Ld to the contact resistance scaling. Rh, is set to 0.01 /o for this case.........35
Figure 3-1 A cross sectional view of the starting heterostructure used to make nano-TLM test
8
stru ctu re s........................................................................................................................................................3
Figure 3-2. Nano-TLM process flow side view and top view......................................................................39
40
Figure 3-3. HSQ pattern with contact length of 200 nm, on top of Mo. ................................................
Figure 3-4 SEM image of Mo lines after metal dry etch, on top of InGaAs cap layer..........41
42
Figure 3-5. A top view of the m esa definition ............................................................................................
43
Figure 3-6 A SEM image of nano-TLM structure after mesa isolation. ...................
nano-TLM
test
structure....................44
Figure 3-7. Plane SEM view of a completed
Figure 3-8 Characterization of critical dimensions of a nano-TLM structure after oxide removal, to
carry out precise measurements on the structure...........................................................................45
Figure 4-1. Kelvin measurement methodology of a conventional TLM. Test structures shown here
48
has contact length Le and varies spacing d, - d4 ...........................................................................
Figure 4-2. Fabricated nano-TLM structure layout (top) and the four-terminal Kelvin resistance
50
measurement schemes (bottom) described in chapter 2 .............................................................
9
Figure 4-3. Typical measurements of I-V characteristics of nano-TLM structures with average
contact length Le = 276 nm and difference contact spacing Ld-......................................
51
Figure 4-4. Measured resistance values plotted against contact spacing Ld, for two different
measurement schemes on a set of devices with the same nominal contact length and different
contact sp acin g .............................................................................................................................................
52
Figure 4-5. Examples of fitting the theoretical model to experimental results. We change three
variables pc, Rshm and Rsh in the theoretical model to fit the experimental data. The values of L,
indicated in each chart are nominal. In the parameter extraction, actual measured values are
used. The sam e for Ld------........... - - .... .
-----......................................................................................
54
Figure 4-6. A comparison of the best contact resistances reported and the result obtained in this
w ork ................................................................................................................................................................
56
Figure 4-7. Contact resistance scaling trends comparison of this work and best reported contact
re sistan c e s.....................................................................................................................................................5
6
Figure 4-8. Comparison of contact resistance using lift off vs. dry etching to define metal lines. The
contact length Le = 3 pm ...........................................................................................................................
58
Figure 4-9. Comparison of contact resistance using sputtering and ebeam evaporation to deposit Mo
with thickness of 20 nm. The contact length Le = 3 pm.............................................................
59
Figure 4-10. Contact length variation within a nano-TLM test structure. ..................
60
10
List of Tables
Table 1. Extracted specific contact resistivity, semiconductor sheet resistance and Mo sheet
resistance for sets of experim ental data...............................................................................................................54
11
12
CHAPTER 1. INTRODUCTION
1.1.
Introduction to III-V CMOS
Silicon-based CMOS technology has been driving the scaling of logic gates for the past fifty years.
Following Moore's law, fabrication processes using Si channel and silicon dioxide gate dielectric
have pushed the gate length down to nanometer regime. However, in recently years Si CMOS has
reached its fundamental physical limits and there are concerns about the viability of Si-based CMOS
for gate lengths below 10 nm [1]. In order to extend Moore's law further, new technologies and
materials are being investigated to improve the performance and power consumption of logic
applications.
According to the International Technology Roadmap for Semiconductors (ITRS), alternative channel
materials with enhanced transport are anticipated solutions to the scaling problems of Si channel
MOSFETs. It is also projected that the first product with III-V (for n-channel) will be introduced in
2018 [2]. III-V compounds such as InGaAs or InAs have more than 10 times higher electron
mobility compared to Si at a comparable sheet charge density. This underlies the strong interest in
investigating III-Vs as an alternative channel material choice for future generations of deeply scaled
CMOS [3, 4].
13
IinAs
InAs
InAs
InAs
10,000-
InSb
lnGaAs
GaAs
E
InGaSb
U
Ge
1,000- Si
InSb
0GaSb
Ge
-
InGaAs
-S1
0
GaAs
100Ge
GaAs
I
0.54
0.56
InP
InAs AlSb
GaSb
InSb
Relaxed lattice constant
I
I
0.58
0.60
1
0.62
1
0.64
I
0.66
Lattice constant (nm)
Figure 1-1. Electron and hole mobility of group IlI-V compounds, in
comparison with Si. [Fig. taken from J.A. del Alamo [3]].
Figure 1-1 shows electron and hole mobility of some III-V compounds compared to conventional Si
MOSFETs [3]. It is obvious that the electron mobility of these III-V compounds is extraordinary,
which contribute to excellent transport characteristics and outstanding frequency response for logic
applications.
Recently, many exciting demonstrations of III-V MOSFETs have been published. This includes a
nanometer-scale InGaAs MOSFET exceeding the logic performance of Si at 0.5 V [5]. In order to
allow process integration of III-Vs to current CMOS technology, however, there are a few challenges
that need to be overcome. One of those is to find a high-permittivity dielectric material for the III-V
gate stack, which is the key to a MOSFET. The native oxide, Si0 2 of silicon technology is not
suitable for III-V compounds, which brings the challenge of finding a gate dielectric that minimizes
interface defects and has high stability for III-V MOSFETs. Another obstacle is the large difference
between electron mobility and hole mobility in III-V compounds. This is also a serious problem
because NMOS and PMOS transistors should have similar performance for CMOS logic circuits. In
14
order to increase hole mobility, compressive strain is introduced and improvements have been
demonstrated for some III-V compounds [6-8]. However, the performance of III-V PMOS is still
not satisfactory compared to other materials such as Ge. In addition to these challenges, a very low
ohmic contact resistance is also necessary especially since the contact dimensions are required to
scale proportionally with gate length. This last challenge has not received enough attention to the
present time, and will be the focus of this study.
1.2.
Motivation - Resistance Scaling in III-VMOSFET
Parasitic resistance is a serious concern in CMOS devices. As device footprint decreases, the source
resistance of transistors needs to be as small as 50 0 - pm to maintain high performance at low
voltage [3]. As shown in Figure 1-2., the source resistance is comprised of the contact resistance
between the pad metal and the contact metal (Rgad), the sheet resistance of the contact metal (Rm),
the contact resistance between the contact metal and the cap layer (RcaP), the contact resistance of
the cap layer and the extrinsic channel (Rgxt), and the resistance of the extrinsic channel (Rex,). The
total source resistance R, can be expressed as following:
Raa
d=+ Rm + Rcap + Rgxt + Rext
(1)
While the gate lengths of 111-V MOSFETs continue to scale down, the dimension of the contacts also
needs to be decreased aggressively.
It is predicted that the contact resistance will increase
dramatically when the contact length decreases to the nanometer regime [9]. Figure 1-3 shows how
the overall contact resistance Rc=Rs-Rext, increases with decreased contact length in various scenarios
[9]. As we see, when the contact length is shrunk to 10 nm the contact resistance with common
designs is expected to be two orders of magnitude higher than the target range,.
15
RPad
Rm
Rext
Figure 1-2. Cross section view of the source region of a typical source
contact and its resistant components.
The contact resistance between the metal and the cap layer RCaris a dominant component of Rs, and
the scaling of RCap with contact length is the focus of this work.
Decreasing RcaP is very
challenging with current fabrication processes, however it has been suggested that an ultra-low
contact resistance is possible with a highly doped InGaAs cap [10] and a metal-first scheme that
minimizes surface contamination [11, 12].
We use these approaches to improve the contact
resistance between the metal and the cap layer.
The scaling of metal to III-V semiconductor contact resistance in the nanometer regime has not been
studied experimentally. One goal of this project is to make such nano-scale contact structures to
examine the contact resistance scaling behavior and understand the physics of such small contacts.
A second goal of this study is to develop a fabrication scheme that is compatible with the current IIIV MOSFET process, in order to achieve a very low ohmic contact resistance in nanometer-scale
contacts.
16
1.E+05
1.E+04
1.E+03 -
en
A
1.E+02*.
1.E+01
...
+C
target
range
+
+
*D
1.E+00
1.E+01
1.E+03
1.E+02
Lc (nm)
1.E+04
Figure 1-3. Effect of contact-length scaling on overall contact
resistance (RcRARVX in Eq. 1), predicted using trilayer transmission
line model. Fig. taken from N. Waldron [9].
1.3.
Nano-TLM for HI-V CMOS
In order to fabricate nano-scale contacts that can achieve the targeted resistance range, an aggressive
design approach is required. The measurements and characterization of R, are usually done using the
transmission line method (TLM) [13]. The design of a TLM structure is illustrated in Figure 1-4. A
Transmission Line Model (TLM) test structure with contact length Lc, contact spacing Ld and contact width W In this
design, because the drawing dimensions are large, regular variations of contact length (L), contact
spacing (Ld) and contact width (W) due to fabrication process limitations are not very problematic.
For nano-scale contacts, however, the physical dimension of the contacts is smaller than the
resolution of a typical photolithography tool. To fabricate nano-scale contact structures for TLM
characterization, a new design that incorporates e-beam lithography is required.
17
Figure 1-4. A Transmission Line Model (TLM) test structure with
contact length Le, contact spacing Ld and contact width W
The design of a Nano-TLM structure should consider both fabrication limitations and
measurement needs.
It should also be compatible with existing III-V MOSFET fabrication
processes to allow process integration. Figure 1-5 shows the designed Nano-TLM structures for
this project. The metal lines are formed by e beam lithography so the contact length and spacing
are small and well controlled. The contact width is defined by a self-aligned dry etching process.
These structures each contain four contact pads that are connected to the ends of the metal lines, so
Kelvin measurements of the contacts are possible.
Mesa
Metal
LL
-------e-
Figure 1-5. Top down view of nano-TLM structures with various
contact lengths (Le) and spacings (Ld). Drawing is not to scale.
18
1.4.
Thesis Outline
In this project, we have developed a fabrication process for nano-TLM test structures that
incorporates e-beam lithography. We have measured and characterized such structures down to 200
nm in contact length and 300 nm in contact spacing using a four-point Kelvin measurement scheme.
A theoretical model was developed using a 2-D distributed circuit network. From comparison
between model and measurements, we have extracted the specific contact resistivity (p,), metal sheet
resistance (Rshm) and hetetostructure sheet resistance (Rsh) of the fabricated structures. We were able
to obtain a specific contact resistance of (1.16 +/- 0.058) x 10-9 Q - cm 2 , which is lower than the best
contact resistance reported for a TiW to InGaAs contact [11].
This thesis is organized in the following way. Chapter 2 discusses the theoretical modeling of nanoTLM test structures. Physical parameters that are relevant to the extraction of contact resistance are
defined and explained. We introduce the simple TLM model and extend it to our specific test
structure to set up a 2-D circuit network. The analysis of this circuit network is presented and
terminal resistance expressions are derived.
Chapter 3 focuses on the fabrication of nano-TLM test structures. We describe the hetetostructure
used for the fabrication, and a detailed process flow is discussed. Completed nano-TLM structures
are presented in this chapter, with a section on SEM analysis and measurement of contact lengths
and spacing.
In Chapter 4, we describe the electrical measurement scheme and discuss how the contact resistances
are analyzed using the TLM model.
Measurement data will be presented for two different
fabrication schemes and these data will be compared to show the advantage of metal first approach
over lift-off. We will then use the theoretical model developed in Chapter 2 to extract key
parameters of nano-TLM structures, and interpret the meaning of transfer length and contact
resistance in the context of nano-TLM. We will compare the experimental data and the theoretical
model, and examine the relationship of contact resistance as a function of contact length. The key
findings of the nano-TLM experimental results in combination of the theoretical model are
presented, and we project the performance of 10 nm contacts for III-V CMOS.
19
Finally, in Chapter 5, we summarize all of our findings of this nano-TLM contact project and
provide suggestions for future studies on III-V CMOS.
20
CHAPTER 2. THEORETICAL MODEL FOR DESIGNED
NANO-TLM STRUCTURE
2.1 Introduction
In this chapter, we build a 2D resistive circuit network to model the fabricated nano-TLM test
structures. Resistance expressions are derived for two different Kelvin measurement schemes. The
model is used in Ch. 4 to extract the relevant parameters characterizing the fabricated nano-TLM
structures.
2.2 Simple TLM Models for Metal to Semiconductor Contacts
The contact resistance in a III-V MOSFET is often modeled using a transmission line method (TLM)
[13]. A typical lateral contact between metal and a thin film is illustrated in Figure 2-1 (a). Due to
current crowding at the contact edges, current distribution under a contact and in the active layer is
not uniform. The TLM model uses a resistive circuit network to analyze this current distribution, as
shown in Figure 2-1 (b). In this simple model, the active semiconductor layer is assumed to be
infinitely thin, and is characterized by its sheet resistance (Rsh). pc is the specific contact resistance of
metal-semiconductor interface (L - pm 2 ), W is the contact width (pm) and Le is the contact length
(ptm). We express the infinitesimal resistance in the horizontal direction, dR, and conductance in the
21
vertical direction, dG, using these parameters. We neglect the sheet resistance of the metal layer.
The voltage drop between the points A and B can be expressed as following [13]:
L= metal contact length, Ld = metal contact spacing, W= metal contact width
-C
Cu entflow
(a)
Rs
A
1
dR= R--x
Le
---
-------
----
------
W
w
dG =-dx
Pc
dGI
C
1
x
0
x
L---------------L
.
(b)
Figure 2-1 (a) Cross sectional view of a planar metal to thin-film semiconductor contact, and current flow at the
contact region. (b) The equivalent circuit model for the contact at one end of the structure, assuming a very thin active
layer characterized by sheet resistance R~h.
cosh(x- -|RS/
V(x) = 1o -
c
sinh(Le - )Rsh/pc)
(2)
Where Io = total current (A). The current along A and B is then:
I (x) = I0 -
sinh(x - VRsT7p)
PC
sinh(Lc -)RSh/ pc)
22
(3)
The resistance across A and B, the contact resistance with unit i - pm, is the voltage drop across the
contact V(Le) divided by the current 10:
Rc = VRSh
In this expression, the term
-fp coth(Le - )Reh/pc)
(4)
pc/Rsh has units of length and represents the distance over which most
of the current is transferred between the metal and the active layer. This is denoted as the transfer
length:
Lr =
pc/Rsh
There are two limiting cases to this model. When the contact length Lc
coth(Lc/LT)
~
LT/Lc
(5)
0.5LT
,
then
and Re can be simplified to:
R Rcj
=c
(6)
This is the limit of a short contact in which, essentially, the current flows downwards over the entire
contact length.
For Lc > 1.5LT
,
coth(Lc/LT) ~ 1 and
Re =PC
LT
(7)
This is the limit of a long contact in which the current flows downwards on the scale of the transfer
length.
The effect of contact length scaling on contact resistance according to this simple circuit model can
be illustrated in Figure 2-2. As we can see, for long contact length (Le > LT), the contact resistance
has a minimum value that is independent of contact length. When Lc decreases below LT the contact
resistance increases exponentially. We also observe that the higher the pc, the earlier Re starts to
increase as Le scales down. This trend presents a major concern when contacts are decreased to the
sub-micron regime.
23
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
-
I.E+01
1.E+02
1.E+03
1.E+04
Lc [nm]
Figure 2-2. Contact resistance - width product as a function of contact
length for different specific contact resistivity for Rh = 200 a/o.
Using this circuit model, R, Rsh and pc can be extracted from TLM test structures as presented in
Figure 2-3. The total resistance measured can be expressed as:
RT =
W
(8)
+ 2Rc
RT
Slope = Rh/W
:
-
2Rc
0
Ld
Figure 2-3 A plot of total resistance of a TLM test structure.
24
By measuring the total resistance of these structures with different spacing Ld, a plot of total
resistance can be obtained, as show in Figure 2-3. Three parameters can be extracted from this plot.
The slope leads to the sheet resistance Rsh. The intercept at Ld
=
0 gives two times the contact
resistance 2Re. Once we have Rsh and Re, we can use formula above to compute pc and LT.
2.3 Proposed TLM Structure and Model
2.3.1 Nano-TLM Structure Design
The design of nano-TLM test structures follows the same concept of a simple TLM while taking into
account the fabrication limits for sub-micron patterns. As shown in Figure 1-5, an individual nanoTLM structure includes two nano-scale metal lines that are defined by e-beam lithography, and they
are connected to the measurement pads by extending the metal lines at an angle. The four-pad
design is necessary for Kelvin measurements that eliminate the voltage drop across angled metal
lines.
2.3.2 TLM Equivalent Circuit Model and Analysis
The nano-TLM test structure can be modeled using a 2D distributed resistive circuit network. Figure
2-4 (a) shows a single nano-TLM test structure, characterized by contact length Le, contact spacing
Ld and the width of mesa W. Fig. 2-4(b) shows the equivalent circuit representation of (a). Due to
the fact that Kelvin measurements will be performed, the resistance of the four metal lines that
provide access to the intrinsic structure is not modeled.
25
\.
w
(a)
Y
x
0
x
w
W
(b)
Figure 2-4. (a) Top down view of a single nano-TLM test structure. (b)
The 2D distributed resistive circuit network that illustrates (a).
In this circuit model, we use three parameters to characterize the nano-TLM network. They are the
sheet resistance of the semiconductor Rsh (Q/o), the sheet resistance of the metal Rsh. (9/o), and
specific contact resistivity of the metal-semiconductor interface pc (Q-pm). drm in Figure 2-4 (b) is
the elemental longitudinal resistance of the metal line:
Rsh
drm = Rs m dx
Lc
(9)
dgs is the elemental metal to metal conductance through the semiconductor, and we can use the
simple TLM model discussed earlier to write the total differential conductance between the two
metal lines as:
26
dgs =
1
2Rc + RSh
- d
1
=
dxL =
2pc -Rsh coth (
- dx
+R
(10)
L
Equation (10) is obtained by evaluating the cross-sectional resistance of the nano-TLM as shown in
Figure 2-5. We can simplify it to:
1
dgs=
RTLm
(11)
dx
Where
RTLM
=2- pc- Rscoth
C)+R
+
La
(12)
L
11 Lal
Figure 2-5. Cross sectional view of nano-TLM with equivalent circuit
network.
In equation (12), Rsh is the sheet resistance between the two metal lines. The transfer length along
the y direction is defined as:
LT1
=
(13)
We can now evaluate the total resistance according to different Kelvin measurement schemes. There
are a total of four measurement schemes that are illustrated in Figure 2-6. RCD,AB and RAB,CD are
27
equivalent, as well as RCB,AD and RAD,CB, and measurements for all four schemes are performed. We
seek to develop expressions for these four resistances in terms of the geometry of the structure and
RsA., Rsh and Pc.
A
Nano-TLM Network
C
A,
D
B
iC
VC+
B
D
RAB,CD
RCD,AB
RCBAD
RADCB
Figure 2-6. Four possible Kelvin measurement schemes to characterize
nano-TLM test structures
In order to analyze the resistance in these four measurements, we define the current direction and
voltage drop according to Figure 2-7.
28
/2(W
C
D
drm
I,(WAI)
IX)
i
I
I
x+dx
x
0
W
-
X
Figure 2-7 Current and voltage definition for the analysis of the 2D
nano-TLM circuit network.
Our goal is to solve for V(x), I(x) and 12(x) as defined in Fig. 2-7, so that expressions for the four
resistances in Fig. 2-6 can be found.
At location x, we can express dV(x) and dIj(x) using Kirchoff's law:
dV(x) = (1 2 (x)
-
I1(x))
-drm = (12 (x) - 11 (x))' Rs-
m dx
(14)
C
And
d11 (x) = -dI 2 (x) = -V(x)dgs = -V(x)
dx
RTLM
(15)
If we take derivative of above and combine with above we get:
d2 1(x)
d2
dx 2
_
(12 (x)
-
11 (x))
RsfTm
,~RL
(16)
From here, we solve for V(x) and I(x) for two different measurement schemes, RAB_CD and RADBC as
shown in Figure 2-6. Note that the evaluation of RABCD and RCDAB, as well as RAD_BC and RBCAD
should theoretically yield the same result.
29
For the case of RABCD, we know:
Il(x) = -12 (x)
(17)
At the ends, specifically:
I(0) = -I2(0) = -10;
11 (W) = -I
2
0;
(W) =
(18)
We can rewrite above as:
d 2 11 (x)
2 Rshm
dx2dX-
I(x) L.RM'=
Le(x-LRTL
(19)
0
We define a transfer length in the x direction:
V-c - RTLM|(
LTx =
2
(20)
Rshm)
Then (19) becomes
d211l(X)
11 (X)=
0
(21)
2
d
The solution to this differential equation is:
I,(x) = a -sinh
-
+ b -cosh
-);
(22)
With the boundary condition given in (18), we can evaluate a, b and write the solution for I,(x).
I(x) = Io[coth (W) sinh
We take derivative of (23), plug into (15) and get:
30
) -cosh
-
(23)
V (X)
RT LMIo
W
LTX
LTx
--
=[coth
cosh
x
--
sinh
-
Tx
(24)
Finally,
RABCD =
V(W)
RTLM
=
I
Lrx
csch
(W'
(25)
-
LTX
Next we solve for RADCB. In this case:
11 (x) + 12 (x)
= 1o
(26)
And, at the ends:
I1(0) = 0; 12(0) = I0; 1i(W) = 10; 12 (W) = 0;
(27)
We can rewrite (16) as:
d 21(X) 1 (x)
dx
2
2
Rshm
LC - RTLM
+
Rshm - 10
R
=
(28)
0
Then (28) becomes
d 2 1 1 (X)
dX 2
L,(X)
2 0
(29)
2L 2
L2
The solution to this differential equation is:
Ii(x) = a -sinh
(T
+ b - cosh --
Tx
)
x
10
(30)
2
With the boundary condition given in (27), we can evaluate a, b and write the solution for I,(x):
3IO
W
Ii(x) = [--csch
2
Lr
ITX
1
2
coth
W
Lr X
]sinh
31
x\1
-
TLx
0
+cosh
2
x
(-TX)
rx
-
lo
(31)
We take derivative of (31), plug into (15) and get:
V(x) =RTLM [
1
31
W
S(C
-
(32)
-
coth
i)
cosh
wnTXd
LTX/ t
s
+2
sinh(-)];
Lo VTx
Next we need to solve VCB,
VCB
with
=
VCA - VBA
=
V(O)-VAC;
(33)
w
VAC = foW12 (x)drm
(34)
=- Rshm
[4LTx
coth
- csch
-
W];
And,
V(O) =
(
LTx
2
csch(
\L
) coth
TX/
2
(35)
-LTxJ
Therefore,
VCB
Rshm' Jo [4LTx(coth (W)
-
sc~j~i)
w~+RTLMJO1
W] +
Tsch
Finally,
32
(36)
3 csch (W)
1(W\
- coth
)];
VCB
RADCB
-
--
Rshm4
[
-csch
LT(coth
(W
Lrx
W
-
LC
(TTX)(37)
-W] +
RTLM 3
[- [csch
LTx
2
W
1
Lrx
2
coth
-
Lr
'
We now have the expressions for the two Kelvin measurements schemes. These expressions give us
the relationship between the measured resistance value and the critical parameters for our nano-TLM
structure.
2.4 Discussion
To better understand these resistance expressions, we first examine the effect of Rshm. Assume Rshm =
0, which is the case when the effect of metal line sheet resistance is negligible, we can simplify
equation (25) and (37) to be:
RABCD =RADCBc=2"
-
~
pc- Ra
Lc
R-L
+
"oth
W
, pc/Ra
W
(38)
We see that the two measurement schemes arrive to the same expression, which makes sense
because current paths are evenly distributed along metal lines. For this case, we can illustrate the
contact resistance scaling trend as shown in Figure 2-8, for different values of Le and pc. Basically,
for Rshm = 0, both measurements replicate the simple TLM model.
33
p = 60- l.cm2
1.E+04
1.E+02
10
1.E+01
1.E+00
1.E+01
I.E+03
1.E+02
1.E+04
Lc [nm]
Figure 2-8. Contact resistance width product as a function of contact
length for different specific contact resistivity for RA = 200 Q/o, Rshm
=0, using the 2D nano-TLM circuit model. RABCD = RADCB in this
case.
To examine the effect of metal sheet resistance to the overall contact resistance, we vary Rsh, and
graph the resistance scaling trend in Figure 2-9. In this plot, we use a typical Rd of 200 a-pm and pc
of 1x 10-8
-cm2 . As we can see that the contact resistance scaling trend is similar to what is
observed in Figure 2-2, however, for the two measurement schemes the change of metal sheet
resistance have different effect on the contact resistance values. For RABCD, increasing Rshe causes
the decrease of overall contact resistance. The reason is the shortened current path in the x direction
(see Figure 2-7) due to increased drm. For RADCB, the contact resistance increases with Rshm and this
is expected because the current goes through the complete contact width W. We also observe that
the metal sheet resistance does not affect the contact resistance when the contact length is long (L, >
10 um). This also makes sense because larger contact length decreases the metal resistance and Rshm
does not contribute much to the contact resistance.
We also plot the dependence of RABCD and RADCB on Ld, as shown in Figure 2-10. We observe that
the change of contact spacing affect the resistance values more when Le is large. At very small
contact lengths, especially in the 10 nm range, the Ld dependency is minimal.
34
1.E+04
-Rshm
-Rshm
-Rshm
Rshm
1.E+04
= 0.01 Ohm/sq
= 0.1 Ohm/sq
= 0.5 Ohm/sq
= 1 Ohm/sq
1.E+03
1.E+03
2.
E
S1.E+02
1.E+02
C
1.E+01
1.E+01
1.E+00
0.1
0.01
1
10
1.E+00 '0.01
0.1
L, [um]
10
1
L, [um]
Figure 2-9. The effect of Rsh, to the contact resistance scaling.
a
1.E+03
1.E+03
1.E+02
1.E+02
1.E+01
1.E+01
-Ld
-Ld
-Ld
-Ld
1.E+00
-Ld = 0
-Ld
= 0.2un
-Ld = 0.7 um
--- Ld = I um
=0
= 0.2 um
=0.7 um
=I
0.01
um
1.E+00
0.1
1
10
0.01
0.1
1
10
Le [um]
Le [urn]
Figure 2-10. The effect of Ld to the contact resistance scaling. Rsh.
set to 0.01 £/o for this case.
is
Our next step is to fabricate and measure the nano-TLM test structures and use this model to extract
Rsh, Rshm, andpc.
35
2.5 Summary
In this chapter, we have introduced the transmission line method for characterizing metal to
semiconductor contacts.
We extend this concept to our nano-TLM structures and build a 2D
distributed resistive circuit network to analyze the resistance of these structures as a function of Rsh,
Rshm, and Pc. In the following chapters, we will describe the fabrication process and measurement
schemes of nano-TLM test structures and the extraction of these parameters. This will allow us to
utilize the theoretical model developed in this chapter and understand the contribution of each of the
three parameters to the total contact resistance in concern.
36
CHAPTER 3. NANO-TLM FABRICATION
3.1 Introduction
This chapter focuses on the fabrication process development and SEM analysis of the nano-TLMs.
Our process incorporates electron beam lithography to build structures with sub-micron contact
length. Different fabrication techniques are compared and optimal process flow is presented. The
fabricated structures will be measured and analyzed in the next chapter and the critical device
parameters will be extracted.
3.2 Starting Heterostructure
A description of the heterostructure used for this project is shown in Figure 3-1. The wafer was
grown by Intelligent Epitaxy Technology, Inc. (IntelliEPI) using molecular beam epitaxy (MBE).
The structure resembles an inverted high electron mobility transistor (HEMT) design. This structure
is chosen because it is the design of choice for current III-V CMOS research due to the reduced
leakage current compared to that of III-V HEMT model [14].
The cap layer consists of two layers of heavily doped (3 x 1019 cm-3 ) InGaAs: 5 nm thick layer of
Ino.6 5Gao.35 As followed by a 10 nm thick layer of Ino. 53Gao. 47As layer below. The higher In content in
the top cap layer is used to improve the ohmic metal contact resistance [15]. A 4 nm InP etch stop is
37
placed underneath the cap layer to facilitate the dry etching steps in the fabrication process. All other
layers are lattice matched to the InP substrate.
inP Etch Stop 4nm
InGaAs Channel tSnm
InAlAs Bufier 25nm
InP Buffer 6nm
InP Buffer 400nm
inP Substrate
Figure 3-1 A cross sectional view of the starting heterostructure used
to make nano-TLM test structures
3.3 Process Flow
In this section, we will describe the process flow for fabricating the nano-TLM test structures. An
overview of the process flow is shown in Figure 3-2. There are three basic modules that we describe
in separate sections. We first introduce ohmic metallization using Molybdenum for a non-alloyed
ohmic contact. Mesa isolation using a dry etching process is discussed next. Lastly, pad formation
using a lift-off process is described. The nano-TLM structure fabricated here uses Mo for nonalloyed ohmic contacts due to its reported low contact resistance [12].
38
I
(i) Starting heterostructure
I
(ii) Mo ohmic metal deposition
Top view
Side view
(iII) e-beam lithography, Mo etch
(v) SiO 2 etch
(iv) Si02 deposition
Channel
Top view
Side view
(vi) Mesa isolation
(viii) Pad deposition and lift-off
(vii) Photolithography.
Figure 3-2. Nano-TLM process flow side view and top view.
39
3.3.1 Ohmic Metallization
After the heterostructure is received from the grower, the process starts with wafer cleaning using 1:3
mixture of HCl:H 2 0. This solution removes native oxide to ensure high quality ohmic contacts.
Shortly after this, we RF sputter 40 nm of molybdenum (Mo) using sputtererAJA International Orion
5. The calibrated deposition rate is 1 A/s. Initially the Mo was deposited using e-beam evaporation,
but the contact resistance was found to be much higher, as suggested in literature [16].
Following Mo deposition, we define metal contact lines using e-beam lithography, because nanoTLM process requires a high resolution to achieve short contact length. We chose hydrogen
silsesquioxane (HSQ) as the e beam negative tone resist for its high resolution and good dry etch
resistance [17]. HSQ is spun on the wafer at 3500 RPM for 1 minute, and the substrate is pre baked
at 200C for 2 minutes before e beam exposure in order to achieve a high contrast [18]. The metal
line pattern is written in the HSQ layer using Raith 150, an e beam lithography tool based on a Leo
SEM column, with energy of 30 keV and area dose of 1050 pC/cm 2 . Right after exposure, the
written HSQ pattern is developed using 25% Tetramethylammonium hydroxide (TMAH) solution
for 70 s. At this point, the pattern written is observable under microscope and SEM. Figure 3-3.
shows a typical pattern formed after HSQ development on top of Mo layer, the contact length here is
around 200 nm.
Figure 3-3. HSQ pattern with contact length of 200 nm, on top of Mo.
40
In the next step we use dry etching to define thin metal lines using HSQ as etch mask. HSQ at this
point becomes a durable oxide layer that exhibits good etch resistance. To etch the Mo layer we use
the Plasmaquest, a reactive ion etcher/plasma enhanced chemical vapor deposition (RIE/PECVD)
tool. A combination of SF6 and 02 gases are used and the etch rate is approximately 3 A/s. These
gases constitute an effective etchant for Mo, but do not attack the InGaAs cap layer [19]. After
etching, metal line formation is verified by SEM. Figure 3-4 shows a typical SEM image of the
metal lines on top of InGaAs cap layer after the dry etching. In this figure, the HSQ on top of the
metal lines is still present. This is to protect Moly lines from the subsequent dry etch steps.Figure 3-4
SEM image of Mo lines after metal dry etch, on top of InGaAs cap layer.
Figure 3-4 SEM image of Mo lines after metal dry etch, on top of
InGaAs cap layer.
3.3.2 Mesa Isolation
The isolation of the nano-TLM structure is achieved by mesa etching. The definition of the mesa
area is illustrated in Figure 3-5. In addition to the mesa area, we also define 4 islands to hold the 4
metal line branches in place for pad connection later.
41
Islands
Mesa
Islands
Figure 3-5. A top view of the mesa definition.
We first deposit a layer of SiO 2 using STS CVD, a PECVD tool, at a temperature of 250 *C. The
deposition rate is separately calibrated for each run and the deposition thickness is measured using a
reference Si wafer. We find that the optimal SiO 2 deposition thickness is 60-80 nm, which can
withstand the mesa dry etch step and is easily removed afterwards.
A photo lithography step using OCG825 resist is used to define the mesa area as well as the four
islands on the corners of the metal lines. Photo resist was spun and pre-baked before a 7 s exposure.
After developing in OCG934 developer, the mesa pattern is observed under the microscope.
In the following steps, we create the mesa by first etching the SiO 2 film for 300 s using a
combination of CF4 and He gases. In this step, we use a DC bias of 100 V and ECR power of 200
W. With the SiO 2 layer patterned, we remove the photo resist and use SiO 2 as a hard mask for the
next etching step. It is worth to note that during the etching of SiO 2, the resist is hardened and
cannot be removed by acetone. We use MICROSTRIP to remove the leftover photo resist.
We now use the SiO 2 pattern as the hard mask for mesa dry etch. This etch is done in the
Plasmaquest using a combination of Ar, CH4 , H2 and 02 gases. The process time is 15 minute to
etch off~ 80 nm down to the InP buffer layer.
42
At this point mesa isolation is complete, and the structure is observed under SEM. Figure 3-6 shows
a SEM image of a typical nano-TLM structure after mesa isolation. The rough mesa edge is a result
of photoresist overexposure. This contributes to around 10% variation of the mesa width across
different test structures. Since we measure and normalize mesa width for each individual structure,
this variation does not affect the characterization of the finished test structures. Note also that at this
point there is still oxide on top of mesa and the metal lines, part of which will be removed next for
pad connection.
Figure 3-6 A SEM image of nano-TLM structure after mesa isolation.
3.3.3 Pad Deposition
The last step in the process is to deposit pads metal so subsequent device measurements can be
carried out. The pads are defined using AZ5214E resist, spun at 3000 RPM for 30 s and exposed for
9 s after a pre-bake step. We also introduced a flood exposure step to convert unexposed areas
soluble to result in a negative tone resist [20]. After developing, part of the metal lines are exposed.
Since these metal lines are still covered by oxide, we use buffered oxide etch (BOE) 1:7 to remove
the left over SiO 2. We then deposit pad metal layers Ti/Au (20 nm, 500 nm) using a Temescal FC2000 e beam evaporator, and use acetone lift-off to complete the definition of contact pads.
Following the pad patterning, we anneal the sample in a rapid thermal anneal tool at 400*C for 40 s
to improve the contact quality.
43
3.4 SEM Analysis
The completed nano-TLM structures and their critical dimensions are analyzed and measured using
SEM. Figure 3-7 shows the SEM image of a completed nano-TLM structure. The metal lines have
a length of about 15 pm to the pads. The structure shown here has SiO 2 on top of the mesa and
metal lines, which will be removed later after electrical measurements. This is detailed next.
Figure 3-7. Plane SEM view of a completed nano-TLM test structure.
3.4.1 Estimation of Metal Contact Length and Spacing
The contact length and spacing measurement is done after the electrical measurements that are
described in the next chapter. For this, we remove the oxide from the top of the metal lines. Figure
3-8 illustrates this process for the structure shown in Figure 3-7. The contact length (L,), contact
spacing (Ld) and mesa width (W) can then be accurately measured by SEM and we obtained L, = 190
nm, Ld =310 nm and W = 4.02 pm with a measurement accuracy of 15 nm. These measurement
values are used in subsequent chapter for data analysis.
44
The smallest contact length we obtain from a working structure is 162 nm, with a contact spacing of
308 nm. There are a few limiting factors for further decreasing the metal line width and contact
spacing. First is the proximity effect during the e-beam lithography step. When the metal lines are
drawn close together, the electron energy has an overlap and the dose on the metal lines is increased.
This causes the thickening of the metal lines and narrowed spacing between metal lines. To correct
this effect, lower dose factors can be applied to the area where the metal lines are placed close
together. The thickness of the HSQ resist is another limiting factor for the metal line resolution. We
need the HSQ layer to be above 100 nm so it can stand the dry etch step, and the e-beam resolution
gets worse with increased resist thickness. To have a better resolution, a thinner resist that can
withstand the dry etching process has to be engineered.
Figure 3-8 Characterization of critical dimensions of a nano-TLM
structure after oxide removal, to carry out precise measurements on the
structure.
3.5 Summary
In this chapter the process flow of nano-TLM structure fabrication was described. Detailed process
steps were presented for each of the three modules: ohmic metallization, mesa isolation and pad
deposition. This is followed by SEM analysis of the finished device. We have achieved shows a
contact length of 162 nm with contact spacing of 308 nm, more than 1Ox smaller than a conventional
45
contact. In the next chapter, we will focus on measurement and characterization of the completed
nano-TLM test structures.
46
CHAPTER 4. NANO-TLM MEASUREMENT AND ANALYSIS
4.1 Introduction
In this chapter, we will discuss the measurement schemes used to characterize the fabricated nanoTLM structures. The theoretical model will then be used to analyze the measurement data and extract
three contact parameters of concern: the specific contact resistivity (pc), metal sheet resistance
(Rshm)
and semiconductor sheet resistance (Rsh) of the nanocontacts that we have fabricated.
4.2 Measurement of Conventional TLM
The measurement methodology for a nano-TLM structure is based on the conventional TLM
measurement, even though the design and analysis of a nano-TLM structure is more complicated. In
this section we discuss ways the traditional TLM structures are characterized.
The contact resistance measurement using a conventional TLM is shown in Figure 4-1. As we
discussed in chapters 2, the contact resistance, sheet resistance and transfer length of a contact are
evaluated by plotting measured resistance against contact spacing (Ld), for the same contact length
(Le). Here we adapt the four-terminal contact resistance method, also known as the four-terminal
Kelvin resistance [21], because it eliminates the probe resistance and the contact resistance between
47
the probe and the test structure. In this method, current is forced through terminal C and D, and the
voltage is measured across A and B. What we measure is then the total resistance from contact 1 to
contact 2.
r-- -- -- -------
I
Ld3
I
A
B
C
D
Ld4
Figure 4-1. Kelvin measurement methodology of a conventional
TLM. Test structures shown here has contact length Le and varies
spacing di - d4.
4.3 Measurement and Analysis of nano-TLM
The measurement of nano-TLM test structures is an extension of the conventional method
introduced above. The structures are designed for TLM type measurements using the four-terminal
Kelvin resistance methodology. In this section we discuss how the measurements are set up and how
48
the data is collected. We will also analyze the collected data using the theoretical model developed
in chapter 2 to evaluate the critical parameters that characterize the device contact resistance.
4.3.1 Measurement of nano-TLM
The measurement schemes for the nano-TLMs were described in chapter 2. Similar to the
conventional TLM measurement, we also use the four-terminal Kelvin resistance method. This way
we will eliminate the probe resistance, the probe to substrate contact resistance as well as minimize
the contribution of the pad sheet resistance and pad to Mo contact resistance.
The structure layout
and the measurement schemes are shown in Figure 4-2. On the top of the graph, we show the
structure layout for a series of nano-TLM structures. These individual structures have the same
nominal contact length but different contact spacing.
The bottom of the graph are the four
measurement schemes for an individual nano-TLM structure, which was described in chapter 2.
49
- -I
~
- -I
RCDAB
RAB,cD
RcAD
RADCB
Figure 4-2. Fabricated nano-TLM structure layout (top) and the fourterminal Kelvin resistance measurement schemes (bottom) described
in chapter 2.
The measurements are taken using an Agilent 4155A semiconductor parameter analyzer. To acquire
high accuracy data, we use the VMU ports of the analyzer for voltage measurement, and the SMU
ports for current injection. Typical I/V measurement results are graphed in Figure 4-3. We took the
measured voltage difference from the two VMU ports, and plot that against the current measured
from SMU ports. The total resistance is then the inverse slope of the plot.
50
2 E-A
*5
1.5E-04
5.OE-05
0.OE+00
-5.0E-05
A
-1.OE-04
-1.5E-04
-2.OE-04
-0.025
*
+Ld
=270 nm
-ELd
=
380 nm
d=50n
*-
Ld=780nm
-5-0.015
0,Ld
=1.00 um
.0
-0.005
0.005
0.015
0.025
V [V]
Figure 4-3. Typical measurements of I-V characteristics of nano-TLM structures with
average contact length Le = 276 nm and difference contact spacing Ld.
Next, we plot the extracted resistance values against contact spacing. A typical R vs. Ld graph is
shown in Figure 4-4 for a set of structures with the same nominal contact length but varying contact
distance. There are a few details worth noting here. First of all, the measured contact lengths are not
exactly identical across structures that have the same nominal contact length. This is due to the
process variation when the metal lines are defined by e-beam lithography. We observed that when
contact spacing is small, especially under 500 nm, the contact length turns out to be larger than the
drawing dimension, and we believe this is caused by proximity effects and the resolution limit of the
e-beam lithography tool. Because the metal contact length is in the nanometer regime, it is important
to have accurate measurements of the device dimensions. Due to this variation, the transmission line
method used for a conventional TLM (as seen in Figure 2-3) is not appropriate. Note that RABCD
and RADCB values are very close to each other with RABCD consistently above RADCB- This reflects
the case of Rshm.~ 0 discussed in chapter 2, that when the metal sheet resistance is negligible, the two
measurement schemes arrive at the same value. In the next section, we will discuss how we
characterize these nano-TLM structures individually and how to use the theoretical model to extract
the relevant resistance parameters.
51
int-4-5 Die 1 Row 15
600
R(ABCD)
+ R(ADCB)
500
Lc = 365nm
400
Lc=357nm
E
300
Lc 363nm
Lc=364nm
200
Lc=371nm
100
Lc =392nm
0
0
0.2
0.4
0.6
0.8
Ld [ur]
1
1.2
1.4
Figure 4-4. Measured resistance values plotted against contact spacing Ld, for two different
measurement schemes on a set of devices with the same nominal contact length and different
contact spacing.
4.3.2 Interpretation of Sheet Resistances and the Contact Resistivity
Our next step is to extract the relevant resistance parameters that characterize these structures. These
are: the metal to cap specific contact resistivity pc (n-cm2), the metal sheet resistance Rshm (nIc) and
the semiconductor sheet resistance Rs (92/o). In order to do this, we develop a Matlab program and
use an optimization module to find pc, Rsh, and Rsh values that best fit the experimental data.
In the Matlab program, we first make an initial guess of the parameter values, and list a range of
values these parameters can take on. We then calculate the expected resistance values using the
theoretical model developed in chapter 2 and compare them to the experimental data. The program
will start from the initial guess and search through values in the given range to find the best fit for the
experimental data.
52
The fitting is done point by point. For each structure,
RAB
CD represents the average of RABCD and
RCD_AB, and RADCB is the average of RADCB and RCBAD. We require the best fit to give the least
error across two sets of measurement (RAB CD and RADCB) for a group of 4-6 devices with the same
nominal contact length but different contact spacing that are located side by side on the chip. As we
see in Figure 4-4, the contact lengths change with the contact spacing, so we use the measured
contact length and spacing for each specific structure in the Matlab program.
Figure 4-5 shows examples of the fitting results for two sets of structures on the same chip, with
different nominal contact lengths. We plot the measurement data against the 2D circuit model with
optimized pc, Rshm and Rsh, to show the best fit of the model to the experimental results. The extracted
parameters for each set of devices are indicated in the inset of these figures.
We use data collected from two different chips, and the fitting results are listed below in Table 1.
Each row in the table represents a set of devices with the same nominal contact length and different
metal spacings. In this table, <Le> (nm) is the average measured contact length. The optimization
tool in Matlab uses the method of least squares, therefore the error shown in this table represents the
least-squares error.
53
Int-4-5 Die 1 Row 14, Le = 323 nm
500
* 2D Circuit Model
450
8
Int-4-5 Die 1 Row 14, Lc = 323 nm
500
a 2D Circuit Model
450
Experimental Data
400
400
350
350
300
300
250
250
200
200
150
= 0.098
100
150
0-um'
= 0.098 O-um2
eP
Ra= 336 a/sq
Rh. =1 mO/sq
100
Rh = 336 0/sq
R *m
1 mQ/sq
50
Experimental Data
50
0
0
0
0.5
1.5
1I
0
a
Int-4-5 Die 1 Row 15, L, = 370 nm
600
2D Circuit Model
Experimental Data
500
a2D Circuit Model
Experimental Data
500
400
400
300
300
200
0
eU
200
= 0.18 O-um2
100
Ra= 347 0/sq
*
= 0.18
100
i
0.5
a-um'
Rh 347 0/sq
RA.= 1m/sq
R
0
0
1.5
Ld [um]
Int-4-5 Die 1 Row 15, Le = 370 nm
600
1I
0.5
Ld[umI
=1 mn/sq
0
1.5
0
0.5
Ld[umI
1I
1.5
Ld[um]
Figure 4-5. Examples of fitting the theoretical model to experimental results. We change three
variables pc. R, and R~h in the theoretical model to fit the experimental data. The values of L,
indicated in each chart are nominal. In the parameter extraction, actual measured values are
used. The same for Ld.
Table 1. Extracted specific contact resistivity, semiconductor sheet resistance
and Mo sheet resistance for sets of experimental data.
Sample #
Int-4-5
Int-4-5
Int-4-5
Int-4-5
Int-4-5
Int-4-5
Int-4-3
Die 1
Die 1
Die 1
Die 1
Die 2
Die 2
Die 4
Row
<L,> (nm)
pc (Q-um2)
Rsh (0/sq)
Rsh,(mQ/sq)
13
14
15
16
3
4
2
248
323
369
415
336
374
270
0.045
0.098
0.18
0.14
0.45
0.52
1.9
315
336
347
361
280
297
492
0
0
0
0
0
0
0
54
Error (
2
-um2)
0.0204
0.0174
0.0160
0.0111
0.313
0.180
0.112
Considering the measurement error and structure to structure variations, the extracted parameter
values are rather consistent. The algorithm we used gives the smallest metal sheet resistance value
we allow, and changing the lower bound below 1 mf/o does not change the fitting result. This
means that the Mo sheet resistance has negligible contribution of the metal resistance to the
measured resistance. In this case, we report the Rshm as 0.
4.3.3 Contact Resistance and Its Scaling
Next, we compare our result with some of the best values reported in the literature. For Mo to
Ino.53Gao 47As contact, the best contact resistance reported is 1.1
-pm2 [22]. For Mo on abrupt
InAs/InGaAs heterojunctions, the specific contact resistance is lowered to 0.5 +/- 0.3 g-pm2 [23].
With TiW as contact metal, a 0.7 f-pm2 contact resistance was reported [11]. In this study, we
obtain an average Mo to n+ Ino.65Gao. 35As contact resistance of (0.116 +/- 0.058) Q-tm 2 . To the best
of our knowledge, this is the best contact resistance ever reported on InGaAs cap.
We compare our result with reported data so far, and plot it in Figure 4-6. The contact resistivity
obtained in this work is the lowest among the ones reported so far. We also plot the scaling trend
when contact length Le is decreased to 10 nm in Figure 4-7. There are two sets of data from this
work. The trend line is plotted using the averaged pe, Rsh and Rshm values measured here, i.e. 0.116 Q
-um 2 , 340 O/o, and 0.1 m/ro, respectively in the theoretical model. The experimental data points
are calculated by the following:
Rc -W = (RABCD - Rsh - La)/2;
(1)
From the plot we can see that the contact resistance in this work gives a 12.7 Q um contact resistance
when Lc is decreased to 10 nm. This value is significantly lower than what has been reported before
and is a step forward in achieving a low source resistance for future III-V CMOS.
55
* Mo on InO.53GaO.47As
* TIW on InO.53GaO.47As
Cr on InO.53GaO.47As
* Mo on InAs/lnO.53GaO.47As Abrupt Heterojunction
0 This work, Mo on InO.65GaO.35As
100
I
10
E
1
I
This work
0
0
0 0.1 I1.OE+19
1.OE+20
Electron concentration (cm)
Figure 4-6. A comparison of the best contact resistances reported and the result obtained in this work.
1.E+03
-Best Moly contact
Best TiW contact
-This work (Model)
+ This work (experimental)
1.E+02
1.E+01
- - --
- - - -"
-
- - --
1.E+00
0.01
0.1
1
10
Le [um)
Figure 4-7. Contact resistance scaling trends comparison of this work and best reported contact resistances.
56
4.4 Key Findings and Possible Sources of Discrepancies
Using an optimization module in Matlab, we extracted three parameters that characterize a typical
nanometer scale contact structure. We find that even though the metal contact length is small (198410 nm), the metal sheet resistance does not contribute much to the overall resistance. As a result,
the two different measurement schemes give almost identical values which is the Rshm = 0 case
described in Chapter 2.
The low contact resistance in this work was obtained after a few fabrication process development
considerations. During the process development, we tried different fabrication approaches and find a
few factors that affect the contact resistance. First of all, the surface preparation of the sample
contributes contact quality. We compared results from two different approaches. The first approach
is to evaporate the metal layer right after sample cleaning and then define metal lines using dry
etching. The second approach is to define the metal line pattern using e-beam resist and then
evaporate metal and do lift-off. Conventional TLM measurements for the two approaches are
plotted in Figure 4-8. These measurements are done on TLM structures with micron scale contact
length, and
Ld
are measured using SEM. The contact resistance calculated using the lift off approach
is 0.15 Q -cm, which gives a specific contact resistivity of 7.Ox10~6 Q-cm 2 . This is about an order of
magnitude higher than the dry etching approach, which gives a contact resistance of 0.0082 Q-cm
and specific contact resistivity of 2.0x10-
2-cm2.
This phenomenon was also mentioned in
literature [12]. This contact resistivity is still higher than what we obtain in nano-TLM structures.
This is because the metal lines are only 20 nm thick for this specific experiment. This is a lot thinner
than the nano-TLM structures we measured (60 nm Mo thickness). The thinner metal layer has
higher sheet resistance due to current crowding. Also, the metal is evaporated instead of sputtered.
57
350
300
250
C200
150
100
* Mo - Lift off
50
mMo-etch
0
0
20
10
30
Ld [PM
Figure 4-8. Comparison of contact resistance using lift off vs. dry
etching to define metal lines. Mo is evaporated in this experiment. The
contact length Le = 3 pm.
We also compared two different metal deposition techniques, e-beam evaporation and sputtering.
Figure 4-9Figure 4-9 shows the measured resistances for these two cases using traditional TLM test
structures. These structures are prepared to test Mo sheet resistance and the pad to Mo contact
resistance. For this experiment the Mo thickness is 20 nm for both sputtered and evaporated Mo.
The sputtered Mo gives a lower metal sheet resistance, 0.97 Q/o and metal to pad contact resistance,
3.7x 10~8 n-cm 2 , compared to the evaporated Mo, 5.6 f/o and 4.1 x 108 (-cm
2,
relatively. Note that
the metal sheet resistance for sputtered Mo is much higher than what we report for nano-TLM test
structures. The Mo sheet resistance contribution to the nano-TLM resistance measurement turned out
to be very small and could not be accurately extracted. We consider this sheet resistance negligible
and report it as 0.
58
40
+ Sputtered Mo
35
3 Evaporated Mo
e
30
0
25
20
15
10
0
0
10
20
Ld
30
40
[pm]
Figure 4-9. Comparison of contact resistance using sputtering and
ebeam evaporation to deposit Mo with thickness of 20 nm. The
contact length Le = 3 sm.
With these findings, we are able to develop a metal first process using sputtering and achieve an
ultra-low contact resistance that is within the acceptable range when the contact length is shrunk to
10 nm.
Due to fabrication variations and measurement inaccuracies, there are a few sources of error. First of
all, the contact length of the metal lines varies from structure to structure, and also within the same
structure. The two metal lines in a nano-TLM test structure may have different measured contact
length and they also change along the metal contact. Figure 4-10 is an illustration of the contact
length variation between two metal lines. For this structure there is a 2.4% discrepancy, which is
representative of structures we measured. In all cases we use the average of the two contact lengths.
Since the contact dimensions are crucial in nano-TLM characterizations, these variations contribute
to the measurement discrepancies.
59
Figure 4-10. Contact length variation within a nano-TLM test
structure.
The mesa width measurement is another source of error. The mesa edge around the contact metal
lines are not completely straight after dry etching process, and the width on the left side could be
different from the width on the right side.
From the measurements we obtain, we observe a
maximum 5% discrepancy. To minimize these discrepancies, we use the average values for structure
dimensions.
4.5 Summary
In this chapter, we have characterized the nano-TLM test structures by using four-terminal Kelvin
measurements. We have then used an optimization tool in Matlab to extract the contact resistance,
semiconductor sheet resistance and metal sheet resistance of the fabricated structures. The contact
resistance values acquired have an average value of 1.16x 10-9
-cm2 which is lower than the lowest
contact resistance values reported so far. In the next chapter, we will discuss more about contact
resistance scaling trend down to 10 nm contact length, and provide suggestions for future study on
111-V nano-scale contacts.
60
CHAPTER 5. CONCLUSIONS AND SUGGESTIONS
In this thesis, we have developed a fabrication process for nano-TLM test structures to analyze the
resistance of metal/III-V contacts and a theoretical model that describes the resistance behavior of
these structures. We fabricated and tested Mo on n+ InGaAs contacts with contact length from 198
nm to 410 nm. Our model and analysis suggests that with proper surface preparation and metal
deposition technique, an ultra-low contact resistance can be achieved even when the contact length is
scaled down to the nanometer scale. In this chapter, we summarize the key findings of this work and
suggestions for future work are provided.
5.1
Conclusions
In this project, we tested different fabrication techniques to build a nanometer-scaled metal to III-V
contact and developed a process that can provide the lowest contact resistance incorporating a metal
deposition-first fabrication process. We conclude that a metal-first approach using a sputtered metal
deposition technique gives the lowest contact resistance and can be adapted to the current III-V
CMOS processes.
To analyze the fabricated test structures, we developed a theoretical model using a 2D circuit
network. We use this model to extract the contact resistance, the metal sheet resistance and the
semiconductor sheet resistance by fitting the model to the experimental data. We report on seven
61
sets of experimental test structures with contact lengths between 248 nm to 415 nm. We evaluate
each data point and plot them against the scaling trend predicted by our theoretical model. The best
obtained average values are: pc = 0.116 Q-um 2 and Rsh = 340 Q/o. The extracted metal sheet
resistance is very small relative to the other components and it cannot be extracted in a reliable way.
This means that the metal sheet resistance does not contribute to the overall resistance of the
structure. With the assumption that Rshm = 0, we simplify the theoretical model and arrive to simple
TLM expressions that are consistent with our measurements. We also compared this scaling trend
with the best contact resistance values reported in literature.
The process flow developed can be incorporated to the 111-V CMOS process to form source contacts.
Other contributions of the source resistance scaling still need to be examined to achieve an overall
understanding of the nanometer scale source contacts.
5.2 Suggestions for Future Work
We suggest a number of future studies that can continue the source resistance scaling research
described in this work.
*
Extend the current fabrication process to include an etch step to etch cap and channel
between metal lines in order to study the cap to channel contact resistance, which is another
important component of the source resistance. This should complete the source resistance
scaling study for 111-V MOSFETs.
*
Carry out a 3D simulation using TCAD to model the nano-TLM test structures, which will
help us better understand carrier transport in the contact region and the physics of nanometer
scale contacts in general. It will also help us find the optimal dimensions for a good ohmic
contact.
* Develop a fabrication process for 111-V MOSFET that incorporates the nano-TLM fabrication
process, to decrease overall device footprint.
* Extend study to smaller contact lengths down to 10 nm.
62
.
Extend study to FinFETs.
63
64
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