Design of Micropower Operational Amplifiers
by
Surapap Rayanakom
S.B., Electrical Science and Engineering (2005)
Massachusetts Institute of Technology
Submitted to the Department of Electrical Engineering and Computer Science
in Partial Fulfillment of the Requirements for the Degree of
Master of Engineering in Electrical Engineering and Computer Science
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2006
C 2006 Surapap Rayanakorn. All rights reserved.
The author hereby grants to M.I.T. permission to reproduce and
distribute publicly paper and electronic copies of this thesis
and to grant others the right to do so.
Author...............
.................................
Department of Electrical Engineering and Computer Science
May 25, 2006
Certified by.....
........................
Brendan J. Whelan
Design Section Manager
VI-A Company Thesis Supervisor
Certified by..............
........................................
Hae-Seung Lee
Science
Computer
ering
and
Engun
Electrical
.Profes or of
M.I.T. Thesis Supervisor
Accepted by...
Arthur C. Smith
Chairman, Department Committee on Graduate Theses
MASSACHUSETTS INSTrrTITE
OF TECHNOLOGY
AUG 14 2006
LIBRARIES
BARKER
2
Design of Micropower Operational Amplifiers
by
Surapap Rayanakom
Submitted to the
Department of Electrical Engineering and Computer Science
May 25, 2006
In Partial Fulfillment of the Requirements for the Degree of
Master of Engineering in Electrical Engineering and Computer Science
Abstract
The operational amplifier is a fundamental building block for electronic devices and
systems. The advancement of modem electronic technology has been setting more
performance demand on the underlying integrated circuits including the operational
amplifier. Reduction in power consumption and improvement in speed are some of the
most important requirements. To address these concerns, this thesis presents a design of
micropower Class AB operational amplifiers which has the ratio of gain bandwidth
product to supply current higher than that of an existing IC. The design is in a 0.6im
CMOS process. The input stage of the design has the folded-cascode architecture that
allows the input common-mode range down to negative supply voltage. The Class AB
output stage swings rail-to-rail and has the ratio of maximum current to quiescent current
greater than 100. The bias cell of the operational amplifier is designed to consume only
6% of the total supply current. The thesis concludes the operational amplifier design
with two frequency compensation options. The one with simple Miller compensation has
a unity gain frequency of 360kHz with 61.5 degrees of phase margin at IOOpF load while
consuming 20ptA supply current. The other with the hybrid of simple Miller
compensation and cascode compensation offers an improved unity gain frequency of
590kHz at the same loading and power condition.
VI-A Company Thesis Supervisor: Brendan J. Whelan
Title: Design Section Manager, Linear Technology Corporation
M.I.T. Thesis Supervisor: Hae-Seung Lee
Title: Professor of Electrical Engineering and Computer Science
3
4
Acknowledgements
I am very grateful to Brendan Whelan, my VI-A company thesis supervisor. This
project would have been impossible without his supervision. I appreciate his time and
patience in guiding me throughout the course of the project. I learned something new
every time we talked, and I became a better engineer by working with him. This
internship opportunity with him was one of the most rewarding experiences for me.
There is nothing more I can ask for from him as a teacher and as a friend.
I would like to thank Professor Harry Lee for supervising the thesis. I learned
tremendously from his advice, insightful comments, and his class. His generous support
on the thesis is much appreciated.
I would also like to recognize other design managers and engineers at Linear
Technology for their technical help. I extend my thanks to Bill Jett and Frank Johnson
for their advice on several occasions. I also benefited from the discussions with Brian
Hamilton, John Wright, and John Morris.
I would like to acknowledge all the teachers in my life. Particularly, I would like
to thank Ajam Tossaponne Suwannachart for her teaching and constant encouragement
during my high school years.
Last but not least, I am forever grateful to my parents and sister. It is impossible
to list all the things they have done for me, all the moments we have shared together, and
all the contributions they have made to my success. Their unconditional and neverending love and support are beyond I can thank, and I am blessed to have my family. I
am also indebted to my grandparents' love and everything they have contributed to my
life. Finally, I would like to extend my gratitude to my aunts, my uncles, and my cousins.
5
6
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION
15
1.1 OVERVIEW OF MICROPOWER OP AMP IN LTC1541
15
1.2 LTC]541 LIMITATIONS AND PROBLEM DEFINITION
16
1.3 THESIS GOAL
17
1.4 THESIS ORGANIZATION
19
CHAPTER 2 INPUT STAGE
21
CONSIDERATION OF TRANSISTOR TYPE IN INPUT STAGE
21
2.1 CONSTRAINT 1: INPUT COMMON-MODE RANGE
21
2.2 CONSTRAINT 2: LARGE DC OPEN-LOOP GAIN
25
2.3 CONSTRAINT 3: INPUT OFFSET VOLTAGE
26
CHAPTER 3 OUTPUT STAGE
31
3.1 OUTPUT STAGE BACKGROUND
31
CONFIGURATION OF OUTPUT TRANSISTORS
31
OUTPUT STAGE BIASING
32
DESIRED CHARACTERISTICS OF OUTPUT STAGE
32
3.2 TRANSLINEAR-LOOP-BIASED OUTPUT STAGE
33
QUIESCENT CURRENT
34
MINIMUM CURRENT IN OUTPUT TRANSISTORS
37
MAXIMUM CURRENT IN OUTPUT TRANSISTORS
38
VARIATION OF QUIESCENT CURRENT OVER SUPPLY VOLTAGE RANGE
40
3.3 MODIFIED TRANSLINEAR-LOOP-BIASED OUTPUT STAGE
41
CHAPTER 4 BIAS CELL
45
7
4.1 REFERENCE CURRENT IN BIAS CORE
45
4.2 START-UP CIRCUIT
48
4.3 REFERENCE VOLTAGES BIAS CIRCUIT
50
CHAPTER 5 FREQUENCY COMPENSATION
55
5.1 PROPOSED
MICROPOWER OP AMP WITH SIMPLE MILLER COMPENSATION (SMC)
55
60
5.2 CASCODE COMPENSATION
5.3
PROPOSED MICROPOWER OP AMP WITH HYBRID ASYMMETRIC EMBEDDED
CASCODE COMPENSATION (HAECC)
64
CHAPTER 6 FINAL RESULTS AND CONCLUSION
69
FINAL RESULTS
69
DiscusSION
72
FUTURE WORK
74
APPENDICES
75
APPENDIX A SCHEMATICS AND CHARACTERISTICS OF 20pA MICROPOWER OP AMP
77
WITH SIMPLE MILLER COMPENSATION (SMC)
APPENDIX B SCHEMATICS AND CHARACTERISTICS OF 20FtA MICROPOWER OP AMP
95
WITH HYBRID EXPLICIT CASCODE COMPENSATION (HECC)
APPENDIX C SCHEMATICS AND CHARACTERISTICS OF 20ptA MICROPOWER Op AMP
WITH HYBRID SYMMETRIC EMBEDDED CASCODE COMPENSATION (HSECC)
APPENDIX D SCHEMATICS AND CHARACTERISTICS OF 20iA MICROPOWER
OP AMP
WITH HYBRID ASYMMETRIC EMBEDDED CASCODE COMPENSATION (HAECC)
8
113
131
LIST OF FIGURES
Figure 1-1: Photodiode Amplifier with Single-supply .................................................
19
Figure 1-2: Inverting Amplifier with Dual Supplies......................................................
19
Figure 2-1: B asic Input Stage ......................................................................................
22
Figure 2-2: Fully Differential Basic Input Stage [8]......................................................
23
Figure 2-3: Folded-Cascode Input Stage (adapted from [9] to have the PMOS input pair)
...................................................................................................................................
24
Figure 2-4: Fully Differential Folded-Cascode Input Stage [9].....................................
25
Figure 2-5: Input Stage of the Proposed Micropower Op Amp...................................
26
Figure 2-6: Input Stage with Transistor Sizes...............................................................
28
Figure 3-1: Complementary Source Follower Configuration [18]...............................
31
Figure 3-2: Complementary Common-Source Configuration [18] .............................
32
Figure 3-3: Translinear-Loop-Biased Class AB Output Stage .....................................
34
Figure 3-4: Quiescent Current IQ vs. Supply Voltage
VDD
in Translinear-Loop-Biased
O utput Stage........................................................................................................
. . 41
Figure 3-5: Modified Translinear-Loop-Biased Class AB Output Stage .....................
Figure 3-6: Quiescent Current IQ vs. Supply Voltage
VDD
in Modified Translinear-Loop43
B iased O utput Stage..............................................................................................
Figure 3-7: Currents in Output Pair,
IDM2P
42
and IDM2N vs. Load Current ILOAD in Modified
Translinear-Loop-Biased Output Stage ...............................................................
43
Figure 4-1: Bias Core Generating Reference Current [25], [26]..................................
46
Figure 4-2: Bias Core with Start-up Circuit..................................................................
48
Figure 4-3: Reference Voltages Set Up in Bias Cell ...................................................
50
Figure 4-4: Schem atic of Bias Cell................................................................................
52
Figure 4-5: IREF,
ISU, VNCASCODEB,
and VPCASCODEB
vs.
VDD ----
-.......................
...
53
Figure 5-1: Simplified Schematic of Proposed Micropower Op Amp with Simple Miller
C ompensation (SM C) ...........................................................................................
57
Figure 5-2: Schematic of Proposed Micropower Op Amp with Simple Miller
C om pensation (SM C) ...........................................................................................
9
58
Figure 5-3: Frequency Response with CL=100pF and RL=100kQ of Proposed
Micropower Op Amp with Simple Miller Compensation (SMC) ........................
59
Figure 5-4: Small-Signal Transient Response with CL=IOOpF and RL=100kK2 of Proposed
Micropower Op Amp with Simple Miller Compensation (SMC)........................
59
Figure 5-5: Class A Op Amp with Cascode Compensation (Adapted from [30])........ 61
Figure 5-6: Simplified Schematic of Proposed Micropower Op Amp with Embedded
Cascode Compensation (ECC) Only ...................................................................
62
Figure 5-7: Frequency Response with CL=100pF and RL=100k
I Oof Proposed
Micropower Op Amp with Embedded Cascode Compensation (ECC) Only..... 63
Figure 5-8: Frequency Response with CL=lOpF and RL=lOOkQ @ IL=- 1 .0 , -0.5, 0.0, 0.5,
1.OmA of Proposed Micropower Op Amp with Embedded Cascode Compensation
(EC C ) Only ..........................................................................................................
. 63
Figure 5-9: Small-Signal Transient Response with CL=lOOpF, RL=100kK2, and IL=0.5mA
of Proposed Micropower Op Amp with Embedded Cascode Compensation (ECC)
O nly ...........................................................................................................................
64
Figure 5-10: Simplified Schematic of Proposed Op Amp with Hybrid Asymmetric
Embedded Cascode Compensation (HAECC)......................................................
65
Figure 5-11: Schematic of Proposed Micropower Op Amp with Hybrid Asymmetric
Embedded Cascode Compensation (HAECC)......................................................
66
Figure 5-12: Frequency Response with CL=OOpF and RL=100kK2 of Proposed
Micropower Op Amp with Hybrid Asymmetric Embedded Cascode Compensation
(H A EC C) ..................................................................................................................
Figure 5-13: Frequency Response with CL=lOpF and RL=l00k
67
@ L=-l.O, -0.5, 0.0, 0.5,
1.OmA of Proposed Micropower Op Amp with Hybrid Asymmetric Embedded
Cascode Compensation (HAECC).........................................................................
67
Figure 5-14: Small-Signal Transient Response with CL=lOOpF, RL=100kQ, and
IL=0.5mA of Proposed Micropower Op Amp with Hybrid Asymmetric Embedded
Cascode Compensation (HAECC).........................................................................
68
Figure 6-1: Frequency Response of 20pA Micropower Op Amp with HAECC
Compensated Down to Have cDm = 450 at 15pF Load to Compare with MAX9914 72
10
Figure 6-2: Frequency Response of 5pA Micropower Op Amp with HAECC
Compensated Down to Have Dm = 450 at 50pF Load to Compare with MIC861 ... 73
11
12
LIST OF TABLES
Table 1-1: Electrical Characteristics of LTCJ541 [1]...................................................
16
Table 1-2: Design Specifications of Micropower Op Amp ..........................................
18
Table 6-1: Characteristics of 20pA Micropower Op Amp with Simple Miller
C om pensation (SM C ) ...........................................................................................
69
Table 6-2: Characteristics of 20ptA Micropower Op Amp with Hybrid Asymmetric
Embedded Cascode Compensation (HAECC).....................................................
70
Table 6-3: Comparison of Unity Gain Frequency between the Proposed 20ptA
M icropower Op Amps and M AX9914 ..................................................................
73
Table 6-4: Comparison of Unity Gain Frequency between the Proposed 5pA Micropower
Op Amps and M IC 861.........................................................................................
13
74
14
Chapter 1 Introduction
The operational amplifier is a fundamental building block in electronics. It is
employed in a wide range of applications including monitoring circuitry, cellular phones,
portable devices, medical instrumentation, and solar-powered systems [1], [2]. Linear
Technology Corporation launched LTC1541 Micropower Op Amp/Comparator/Reference
in February 1998. The IC has been incorporated in many consumer products such as
smoke detectors, infrared receivers, battery-powered systems, and portable phones [1].
1.1 Overview of Micropower Op Amp in LTC1541
The micropower op amp, which is part of LTC]541, was fabricated in a 4.Opm
CMOS process. It has a unity-gain frequency of 12kHz while consuming a typical
supply current of 1.5pA. Electrical characteristics of LTCJ541 with 3V supply voltage at
25 "C from [1] are summarized in Table 1-1.
Specifications are at 251C.
VDD
=
3.OV and Vss = OV.
Primary Characteristics
Symbol
GBW1
Parameter
Gain Bandwidth Product
CL = OpF
RL
100k1
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
CL = OpF
RL = 10OkQ
is
Supply Current
No load
VINCM
Input Common-Mode Range
-
Vos
Input Offset Voltage
VINCM
VOUT
VOUTH
Output High Voltage
Value
Condition
RL =
1.5V
=
100k to Vss
Typical
Max
-
12
-
kHz
93
114
-
dB
-
1.5
-
pA
Vss
-
-
-
0.7
mV
-
-
V
VDD
-
0.07V
' Implying the gain bandwidth product per supply current GBW/ Is= 8 MHz/mA @ CL =OpF
15
Unit
Min
VDD
-
l.3V
V
VOUTL
Output Low Voltage
RL =
1O0kf to VDD
Vss +
-
-
V
0.05V
ISOURCE
Output Source Current
-
0.6
0.95
-
mA
ISINK
Output Sink Current
-
1.2
1.8
-
mA
Parameter
Condition
Min
SR
Slew Rate
Av=
CMRR
Common Mode Rejection Ratio
Secondary Characteristics
Symbol
Value
1V/V, IV Step
@ DC
Unit
Min
Typical
Max
-
0.008
-
V/ps
63
-
-
dB
74
-
-
dB
-
3
-
pVP-P
VINCM = Vss to VDD -1.3
PSRR
Power Supply Rejection Ratio
@ DC
en
Input Noise Voltage
f= 0.1 to 10Hz
Table 1-1: Electrical Characteristics of LTC154J [1]
1.2 L TC1541 Limitations and Problem Definition
The standard of electronic equipment and systems has been constantly developing
for the past years. This condition has imposed more demanding performance
requirements on the supporting semiconductor products, particularly lower power
consumption and higher speed. As a result, these foundational integrated circuits
including op amps have to continually improve to meet the need.
Currently, there are a few general-purpose low-power op amp ICs in the market.
One of them is MAX9914 1MHz, 20yA, Rail-to-RailI/O Op Amps with Shutdown by
Maxim Integrated Products. It has a 1MHz gain-bandwidth product at 15pF load with 45
degrees of phase margin [3]. Another well-known one is MIC861 TeenyTm UltraLow
Power Op Amp by Micrel, Inc. With static supply current of 4.6ptA, MIC861 offers a
225kHz gain-bandwidth product at 50pF load with approximately 45 degrees of phase
margin 2 [4].
Although the Micropower Op Amp in LTC]541 consumes an extremely low
supply current, its speed is far too low to accommodate the need of modem technologies
such as medical instrumentation [5] and portable devices. This thesis seeks to identify
The phase margin is not given in [4]. It is estimated from the datasheet that the IC has 2-3 periods of
decayed oscillation in the small-signal pulse response at 50pF load.
2
16
the fundamental limit of speed versus power consumption and propose an improved
general-purpose micropower op amp whose speed to supply current ratio is higher than
that of LTC1541. Other crucial performance specifications are large DC gain and wide
input common-mode range that includes the negative supply voltage. In addition, op amp
characteristics such as stability, input offset voltage, output swing, and output drive
capability have to be considered as well. Some target applications of the new generalpurpose low-power op amp include battery-powered systems, portable electronic devices,
and safety sensors.
1.3 Thesis Goal
This thesis aims to design a two-stage operational amplifier that satisfies the
performance specifications in Table 1-2 and can operate between supply voltages of 2.5V
up to 6.OV. The specifications are defined at supply voltage of 2.5V, and they are
ordered by their relative importance in the descending order. The first three parameters:
unity gain frequency, DC open-loop gain, and supply current, are central in the design
process. The other requirements on the primary list must be met, unless their sacrifice
exceptionally enhances one of the first three characteristics. The design should also
satisfy all the secondary specifications.
Specifications are at 25*C.
VDD
= 2.5V and Vss
=OV.
Primary Specifications
Symbol
Parameter
Condition
Value
Unit
GBW 3
Gain Bandwidth Product
CL = I00pF
RL= IOOkQ
> 0.3
MHz
Large-Signal Voltage Gain
CL = IOOpF
(DC Open-Loop Gain)
RL = 1OkW
> 100
dB
Supply Current
No Load
<21
pA
AVOL
Is
> VDD VINCM
Input Common-Mode Range
-
1.25V
And must include
V
negative supply voltage
3 Implying the gain bandwidth product per supply current GBW/ Is> 14.3 MHz/mA @ CL = IOOpF. Note
that GBW/ Is @ CL = OpF is going to be higher than that @ CL = IOOpF.
17
VOS
(Untrimmed) Input Offset Voltage
VOUT
VOUTH
VOUTL
High Output Voltage
Low Output Voltage
ISOURCE
Output Source Current
ISINK
Output Sink Current
VINCM = 0.65V
-OmA
ISOURCE
=
ISINK =
1.mA
CL
= IOpF
RL= I00kK2
CL = lO0pF
RL= IO0kK2
mV
< 5
- 0-3V
V
< Vss + 0.3V
V
> 1.0
mA
> 1.0
mA
Value
Unit
> 0.15
V/ps
> VDD
Secondary Specifications
Symbol
Parameter
Condition
SR
Slew Rate
Av=
CMRR
Common Mode Rejection Ratio
@ DC
> 60
dB
PSRR
Power Supply Rejection Ratio
@ DC
> 60
dB
t
0.1% Settling Time
Av=
< 10
ps
1VI/V, IV Step
IV/V, IV Step
Table 1-2: Design Specifications of Micropower Op Amp
With these specifications, the new design is expected to be a more versatile lowpower general-purpose op amp than the Micropower Op Amp in LTC1541. The unitygain frequency is specified to be greater than 300kHz so that the op amp can
accommodate a broader range of applications. At this frequency, the op amp has to be
properly compensated and well stable with 1 OOpF load.
For supply current, the new op amp must take less than 21 pA in order to be
power-friendly to portable equipment and battery-powered systems. This power
restriction implies that the ratio of gain-bandwidth product to supply current has to be
greater than 14.3 MHz/mA at 1 OOpF load, which is higher than that of the Micropower
Op Amp in LTC1541 or 8 MHz/mA at OpF load.
Another main specification of the new design is a large DC open-loop gain of
more than 100dB. The large DC open-loop gain is important for low-frequency detecting
applications such as gas sensors because it minimizes the gain error. Moreover, in these
applications, the input voltage is small and a large gain is needed to get a measurable
output [6].
The input common-mode range of the new micropower op amp is specified to be
wider than half of the supply voltage and must include the negative supply voltage. This
specification is imposed because a number of single-supply applications, such as the
photodiode amplifier in Figure 1-1, have to take the input at the ground level.
18
In
addition, many dual-supply applications such as the inverting amplifier in Figure 1-2 are
often biased at its mid supply voltage or ground [6].
2.5V
Figure 1-1: Photodiode Amplifier with Single-supply
+1.25V
VIN
1.25V
Figure 1-2: Inverting Amplifier with Dual Supplies
1.4 Thesis Organization
Chapter 1 gives an overview of low-power operational amplifiers and their
applications, defines the problem of interest, and sets the goal that this thesis seeks to
achieve.
The rest of the thesis is organized as follows. Chapter 2 discusses how the target
specifications constrain the design of input stage of the micropower op amp, and
demonstrates the input stage details resulted from the restrictions. Chapter 3 extensively
19
describes the output stage. The design of bias cell is presented in Chapter 4. Chapter 5
looks into the limitation on the gain bandwidth product in the context of frequency
compensation of two-stage op amps. It then presents the complete micropower op amps,
and selected simulation results. Lastly, Chapter 6 discusses the results and concludes the
thesis work. In addition, the appendices provide a complete collection of simulation
results of the proposed micropower op amp with different frequency compensation
schemes.
20
Chapter 2 Input Stage
This chapter examines a number of common input stages and explains how the
input stage design is shaped by the constraints from specification. It first reasons why the
PMOS input pair is chosen over the NMOS one. The related constraints, namely input
common-mode range, DC open-loop gain, and input offset voltage, are then discussed in
the design context. The input common-mode range requirement sketches the preliminary
topology of the input stage. The final architecture is the result of the open-loop gain
restriction. Lastly, the input offset voltage constraint instructs how the transistors have to
be sized.
Consideration of Transistor Type in Input Stage
One of the primary reasons that PMOS transistors are chosen for the input stage is
the fact that its input common-mode range includes ground for single-supply operation
[6]. There are a number of other benefits for having PMOS transistors as the input stage
rather than NMOS transistors [7]. First, PMOS transistors have less 1/f noise. Second, a
PMOS input stage results in a higher slew rate than an NMOS one.
The following sections explain the design details of input stage based on the
consideration of the related constraints: input common-mode range, DC open-loop gain,
and input offset voltage.
2.1 Constraint 1: Input Common-Mode Range
One of the primary specifications of the op amp in design is to have the input
common-mode range that includes ground for single-supply operation as well as midsupply voltage for dual-supply operation. This section discusses different input stage
architectures and reasons why the single-ended folded-cascode configuration is used as
the input stage in the proposed micropower op amp.
Most op amps employ one of the following common topologies or their variants
as the input stage: single-ended or fully differential basic input stage, or single-ended or
21
fully differential folded-cascode input stage. The four common topologies are shown in
Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4 respectively [8]-[0].
The basic input stage in Figure 2-1 has the maximum common-mode input of VDD
- (VSGP + VDS,SAT),
which is high enough to accommodate mid-supply inputs for dual-
supply applications. However, its common-mode range cannot go down to ground for
single-supply operation, and therefore does not meet the requirement. The lowest of the
input range is only
2
VDS,SAT
VGSN - VSGP + VDS,SA T,
above the ground (In general,
which amounts to be approximately 1VDSSAT to
VGSN>
VSGP because the input pair is usually
weakly inverted due to its large width, but the current mirror transistors are strongly
inverted).
VINM
VINP
VOUT
Figure 2-1: Basic Input Stage
The basic input stage may also be implemented as a fully differential architecture
shown in Figure 2-2, simplified from [8]. Its common-mode input level can go up to
- VSGP - VDS,SAT
as 2VDS,SAT
VDD
(same as that of Figure 2-1) and can go down beyond the ground to as low
- VSGP.
Although it satisfies the input common-mode range specification, it
requires a common-mode control circuit, which in turn increases power dissipation in the
op amp. The second stage must also have differential inputs, which increases the power
dissipation even more. These extra implementation costs are its disadvantages, especially
for the op amp in design in which the total supply current has to be minimized.
22
VCMC
from common-mode
control circuit
VINM
VINP
VOUTI
VOUT2
VBIAS
Figure 2-2: Fully Differential Basic Input Stage [81
The folded-cascode topology in Figure 2-3, adapted from [9] to have the PMOS
input pair, has the same input common-mode range as the fully differential basic input
stage in Figure 2-2. Therefore, it satisfies the requirement. In addition, its input
common-mode range remains the same if a cascode current mirror or a wide-swing
current mirror is used instead of the simple current mirror shown in the schematic. The
only drawback is it consumes more current than the basic input stage for the same tail
current to implement the folded section. However, a wider input common-mode range
that includes ground for single-supply operation is more important. The input stage of
the proposed micropower op amp is based on this topology.
23
M15
VINP
E--=
M16
VINM
VOUT
VBIAS
4<
cc~
Figure 2-3: Folded-Cascode Input Stage (adapted from 191 to have the PMOS input pair)
The differential form of the folded-cascode input stage is shown in Figure 2-4 [9].
This topology has the same additional implementation need as the differential basic input
stage, and therefore is not appropriate for the author's design. Other input stage
topologies explored include the complementary input stage in [21]. It allows rail-to-rail
inputs. However, it needs a transductance control circuit to ensure that the input stage
has a constant transconductance across all the input range. This additional requirement
increases design complexity and results in more power consumption. Therefore, the
complementary input stage is not selected for the proposed micropower op amp.
24
VB2
vINP
F-<=:3vINM
vouTi
--
"
voUT2
VBI
Figure 2-4: Fully Differential Folded-Cascode Input Stage 191
2.2 Constraint 2: Large DC Open-Loop Gain
The specified DC open-loop gain is at least 100dB. This high DC open-loop gain
is one of the design goals because the op amp has to support many applications that
require very large gains at low frequencies. These applications include gas sensors and
other transducers such as thermocouples, bridges, hall-effect sensors and photodiodes
[10]. This high gain characteristic is not easy to achieve in a two-stage op amp.
The simple current mirror in the chosen folded-cascode input stage in Figure 2-3
has low output resistance, compared to Wilson current mirrors and cascode current
mirrors, and thus making it more difficult to meet the required DC open-loop gain. In
addition, VDS of M16 in the simple current mirror changes with the operating supply
voltage and the bias of the output stage, and thus undesirably causing the bias current in
M16 to slightly vary upon those condition changes.
25
VB2
VNM
VNP
VOUT
VB1
Figure 2-5: Input Stage of the Proposed Micropower Op Amp
The wide-swing current mirror [9] is chosen for the input stage of the proposed op
amp as shown in Figure 2-5. It has high output resistance and has the highest bandwidth
per drain current ratio after the basic Wilson mirror and the improved Wilson mirror [11].
In addition, the wide-swing current mirror can operate with voltage down to 2 VSDSAT
across its output side, unlike both forms of Wilson current mirrors and the cascode
current mirror that require at least VSG + VSDSAT across the output side to operate
properly, i.e. the transistors stay in the saturation region. With the increased output
impedance of the current mirror, the op amp not only has a higher DC gain, but also
higher CMRR and PSRR [10].
2.3 Constraint 3: Input Offset Voltage
The input offset voltage comes from two sources. They are systematic offset
voltage and random offset voltage [12], [13]. The systematic offset voltage is caused by
asymmetry in the op amp architecture. The random offset voltage is the consequence of
mismatches in transistor pairs such as the differential input pair. The contribution of the
26
random offset voltage on the total offset voltage is more significant than that of the
systematic offset voltage when the first stage gain is large. This condition is particularly
true in the author's design in which most of the op amp gain is from the input stage.
(Simulation results show the input stage gain is on the order of 104 in the proposed op
amp). As a result, only the random offset voltage will be considered in this section.
Transistor pair mismatch comes from the difference in their threshold voltage
VT
and current factor , [14]. In general, the variation in the threshold voltage and current
factor becomes less as the transistor area increases. The following calculation of input
offset voltage for transistor sizing is based on the model in [14] and [15]. The standard
deviation of the threshold voltage difference A VT is described by
AVT
where AT is a constant depending on the process technology (usually less for smaller processes)
(2-1)
The standard deviation of the relative current factor difference A8 is described by
where Af3 is a constant depending on the process technology
(2-2)
According to [14], the variance of the gate-source voltage difference in a
transistor pair with the same drain current can be described as
O(v
0 S)= WL [AL[
+
vT)
(vGS
4
2
_
where Vos is the offset voltage (or gate - source voltage difference of a transistor pair)
(2-3)
Equation (2-3) implies the effect of the current factor mismatch reduces as the overdrive
voltage decreases. In almost all circumstances, the threshold mismatch dominates the
offset voltage. For a 0.7pm CMOS technology, the effect of the threshold mismatch is
more significant than the current factor mismatch for overdrive less than 1.4V [14]. In
27
the author's design where the total supply current is under 20pA, most transistor pairs are
weakly or moderately inverted. Therefore, the offset voltage can be estimated by only
considering the component due to threshold mismatch as
2 (VOS)
AV
2
T
WL
(2-4)
This following section explains transistor sizing and input offset voltage consideration.
M15
10/15
2
M17
40/2
VINM
VB2
vINP
M1
M12
50/10 50/10
4
4
M16
10/15
2
M18
40/2
-C=>
M13
20/2
VB1
MB19
3/40
15
VNMIRRORB
voOUT
M14
20/2
MB20
3/40
15
Figure 2-6: Input Stage with Transistor Sizes
The input stage with transistor sizes is depicted in Figure 2-6. The input referred
offset voltage is the result of the mismatch in the following 3 transistor pairs: Ml 1 -M12,
M15-M16, and MB19-MB20. Transistor pairs M17-M18 and M13-M14 do not affect the
input offset voltage. It is also not necessary to consider the offset voltage due to any
mismatch in the output stage because that offset voltage is divided by the gain of the
input stage when referred to the input [10], [14].
The micropower op amp is specified to have an untrimmed input offset voltage of
less than 5mV. In order to achieve good yields in IC production, the transistors are sized
28
such that three standard deviations of input offset voltage is less than 5mV. This
condition corresponds to yielding 99.7% of fabricated ICs having untrimmed input offset
voltage within +/- 5mV [16]. The transistor sizes in the final input stage design in Figure
2-6 evolve from preliminary hand calculation and simulation. The differential input pair
is sized to be very wide for two main reasons. The first goal is to make the input pair
having the highest transconductance gm, compared to other transistor pairs in the input
stage, so that the offset voltage due to the other pairs is attenuated as implied by (2-6).
The other intention is to keep its gate-source voltage small so that the input commonmode range is increased. For the wide-swing current mirror, transistor pair M15-M16 is
sized to be long to get high output impedance. The cascode transistor pair M17-M18 of
the mirror is sized to be wide to have high transconductance [10]. The following
calculation shows the course of preliminary hand calculation of input offset voltage using
the final transistor sizes.
Require 3a(Vos) < 5mV
o(Vos)< 5mV
3
(2-5)
From the input stage in Figure 2 - 6,
(ll2
)07
152
+["7mB19
2
(2-6)
From (2-6), the transconductance ratio
and
K
mii
r'")
9.B19
cmii
simplify the calculation. Hence, the calculated offset voltage will be an overestimate.
(VOS)=Val
12 +152
+
B192
(2-7)
29
For 0.7pm CMOS technology [14]4,
AVTP=22mVpm
AVTN=1 3mV -m
a-l1 2 (AVGS) = A"T
(WL)
2 (AV
=
A
[4. (50pm)- (10pm)]
1
(22mV -pM)2
[2 -(10[m) .(I5Rm)]
2
(WL)
B192
GS ) =A
gm)2
=
2
(WL)B1 9
=(22mV
0.242mV 2
16mV 2
2
= 0.094mV 2
(13mV m)
[I5 - (3gm) -(40gm)]
o-(VS) = /0.242 + 1.61+ 0.094mV
5
o(VoS)= 1.39mV < -mV
3
If the input offset voltage were not a concern, the author could size input stage
transistors to be extremely small. This sizing would make the parasitic capacitances
minimal, so the unity-gain frequency would be higher without any other changes.
However, in practice, it is desirable for the op amp to have low input offset voltage, and
the input offset voltage specification must be met. Therefore, some transistors in the
input stage need to be sized to have large areas as shown in the calculation and Figure
2-6.
4 The constant A vrTfor 0.6pm CMOS technology was not found in literature, so the one for 0.7pjm CMOS
technology is used instead. This choice will result in a conservative estimate of offset voltage because this
constant decreases as the process becomes smaller.
30
Chapter 3 Output Stage
In this chapter, the background on output stages and desired characteristics of the
proposed op amp are first explored. Then, the design of the output stage employed in the
proposed op amp is explained.
3.1 Output Stage Background
The output stage is needed for op amps that have to drive resistive loads or heavy
capacitive loads [17]. This section presents a brief introduction on the configuration of
output transistors and the classification of output stage biasing.
Configuration of Output Transistors
The arrangement of the output transistors in an output stage can be classified into
two basic configurations. They are complementary source-follower and complementary
common-source as shown in Figure 3-1 and Figure 3-2, respectively [18]. Since the
proposed micropower op amp needs to have a rail-to-rail output stage, the
complementary common-source configuration is used in the design.
VDD
M2P
vINA
vOUT
M2N
vINB
Figure 3-1: Complementary Source Follower Configuration [181
31
VDD
VpNA
~M2P
VOUT
M2N
VINB
Figure 3-2: Complementary Common-Source Configuration 1181
Output Stage Biasing
The three common biasing schemes for the output stage are Class A, Class B, and
Class AB. Class A output stage is easy to implement, but it dissipates power all the time
and cannot source or sink current from the load more than its quiescent current value.
Class B output stage saves power because it is inactive when there is no signal, but it has
crossover distortion when transitioning between the active input ranges of the two
devices. Class AB output stage keeps both of the output transistors on with a small
amount of biasing current so it does not have the distortion problem [19]. Moreover, it
can source or sink current when required by the load.
Desired Characteristics of Output Stage
The output stage of the proposed micropower op amp has to be able to swing railto-rail. For the biasing, the output stage should maintain relatively constant quiescent
current across the operating supply voltage of 2.5V to 6.OV. Moreover, because of the
output source/sink current specification, it needs to have a large ratio of the maximum
sourcing/sinking current to the quiescent current. As a result, the output stage of the
proposed micropower op amp is in the complementary common-source configuration and
is biased by a Class AB scheme described in the next sections.
32
3.2 Translinear-Loop-Biased Output Stage
The biasing scheme of the proposed op amp output stage evolves from the
translinear-loop-biased configuration shown in Figure 3-3. This translinear-loop-biased
topology was presented in [20] and extensively investigated in [21]-[22]. It is also called
the Yin-Yang output stage due to the symmetry of biasing [23]. This output stage
exhibits Class AB characteristics. It can operate down to a supply voltage of 2VGs
2VDS if cascode current sources are used, and down to 2 VGS
+ VDS
±
if simple current
sources are used. In addition, this output stage topology does not add noise and offset to
the op amp, provided that the two current sources biasing the bridging transistors, M23
and M26, are implemented by the existing bias currents in the input stage [21]. The
signals from the input stage,
VinA
and VinB, feed directly to the gate of their respective
output transistor and also feed to the other transistor through the bridging transistors,
M23 and M26. While M23 and M26 actively bias the output transistors, nodes
VINB are always of high impedance regardless of supply voltage.
33
VINA
and
M24
I1
Iv2 =2a1
3/1
M25
3/1
M2P
3/1
3/1
b
VINA
VINB
VOUT
M26
M231
1/1 13/1
a
M2N
1/1
a
b
M22
1/1
M21
12= 2aI1
1/1
I1
Figure 3-3: Translinear-Loop-Biased Class AB Output Stage
In the NMOS translinear loop, M23 is sized to be a times as wide as M21 and
M22 to accommodate 12 which is 2a times as large as I1. The output device M2N is sized
to be b times as wide as M21 and M22 so that the output pair can sink and source large
currents and have high gm's. The same geometry guideline applies to the PMOS
translinear loop. In addition, PMOS transistors are sized to be 3 times as wide as their
NMOS counterparts because the hole mobility is approximately one third of the electron
mobility. This decision is made so that PMOS transistors have the same
transconductance and the same gate-source voltage as NMOS transistors under the same
condition, i.e. equal bias currents [18].
Quiescent Current
When the output stage is at rest, the quiescent current can be calculated from
either of the translinear loop. Consider the NMOS translinear loop M21-M22-M23M2N, the quiescent current is determined as follows, similar to an example in [18].
34
From the translinear loop,
GS21 +
GS22
= VGS23 +
GS2N
(3-1)
Since VGS =
21D
VTN±
for NMOS transistors in saturation assuming the effect of
channel length modulation is negligible.
(3-2)
±
v72
FT2
D21
D22
TN22N22
+F
21
T2
F
VTN23 +j
2
D232
T2N4F
TN2N
2I2
D2N
fCX(I
(3-3)
Since VTN21
andVTN22
=VTN2N
VTN 23
(3-4)
(Note that VTN22
ID21
> VTN21.
D22
21
(W)
The body effect causes VTN 22 >
D23
_
because
SB
22 > OV).
D2N
(W)23
22
VTNO
J2N
(3-5)
D22
D21
'D2N2=
W__
F 21
+
F__
D23
__
-
F__
D23
22
F
(3-6)
-2
L
_
ID22
D2ND21
2D2N
D23
22
2
(3-7)
35
ID2N
_ID21
+L
+
2-
L
D23
2-
2
21
(3-8)
In the quiescent state, half of 12 flows through M23 and the other half goes through M26.
-~-
2
12
Q = D2N
b[f
(3-9)
Since 12 = 2aI
(3-10)
IQ
= ID2N
1
(3-11)
The conclusion is the same for the PMOS translinear loop because of the
symmetry. The actual quiescent current may slightly differ from (3-11) from two causes.
The first one is all the transistors do not have the same VDs's, but the effect of channel
length modulation is ignored in the derivation. The other error source contributes to the
deviation from calculation if the transistors are not well in strong inversion. This
deviation is particularly true in the author's design because the currents of the translinear
transistors (except the output pair) are only in the range of 0.2 - 2.OgA. Although the
transistors have
VGS > VTN,
their overdrive voltages are less than 50mV, and thus operate
in moderate inversion. From the simulation of one of the proposed op amps in Figure
3-6, the quiescent current is found to be within 11% of the calculated value, i.e. the
simulated quiescent current is 8.33pA at
VDD
=
2.5V while the calculated value is
9.85pA.
As far as the current allocation is concerned, the total supply current should be
invested in the output pair transistors as much as possible so that the output stage
transconductance, gm2, is high. This design choice is made in order to put the op amp's
second pole location as high as possible. However, the remaining current has to be
enough for the first stage for two reasons. One is the tail current of the differential pair
36
input cannot be too small, otherwise the slew rate is too low. The other need is the
summing current mirror in the input stage has to be high enough so that the mirror pole
does not affect the op amp frequency response near the crossover point. In the proposed
op amps, the author distributes approximately half of the total current in the output pair
transistors, and verifies by simulation that the current left for the first stage after the bias
cell and the biasing of the output stage is sufficient.
Minimum Current in Output Transistors
When the load requires the op amp to source or sink current, one of the output
pair transistors is driven hard while the other is retained active with a small bias current.
For example, if the load draws current from the output stage, VSG2P increases to allow
more drain current in M2P. As a result, VSG26 reduces, following the translinear relation
VSG 24 + VSG 2 5
=
VSG 2 6 +
VSG 2 P,
because VSG24 and VSG25 are fixed by bias current I,.
Therefore, more of bias current I2 flows through M23. When all of I2 goes through M23,
M2N is biased with the minimum current rather than turns off as in the Class B output
stage.
The following calculation for the minimum current is done for M2N, but the same
result also applies to M2P in the opposite scenario [18].
Consider NMOS translinear loop M2 1 -M22-M23-M2N.
From (3-8), ID2N
j2N
=
'D21
+
a
'D22
1
L )21
The minimum current in M2N occurs when all I2 goes through M23.
IMIN
=
D2N=b(2T
-2II
(3-12)
IMIN
=
D2N
(2 _
F2)2bI 1
(3-13)
SinceIQ =bI
IIMIN
ID2 N
(2 - i2IQI
37
(3-14)
IMIN
0'34 31 Q
D2N
In this proposed micropower op amp, the minimum current in the output
transistors is close to 0.4 6 IQ according to the simulation result in Figure 3-7. This
difference from the calculation is caused by the fact that the transistors in the translinear
loops are in moderate inversion because of very low bias currents.
Maximum Current in Output Transistors
The maximum current is defined to be the maximum current that one of the output
transistors is capable of sourcing/sinking current while the other output transistor is
biased with the minimum current (rather than being turned off). To continue the analysis
from the minimum current section, the following absolute maximum current calculation
is performed for M2P [18], [23]. Again, the same result applies to M2N as well.
When M2N is biased at the minimum current, all of I2 flows through M23.
is pulled down to
VG2N
by M23, and it can be pulled down to be as low as
VG2P
VG2N +
at most (to allow M23 to remain in saturation). The lowest gate voltage of M2P
VDS,SAT23
is described by the following equation.
VGS21
GS22
~
GS23 +
DS,SAT23 =
G2P
(3-15)
Under this condition,
VSG2P
is the largest and M2P conducts the maximum current. The
source-gate voltage of M2P can be expressed as.
VSG2P
= VDD -
GS22 -
(VGS21 +
VGS 23 + VDSSAT23
(3-16)
Rewrite VSGand VGS in terms of
VTP 2 P +
-
F+ 2()uPC.
I
VTp,
TN,
and ID.
D2
L
2
38
DD
TN2
21
CC7
p
2
D22
p
21D23
C
23DSSAT23)
(3-17)
SinceVTN22
-VTP2P
=VTN23
2
+
/~P'
_
(-ID2P)
OX
L
21D22
21D21
VDD
VTN 21
-~jf!
pCo
±
Cx
21
Pno
D23
-
T2
p
+ic~jj
VDSSAT23J
/
C"W23
V22
PnC'
(3-18)
2(-ID2P)
P C ox jL
21D
VDD
TP2P
TN 21
~
D22
+
D23
DS,SAT 23 _
p C.
W
pC
C
(3-19)
Use the approximation,
,U pCox
I-/Pnc
3
O
2P
xDD
TP2P
TN21
DS,SAT23
D
D
(3-20)
2(-ID2P)
p,
(VDD + VTP2 P
VTN 21
VDSSAT23
2 2b-I
-
2b(2a11 )
(3-21)
39
IAX
-
pVDD+
D2P
TP2P -
TN 21
VDSSAT 23
2b1
-2
(3-22)
-~-
MAX
C r
D2P
)
2
VDD
TP2P
TN21
DS,SAT 23
\IJ
(3-23)
For the following parameter values,
VDD= 2.5V
VTp2p =
VTN21
-0.9V (typical value from [24])
= 0.8V (typical value from [24])
I, =0.2pA
a
=
5, and b = 50
and VDS,SAT23 is approximated to be 0. 1V (because it is moderately inverted).
The maximum current, IMAY, calculated from (3-23) is found to be 0.98mA while the
simulated IAx is approximately 1.1mA as shown in Figure 3-7. At this point, the
minimum bias current in M2N is down to approximately 3ptA. This result indicates that
the ratio of the maximum current to the quiescent current is 133.
As (3-23) implies, the maximum current increases as the supply voltage goes up.
The derivation also applies to the case when M2N conducts IMAY and M2P is biased with
IMIN.
Variation of Quiescent Current over Supply Voltage Range
The translinear-loop-biased topology in Figure 3-3 is a robust Class AB output
stage, but it has a minor problem. The output pair quiescent current increases as the
supply voltage increases. This variation is due to the effect of the channel-length
modulation. Consider the NMOS translinear loop, M21-M22-M23-M2N, M21 and M22
have the same VDs regardless of the supply voltages because their gate and drain are
connected together. However, VDs23 and VDS2N become larger as the supply voltage
increases. For M23, as VDS23 goes up with supply voltage but the bias current is the same,
VGS23 becomes slightly smaller. As a result, VGS2N is slightly larger at a higher supply
40
voltage because the available voltage for M23 and M2N, which is set up by M21 and
M22 is the same. Together with the increase in VDs, M2N conducts more quiescent
current at higher supply voltages. The same observation is also true for the PMOS
translinear loop. The simulation in Figure 3-4 shows as much as 47% increase in IQ
when VDD goes up from 2.5V to 6.OV.
........
................
...
.................
...
-----L
1aun
-I sun
I --- I ---- I....
............
---------
.............
----
--------
............
--- ---------------- -
.---.-
-
-.
--.... .... - - - --- .-
--. --+ I. .---
...
+ .....I --- I ---
.
...
........ A --------
- - .
---------------- ---------------- ...............
--- ---------------
3.3U
DOWN)
2.5U
ID(HP)
---1
.......
...
-.
1 ... T ---
----
...
....
.. .
.......
..
.... -------------
--------
.......... ........... ...........
------------I
t
3.5U
ID(N17)
--
-----
------------------------ ---
----
+
...
--
.........
jD
~
-
--
-I ...........
'
---
---
--- ------------
...
----
--
....
................ ....
....
...
...........
----
.....
-zinIHI-
--..
............ I .......
I
.
---
4.5U
4.6 o
I........
------ ....... I
--- ---
I
T
5.U
o
55U
6 .@U
UUcc
mouW
Evdu
-9.69654u!
wx((02) 6.0v)
-4207
9.827u
14.26152u
Fr Yam
p
vas
YWx(D(MW), 2.5V)
YaKDOW2,
2.V)
YAX(OhWb2),
6.2V)
YaX(D(h107), 25V)
jY*X(0(h
017),6.V)
1 97365u
-1.99653u
.
IDM2P
IDM2N
IDMB17
Quiescent Current in
Quiescent Current in
PMOS Transistor M2P
NMOS Transistor M2N
of Output Pair
of Output Pair
Quiescent Tail Current of
Differential Input Pair in
Biasing Transistor MB17
Figure 3-4: Quiescent Current IQ vs. Supply Voltage VDD in Translinear-Loop-Biased Output Stage
3.3 Modified Translinear-Loop-Biased Output Stage
The modified configuration shown in Figure 3-5 mitigates the variation in the
quiescent current over the supply voltage change. It is the topology used in the proposed
micropower op amp. This modified biasing scheme alleviates the change in IQ at a small
cost of extra bias currents.
The variation in IQ is reduced by allowing VDs22 and VsD2S to increase with the
supply voltage [23]. VGS22 and VSG2S then become slightly lower as the supply voltage
increases, thereby leaving less voltage available for M23 and M2N, and M25 and M2P,
41
respectively. This effect counters the increase in VDs23 and VSD26, and thus keeps
VGS2N
and VSG2P more constant over the supply voltage change. The simulation result in Figure
3-6 shows the variation in IQ is down to only 20% with the supply voltage change from
2.5V to 6.OV.
I
VINA
VDD
-r
U
I1
I
12
M24
3/1
2al
M25
3/1
.
.
23
M2P
3/1
b
.
vouT
M2 i
M2N
1/1
b
VNB
M22
1/1
M21
1/1
I,
12=
I
II
2a1
Figure 3-5: Modified Translinear-Loop-Biased Class AB Output Stage
42
I alft
I
V
I
........ .............
............
-
uAF
....
.... ...
. . .. . . . .. . . - - - - . . . . . .
.. . . . . . . . . . . . . .
Fi
Id:
Pr
I E
-- - - - - . ... . . . . .---- - - - - -
.. .. .. .. ..
... . ..
... . . . . . . . .... . . .L.
. -..-..
.... .
-- ------ --
----- ---- -
-----
-I - ---
........
M......
YIVX(ViwIP), 25'.')&
X(VoAw1 zBV)
.92527u
jX(1D"A2N), 25V.)
V~X(DO2(h120.V 6.M5S
832703U
......
.......
~0-IDMN
IDMP
Quiescent Current in NMOS Transistor M2N of
Output Pair
Quiescent Current in PMOS Transistor M2P of
Output Pair
Figure 3-6: Quiescent Current IQ vs. Supply Voltage VDD in Modified Translinear-Loop-Biased
Output Stage
Ii
(
~
~
ig29.9m..
!!I
...........
F
FH
D
f
I
...2 ...
....... EE
............................ ....
fNi
... ...
....
2.
2
.
,'NTn
-----...........
ils[igptaA11i 291A
I
I la[sz
----- ----L---
--------PT
M
2P
n.....
A
f11I!ufilr
~~~~~
A
VgX........
Vf(NQI2)Om)50
I~
m
m
-
.......
.
j.
.- !..::
........
....... .... .....
DI~~~~~~~~~~
I~A
----- --
V~X(E2(ktO-
...............
~u
..
rilM
T~TFT
39a271lff6f91111
....
....
......
73u
M.A
3822~
~..
E1lm)_________________________________________
~~~ ~~~ ~ ~~~~~~~~~~~~
...
...
0
]IDM2P
Current in PMOS Transistor M2P
of Output Pair
Figure 3-7: Currents in Output Pair, 'Dm2p and IDM2N vs. Load Current
Translinear-Loop-Biased Output Stage
43
D2
Current in NMQS Transistor M2N
of Output Pair
ILOAD
in Modified
~~
.
-
-
-
44
Chapter 4 Bias Cell
This chapter demonstrates the design of the bias cell used in the proposed op amp.
It explains how the reference current and reference voltages are generated and passed on
to the op amp. The need and the implementation of the start-up circuit in the bias cell are
also explained.
4.1 Reference Current in Bias Core
The bias cell core is implemented by the bipolar Widlar current source in Figure
4-1 [25], [26]. Transistor QB2's emitter area is N times as large as that of transistor QB1.
In this design, N is chosen to be 5, which is the minimum of emitter area ratio normally
used. The reference current is generated by the base emitter voltage difference between
QB 1 and QB2 across resistor RB. Note that transistors QB 1 is in the forward active
region because QB 1 is diode-connected. At the minimum supply voltage of 2.5V, QB2 is
also in the forward active region because VCEB2
=
VDD - VSGMB2 - IREFRB,
than VCE,SAT if the VSGMB2 and the drop across RB are not too high.
45
which is greater
VpD
MBI
10/40
MB2
10/40
MB3
10/1
MB4
10/1
I
QB2
Nx
Switch in
Ix
Start-up
IREF
Circuit
RB
Figure 4-1: Bias Core Generating Reference Current 1251, 1261
The reference current, IREF, can be determined by starting from the KVL equation
of the QB 1 -QB2-RB loop, as presented in [26].
VBE 1
REF RB0
PF
-VBE2
(4-1)
Find VBE in terms Of IC.
VBE
Since Ic = Is
I + VCEL)e
T
and assume
VCE
VA
[27]
VA
(4-2)
Ic
= Ise
VT,
where
VT=
26mV at 300K
(4-3)
Therefore, VBE
= VT
In
(IS
(4-4)
VT
in Ic - VT in
ISI
E
IS2
F
)6F
REFRB
=0
46
(4-5)
Since
Ih
1,
1
JBF
(4-6)
V. ln
--
1 V In
Is1
REF
IREFRB
=0
Is2
(4-7)
VTIn
NI
-IREFRB
0
IREF
(4-8)
IREF=
T
InN
RB
(4-9)
This result implies the bias cell's ability to provide a constant reference current
under process variation. From (4-9), the mismatch in the emitter area ratio AN from
process shifts is reduced to ln(AN). Hence, the remaining source for error is the resistor
RBvalue (i 25% maximum) which can be reduced by adding a trimming resistor [25].
The current mirror transistors are sized to have the width of I0pim and the length of 40tm
so that they have a reasonable area and the mismatch is minimal.
47
4.2 Start-Up Circuit
Start-up Circuit
VDD
10
MS3 MS6
1/100 10/40
MS2
1/100
LI MBI
10/40
MB3
MB 2
10/4 0
I
H-
4
10/1
Isu
I
MS7
2/20
MS1 L1
1/100
MS5
2/10
MS4
2/10
IR EF
OBI
QB 2
ix
5x
RB
i
~-~
Figure 4-2: Bias Core with Start-up Circuit
The bias core has two stable points: one with Ic, = Ic2 = 0, the other with Ic,
=
Ic2 = IREF. Without the start-up circuit, VB of transistors QB I and QB2 could be at GND,
and thus not generating the reference current. For the bias core to generate a reference
current, the base voltage of QB 1 and QB2 must be initially pulled up from the ground by
a start-up circuit. A compact start-up circuit used in this op amp is shown in Figure 4-2
[25]. MSI and MS2 are sized to be narrow and long to minimize the start-up current, Isu.
The first two devices in the start-up circuit becoming active upon the power up
are MS 1 and MS2. The supply voltage across their gate-source voltages forces them to
turn on, and thereby, MSI and MS2 start to conduct start-up current Isu. The start-up
current is then mirrored to MS3-MS4, and MS5 respectively. At this moment, MS5 tries
to sink current from MS6, but MS6 cannot source any current because the bias core has
not been turned on. Therefore, the gate of MS7 is pulled to ground, causing MS7 to pull
the bases of QB I and QB2 up from ground and the bias core is in operation. Now, MS6
48
can source enough current to MS5 and turn MS7 off by pulling its gate up. Note that
MS6 is sized to be 10 times as wide as MB1 and MB2 so that MS7 can be easily turned
off as soon as the bias core starts to supply IREF. The final current in MS6 is limited by
MS5.
The start-up current, Isu, can be estimated by the following. Upon the power up,
MS1 and MS2 see the supply voltage across their gate-source voltages according to the
relation.
VSGMSI
SGMS2
+
DD
-
(4-10)
To simplify the calculation, the body effect on VTP increase of MS1 is ignored, and the
following approximation is made.
SGMS2
VSGMS I
(4-11)
And thus,
DD
VSGMS2
(4-12)
MS2 is in saturation because it is diode-connected. The start-up current can be
approximated by
ISU =
-ID
1
2
o
+ VTPMS2 )2
(WSGMS2
(L
(4-13)
ISu =D
20
W
L
( S)GMS 2 + VTP)
(4-14)
ISU
'D
, 2
LVTPO
)2
(4-15)
This approximation is an overestimate of Isu because in reality
body effect.
49
VsGMSJ> VSGMS2
due to the
4.3 Reference Voltages Bias Circuit
Besides the reference current generated by the bias cell, the op amp needs two
reference voltages: one is the reference voltage for PMOS cascode transistors, the other is
that for NMOS cascode transistors.
The circuit in Figure 4-3 shows how to set up the two reference voltages.
Reference Voltages Bias
Circuit
4
MB1
10/40
MB6
10/40
MB5
MB7
10/1
I
'4
K
MB8
10/40
MB9
10/40
MB4
10/1
MB10
10/1
MB2
I leiMB2
9 ff
2
MB3
10/1
VDD
*
VPCASCODEB
I
IREF
I
NCASCODEB
JV
1
1
V
I
Start-up
Circuit
QB3
,
OBI
OBx I
lx
I
QB 2
5x
O
I'REF
RB
-
~
_________________ i ~
Figure 4-3: Reference Voltages Set Up in Bias Cell
MB5 sets up the reference voltage for PMOS cascode transistors, and MB8 sets up the
reference voltage for NMOS cascade transistors. The voltage at the gate of MB8,
VNCASCODEB, can be determined as follows.
Transistor MB6 mirrors the reference current, IREF, to MB8. Since MB8 is diodeconnected, it operates in the saturation region and
VNCASCODEB
= VGSMB8
_
+ VTN0
(4-16)
50
Similarly,
VPCASCODEB
=VDD -VSGMB
D
=VDD
5
VTPOI
(4-17)
In the design,
VNCASCODEB
and
VPCASCODEB
are set up such that all the inner
transistors of current mirrors (e.g. transistors MBl and MB2 of current mirror MBlMB2-MB3-MB4, for example) operate in the saturation region by having VDS > 0.4V.
Together with IREF, VPCASCODEB, and VNCASCODEB, are passed on to the op amp.
In an IC, especially large ones, the supply voltage line and common ground line
vary slightly from one corner to another. Therefore, reference current IREFis fed to the op
amp as a current instead of the gate voltage of MB2 to ensure the accuracy of bias
currents in the op amp. In contrast, the cascode transistors' voltages,
VNCASCODEB,
VPCASCODEB
and
are supplied to the op amp as voltages because their deviation from the
intended value has little effect on the biasing in the op amp.
The complete bias cell is shown in Figure 4-4. The value of reference current
varies as little as 3.1nA when changing from the supply voltage of 2.5V to 6.OV. Figure
4-5 show the values of
voltage
IREF, Isu, VNCASCODEB,
VDD.
51
and
VPCASCODEP
as a function of supply
D=2.5V
(03E-09
STARTUPPI
iD=-40 009
D4
vCC
VCC
1/100 L
L
1
0.241uA
4.17nA
403nA
0235uA
10=2 47I
0=b
47
17E-09
p2-I
Mai
10/40
0L
ID-I
Mij
1141 E-07 ID= 35E-07
D=
0.241uA
0.241uA
0.241uA
,CC
100
Reference Current to Op Anp
IREF Generator
Bbas Voltages Setter
Start-Up Circuit
MlnA@\
D=-241 -07
c
I
I~
I
41E-07
13
"M/6
10Q4
L
I
vE9
10/40
>-2 41 -07
-C-2.411 0
L
0
I O
NEd
_~
a
0X
CL
vzCc
I
-N4CASC0
03E-
I-fl-
22100
ID
STARTUPR
C-NCO
1/100 L
II
41E-7
OwtL
06I3 II
I
I
GOND
.03E-0-4
ID=4 17E 09
R6
168 ,
Figure 4-4: Schematic of Bias Cell
52
EB
1.6U1
fj - - -I
.1 - - - - - - - - - - - - r
I- -- T
- --- -- -- -
-. 1- - - - - - - - - - - -
I - -- J - -- -- -- - --- -L
I -- -
- --- - -- -L
I - -- J
-- - --- -- -- -- -
-- -- -- --L
v - -- -
- -- -
-- --
I - --
- -- -
-- -
Top
.1 - - - - - - - - -- - - - - - -
T
--G-
- -- - --- -I -- - -- - --- -- -- z- -- -- -- --
- - - ---- - - - - - - - - - -
. JIU -
- - -- - --- ----- -- - --- -- -- -- -- -- -- --
---- -- -- - -- -
SEL>> ---- r ----
-n ----- -- - --- -- -- -T
- -- -- -- -- -- -- -- -- -- -- --
--- ----- -- -- -
--- -- -- -- -- -- -- -- -
- -- - --- -- -- -- -- n - -- I - -- - --- -- -- -
I -- -- -- --- - -- -- --
- -- -- -- -- -- -- --- -- - --- -- -- T
I-
VAICASCODEB
--- -- - --- -- - -- -- -- t3z - --- -- -- -- -- --------- - --- -
Reference
Voltage for
NMOS CascDde
Transistors
- -- - --- -- -- -- -- -- - -- - -- -- -- - --- -r -- -- -- -
I - - -- -- -- -- -- -- --
1.2Un U(MCASCODEB) * U6G-UCC)-U(PCASCODEB)
16 AAfth
I ---------
VDO
I -- - - -- - - --
--
-- - -- - I --- - -- - -- - -- -- -- -I i - - -
L ---I---,
-- -
-- -
-- -
-- -
---------
-- --------------------
- -- - --- -- --- -- -- -
- - - - -- -- -- --
I - --
-
a.. .. . .. . .. . . . . -a-
- - - ft---*
------------
0-
.
..
...
....
0-
VPCASCODEB
Reference
Voltage for
PMOS Cascode
Transistors
-----------------
----------r
*4 ---4-
1
1
2. SU
3. ou
3.511
c ID(MMBII) * -ID(MSTARTUPREF-MS2)
4. OU
4. SU
S. OU
S.SU
6. IOU
UUCC
EvAm**
W
F7
FF
M"Swrenmt
VAM
--0-
N I - Uremerit ROSURS
I
.............
.............. ...
240.86847n'
jYptX(DQMM1 1). 2.5V)
I
IDMB11
Reference
Current of the Op
...................................
-.......
....
Amp
.........
....
............
...................................................
...........
...
Yea(D" Mi 1), 6.0v)
3.92219n
Ya0WD(MSTARTUPREFMS2). FSV) . ..... .02927n
...
----YadX(DM TARTUPREF MS2), S.OV)
-329.02111
nI
YatX(VMASCODEB), 2.M
....
....
t ...
YdX(V(NCASCODEB), 6.OV)
YaiW($0
1.46035
-YCQ-VKASCODMEB), 2
YaIX(V($0 VCC)-V(PCASCODEB). 6 ...
.............
...
Pr
Bottom
...................
...........
.................
.......................
.IM2
.......
..............
.............
.................................. .............................
Current in
Transistor MS2 in
Start-UD Circuit
hmummmmmmmi
Figure 4-5:
IREF9 ISU9 VNCASCODER,
53
and
VPCASCODEB VS- VDD
54
Chapter 5 Frequency Compensation
The previous chapters have explained the design process of the op amp and the
bias cell. The remaining part to complete the micropower op amp design is the frequency
compensation. This chapter briefly discusses two frequency compensation schemes. The
most popular compensation scheme, simple Miller compensation, is considered first.
Next, cascode compensation is explored as a potential scheme in extending the gain
bandwidth product but with a defect of causing peaking in the frequency response. The
combination of the previous two compensation schemes is then presented as the solution
which offers moderate improvement in gain bandwidth and eliminates the peaking
problem in the frequency response of the op amp.
5.1 Proposed Micropower Op Amp with Simple Miller
Compensation (SMC)
The most common scheme to compensate two-stage op amps is Simple Miller
Compensation (SMC) [28], [29]. The implementation is achieved by feeding the output
signal back to the input of the output pair transistors through capacitors Ccl and Cc2 as
shown in Figure 5-1. A disadvantage of SMC is that the right half plane zero severely
compromises the phase margin. This problem can be alleviated by inserting nulling
resistors Rc, and Rc2 in series with the existing compensation capacitors to reduce the
feedforward signal. However, there is limitation on the values of the nulling resistors.
As their values increase, the left half plane zero moves toward lower frequencies.
Although this movement of the left half plane zero helps increase the phase margin of the
op amp, it also reduces the gain margin at the same time. In the proposed op amp with
simple Miller compensation, the gain margin is designed to be at least 10dB and this
requirement is the limit on the nulling resistors size. The complete micropower op amp
with Simple Miller Compensation (SMC) is illustrated in
55
Figure 5-2. Figure 5-3 and Figure 5-4 show its frequency response and transient
response respectively. With supply current of 20pA, the proposed op amp with SMC has
a unity gain frequency of 360kHz with 61.50 phase margin at lOOpF load.
56
VDD= 2.5V
-I
M15
10/1
I
Mil
50/10
4
VM =0.1
2
M12
50/10
VB2
M18
40/2
M17
40/2
4
F-=
M16
S10/15
2
A
10-j M2P
3/1
I
I
50
Cci
VOUT
Class AB
Contro
CC2
M13
14
M14
20/2
VBI
T
M2N
1/1
50
EIDq]
I2
13
Figure 5-1: Simplified Schematic of Proposed Micropower Op Amp with Simple Miller Compensation (SMC)
57
_
I CLL
RL
0241uA
241ATuA
2.41uA
2A1 A
T
IC2PF1
7
JT.
I N, 4
11..m1
PmpRRoRa-;
L 10,40
1
I
P~u7
L
3'10
MW
L
A 1K
E
CM
1 E-W
c L-9 I
2C
0.241uA
0.242uA
0241uA
0.241uA
10.3uA(@VSUFb2.N)
.I~
7
IL M821
L, 10140
M624
10140
L
10
t$W
40&!2
L
1/1l
'II
C
1*
iC
fMP
t
-UT
L
!I 3
J'
S/2
CZtF
_
G
r
M13
MB12
L
NCASCCOE ,311
L
11 .
M
L
M814
311
p
N2
jI
Nril VL
GND
LM13
r-~3/0
I.
3/1O
Mwz
'U'IC3
2PF
|I
I
V1l~
- -I7E
MEto
I
1422
L
MNC3
3/4I
C-4'
T
Figure 5-2: Schematic of Proposed Micropower Op Amp with Simple Miller Compensation (SMC)
58
Ed-
20-
.-.
-
-
---
--.............
-
--
""M".""
n
S
e
1.4
...
_9d
(
d
-
.......-
4w
.
d
U
.
.
,,..
135d.
.-.
.. ..
....
.,,,,
.
r
-18Ed-
-
- - -
----
-
-- - --
-
-- -
--
--
-
--
-.
-225d-
-36EdM
1. 6z
I166Hz
1EInHz
, P(U(OUT)/(U(IW6)-U(16M)))
".
1. MHz 1 Hz
16Hz
DB(U(OUT)/(U(INP)-U(INN)))
Frequency
1iz
+
Mee
"Sswes
Evftd*
IHHz
1.@NHz
16XHz
1
6Iz
Ros
s
Value
P rsawD8r(V(OUT)KV(")-V(l
RM8MW*(De UT)KV( .)-V
" "
"
". ."
......
1..
-315d-
1.ftHz
'
. . .." . .' " . . ""
.
' .'"
a.". .. '"
. .
--. -
.
..
..
3--.274161.47403
-A
Gain
Phase
Figure 5-3: Frequency Response with CL=lOOpF and RL=100kfl of Proposed Micropower Op Amp
with Simple Miller Compensation (SMC)
T 79MMU
a u
____
_________-________
2Ou
SI1I
jC=O1pF
-
.
__
___1
-
.
.RL=
00kdhm
----------------------~.
IL=kmA
..
1----+---- +-----------
- - -- - ----------------- -----
--
------
--
--_I _ I I._ _"I - -
--
- - ------ - - - -
649MUM..newe3.U*
Evalu*.e
I
'
Meiwurnwet
ISitbinaTnmu
XRnaet(v
flT0m1
Value
I
5u
--
A1%L 141
VINP
I
VOUT
Figure 5-4: Small-Signal Transient Response with CL=100pF and RL=100k.Q of Proposed
Micropower Op Amp with Simple Miller Compensation (SMC)
59
V
5.2 Cascode Compensation
The cascode compensation eliminates the feedforward signal by putting a current
buffer in the compensation path as shown in Figure 5-5 [30]. This technique was first
presented by Ahuja in [30]. It was also analyzed for Class A folded-cascode op amps by
Ribner and Copeland in [31], and for fully differential op amps by Hurst et al. in [32].
In the proposed micropower op amp, two current buffers already exist in the
design. One is the cascode transistor pair of the input pair. The other is the cascode
transistor pair in the wide-swing current mirror. Therefore, there is no need to establish
separate current buffers, and the compensation capacitors Cc3 and Cc4 can be directly
connected to the embedded cascode transistors at node E and D respectively as depicted
in Figure 5-6. The results show a significant improvement in the speed. The unity gain
frequency extends to 991kHz as shown in Figure 5-7 when the output stage is at rest with
the same supply current and loading condition. However, when the transconductance of
the output stage transistors changes, there is peaking in the frequency response as shown
in Figure 5-8. This defect in the frequency response greatly reduces the gain margin and
causes oscillatory behavior in the small-signal transient response such as the one in
Figure 5-9. In [33] and [34], Langen, Hogervorst, and Huijsing describe this problem of
using only cascode compensation in Class AB op amps and suggest the need of keeping
simple Miller compensation capacitors Cc, and Cc2 to prevent the peaking.
60
-I
M15
2
II
VINp
Mil
M12
50/10
50/10
VB2
M16
10/15
2
10/15-
-H
M17
40/2
M18
Jr
F-
40/2
VB3
-3
VINM
Cci
I
c
M2P
3/1
50
VOUT
-I
M13
4T
M14
20/2
VBIE=
@
13
12
Figure 5-5: Class A Op Amp with Cascode Compensation (Adapted from 1301)
61
4
CL
RL
VDD= 2.5V
M15
10/1
2
Ii
Mil
50/10
4
vMp =0_
M12
50/10
VB2
M16
10/15
E
M18
417
40/2
4/2t
4
2
M2P
-=VINM
I I
Class AB
Control
50
Cc3
-HF-4
S
M13
M14
20/2
VB1-
VOUT
M2N
5/1
50
I
I2
13
Figure 5-6: Simplified Schematic of Proposed Micropower Op Amp with Embedded Cascode Compensation (ECC) Only
62
CL
-G
Gd-
.
--
200
a
d
rH
JM
0X0 5~
...
.
... .
.............
3-45d15
-9§d-
.+--
-
-
d
"
-195d-
-
-- - -
"..-.-.---
"L..
-
-.--.-.--.--.--....-.-.....
-189d-
-- -ul----111
1 OIL
-225d-
-276d-
S>
-se'j
-.
>
-315d-
IJ
-.
--
- - --
- -v-;-- I
- -.-I -w - - - -, 4---- - - -- ;- - -L
- -.
-.
-Said-
S
;
- -- -
-1- 4
- -.1jr11.1
I1.
131Hz
15Hz
o DB(U(OUT)/(U(IIW)-U(IH)))
P(U(DUT)/(U(INP)-U(INH)))
J
1.MHz
BZ
1
16Hz
1.0Iz
1S8fHz
1@Hz
1.U80z
-
-
- - -r - .
-
U-.I -
I0 96U
I vH3z
INN
-
Frequency
k ocros s(.:.............
p zeocros(D(V~oTAVm).Vt- 901 43489k
Fh.s.M.rgi(D(V(OUT)(V(9f)-V0L8859
14.93053
Gaindwgin(P(V(OUT)(V(WF)-V(?N)
-4-
| -U-
Gain
Phase
of Proposed Micropower Op Amp
RL=100kL
and
CL=100pF
with
Response
Frequency
5-7:
Figure
with Embedded Cascode Compensation (ECC) Only
I
.
ad,
OF-
......
.
.......... ...
....
n
-96dd
9
-135d-
N++ ;4; -++tne
i118-- +11-+
1
--.-...
5t-0
----
4~~~~4'm
t i
--
-- +H4104
--
-+H;ri--
- I ... ---- ; -
-+ +v "
--
--
--
-18d-
-276d-
so H-+--
'
-H!---90--
t
4
-r
- f.-
--
-L41.
-+ f~i.
++Rf
4-8-0-+-- +Htt
~
-+
3 -tv~ii-H i--+
H-MH -++H81-+ttix
-HNH-
-+
HE
H t
~+-i V4 .. ~~-8 K -~,.L
-,-.
+
--
-22Sd-
---
-..-
-I
+ H~t
-- +-"IwNN-+
U
-W-
-t
-3i5d-368d1.(Hz
1Hz
[)
16:Hz 1 6Hz
1.6Hz
lSZ Iz
- x
P(U(uUT)/(U(IHP)-U(J16))) M
1@HMz
199H2
4
Masemnt2
Er
1.MHz
15Hz
15Hz
1. MHz
, DO(U(OUT)/(U(iI )-U(IHH)))
Frequency
E ZvrCr. s(DWV( UT ) V(N4
PhIP WMIrg*(D8( V(UT)((P)V(L
_7 1n rgn(P(V( 4882
k( ) V()- M))), 1)
I
_
904.1113k
88 9013i
527787
85.301_
13 77e
6906271
10.28520
-0.5
1.0
-0-
Symbol
-
99347485k
.
J
IL
93.40771k
-94674
0.0
98 43966
241789
-72093337m
98398
-498393hn!
-
10812
0.5
1.0
Phase
Phase
-V-
-
Phase
Phase
-+-
-4 -
Gain
Gain
Phase
- Gain
-
Gain
-
Gain
1 0
Figure 5-8: Frequency Response with CL=10pF and RL=100kfl * IL- * , -0.5, 0.0, 0.5, 1.OmA of
(ECC) Only
Compensation
Proposed Micropower Op Amp with Embedded Cascode
63
719m1U -
5
,L
.
CL l
f-_-
-------...
---------
----- --------
I,
-
pF
~~
RL 10qkoh
~----
--------
:
.
-----.--
-----
- -
-- ---
-
----
- ---
--
------
-
--
640R
~ ------~M
~~ -- ------------
-- ---- .
------
.
a
- h
----- ----g~
lSdkmr
...... .
f~ cA l
XRenaeN(OUT).
----
0V.1,N
SU
I--
I--
-- 1 -----
----
-... .. . . . . .. . . . --- - - - - - - -- - - - -
V1-
--- I
---- ---
- -- -
.. . . .. - -- - -
- - - -- - - -- - -
1 .1T2433u!
VINP
IVOUT
Figure 5-9: Small-Signal Transient Response with CL=100pF, RL=100kfl, and IL*0.5mA of Proposed
Micropower Op Amp with Embedded Cascode Compensation (ECC) Only
5.3 Proposed Micropower Op Amp with Hybrid
Asymmetric Embedded Cascode Compensation
(HAECC)
In order to exploit the benefit of the cascode compensation, the proposed op amp
employs the hybrid of the simple Miller compensation and the cascode compensation
[33], [34]. The hybrid compensation maintains the simple Miller compensation path to
tame the frequency response when the current in the output stage change as shown in
Figure 5-10. The detailed schematic of the proposed op amp with this compensation
scheme is in Figure 5-11. The simulation results show an improved unity gain frequency
of 589kHz with the same supply current of 20pA and load condition of I OOpF as depicted
in Figure 5-12. The op amp now exhibits neither the peaking behavior in its frequency
response nor the oscillatory transient response when the current in the output pair change
as shown in Figure 5-13 and Figure 5-14 respectively
64
VDD=
Mll
50/10
4
-I
M15
10/1
2
IF "
M12
50/10
VB2
4H
2.5V
M16
10/15
E
2
M18
140/2
M17
40/2
-
VINP =01VfNM
CO
CC4
VB I
dw*
1
M14
20/2
WEEKI
1I12
7
Cc]
VOUT
Class AB
Control
M13
M2P
I C: 3/1
50
M2N
C
50
13
Figure 5-10: Simplified Schematic of Proposed Op Amp with Hybrid Asymmetric Embedded Cascode Compensation (HAECC)
65
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340
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5
1
Cs~
Figure 5-11: Schematic of Proposed Micropower Op Amp with Hybrid Asymmetric Embedded Cascode Compensation (HAECC)
66
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-
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--
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a
n
-
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------
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aur(P(V(OUT)Y(V()-V(64)...
s927467k
61.026
12.70153
L
____
______
Gain
Phase
Figure 5-12: Frequency Response with CL=100pF and RL=100Lk of Proposed Micropower up Amp
with Hybrid Asymmetric Embedded Cascode Compensation (HAECC
eu,
P
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zee-wy.
G
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oment
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Pedk((V(OUT)(V(?P)-V(P4))), 1)
(mA)
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304265
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Phase
Phase
Gain
Gain
Gain
0.0
-0.5
-1.0
--
1.11z
155KHz
KHz 1KHz
1.
I D(U(UT)/(U(Ik)-U(1IHI)))
Frequency
1Nz
5 4.94673k
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.,
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10
Figure 5-13: Frequency Response with CL=IOpF and RL=lOOkQ @ IL=- . 1 -0.5, 0.0,0.5, 1.mA of
Proposed Micropower Op Amp with Hybrid Asymmetric Embedded Cascode Compensation
(HAECC)
67
o
1
I
70 IhIA
HAE x
...........
....
......
II
=
.........................
I
.
I
CL=kOOpt
------------
...........
68*MU---_----_----
---------- ----- -
---------
----------- ----- - --.......... ----- - ---
------------------------
...........
------
--------- _----
......I ------I -----------
----------------------------------- ...... ------------------
-----
...... I ......I ----------------
I
I
I
----------- ------ ...................
---
640MU.....
------------
----------
..............................
-----------
........
-----------: ------ ------ I -------------- -----
----
I ----- r ----- I ----------- ......
j.............
............ ........... I----- I ------
I ..... I ........
A
688MU-
................. .................................. ...... ..................
....................... ...........
........... .............................
. ............................. ----------------------------------- ......
560RU
U(IMP)
bdud*
ISdWWTkm
W
ISUS
I Ws
5us
s
I
-----------: ------
-------
...... ....................
20us
U(OUT)
Time
emerd
XRwxwvroun. 5.1. su..
Vakle
1.4495ru.
1
VOUT
VINP
-0-
Figure 5-14: Small-Signal Transient Response with CL=IOOpF, RL=100kfl, and IL=0.5mA of
Proposed Micropower Op Amp with Hybrid Asymmetric Embedded Cascode Compensation
(HAECC)
68
25us
Chapter 6 Final Results and Conclusion
Final Results
Two micropower op amp designs have proved to satisfy the project specifications
set forth in Chapter 1. They essentially have the same architecture, but employ different
frequency compensation schemes. The first one (Figure A-I in Appendix A) uses Simple
Miller Compensation (SMC). The other one (Figure D-1 in Appendix D) is compensated
by a combination of simple Miller compensation and cascode compensation, or called
Hybrid Asymmetric Embedded Cascode Compensation (HAECC) in this thesis. The
detailed simulation results of all op amp designs are in the appendices. Table 6-1
summarizes the characteristics of the proposed micropower op amp with simple Miller
Compensation (SMC). It has a unity gain frequency of 360kHz with 61.5' phase margin
when loaded with 1 OOpF. The proposed micropower op amp with Hybrid Asymmetric
Embedded Cascode Compensation (HAECC) has a higher unity gain frequency of
589kHz at the same loading and power dissipation condition. Table 6-2 includes the
detailed simulated characteristics of the design with HAECC.
Table 6-1: Characteristics of 20pA Micropower Op Amp with Simple Miller Compensation (SMC)
Simulation results are at 25 0 C. VDD = 2.5V and Vss = OV.
Primary Characteristics
Value
Specifed
Condition
Sym bol
Parameter
GBW 5
Gain Bandwidth Product
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
CL = IOOpF
RL = I 00kQ
> 100
is
Supply Current
No Load
<21
VINCM6
Input Common-Mode Range
-
> VDD -1
Specified
CL = I 00pF
RL = 100k
_
ted
.6
> 0.3
(0m=61.5)
.25V
5 Gain bandwidth product per supply current GBW/ Is= 18MHz/mA @ CL = I OOpF.
6 Verified by CMRR simulation in Figure A-4.
69
Si___
Unit
Simulated
MHz
122
dB
1935
pA
1.3
V
and must include
and includes
negative supply
negative supply
voltage
voltage
vos7
VOUT
(Untrimmed) Input Offset Voltage
VINCM =
0.65V
I.OmA
<5
VDD -
0.3V
4.18
mV
2.
V
VOUTH
High Output Voltage
ISOURCE =
VOUTL
Low Output Voltage
ISINK =I.OmA
< Vss + 0.3V
0.19
V
>
IsOURCE8
Output Source Current
CL=
OpF
RL = 100k1
> 1.0
1.55
mA
'SINK
Output Sink Current
CL=IOpF
RL= 100k
> 1.0
1.04
mA
Sim.la.ed
Unit
Secondary Characteristics
Value
Spe.if.e
Condition
Symbol
Parameter
SR
Positive Going Slew Rate
SR-
Negative Going Slew Rate
CMRR
Common Mode Rejection Ratio
@ DC
> 60
Positive Power Supply Rejection
@ DC
@ C>6084.5
>
60
@ DC
@ C>60994
>
60
Av= 1V/V, 1V
PSRR+
.
Simulated
Specified
Step
Av= lV/V,
IV
> 0.15
0.223
V/ps
< -0.15
-0.236
V/ps
Step
144
dB
dB
Ratio
PSRR-
Negative Power Supply Rejection
Ratio
ts
0.1% Settling Time
Av= IV/V, 1V
Step
dB
5.29
<10
ps
Table 6-2: Characteristics of 20pA Micropower Op Amp with Hybrid Asymmetric Embedded
Cascode Compensation (HAECC)
0
Simulation results are at 25 C. VDD = 2.5V and Vss = OV.
Primary Characteristics
Value
Symbol
Parameter
GBW 9
9CLBandwidth Product
SiGain
Unit
Condition
Specified
= IOOpF
= 0OpF
RL =
100kO
>0.3
>
Simulated
0.5
^ 0.589
MHz
o26r
7 Conservative estimate from calculation.
8 Maximum output source current is measured when the other transistor in the output pair starts to turn off,
i.e. its current goes down to as low as lIpA.
9 Gain bandwidth product per supply current GBW/ Is= 29.5MHz/mA
70
@ CL = IOOpF.
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
CL = IOOpF
RL = 100kf1
> 100
122
dB
is
Supply Current
No Load
<21
19.95
pA
.3
> VDD - 1.25V
VINCM1
0
Input Common-Mode Range
-
negative supply
negative supply
voltage
voltage
Vos
(Untrimmed) Input Offset Voltage
VINCM
=
0.65V
VOUTH
High Output Voltage
ISOURCE =
VOUTL
Low Output Voltage
'SINK =
1
ISOURCE]2
Output Source Current
ISINK
Output Sink Current
I.OmA
1.OmA
CL = lO0pF
RL= IO00W
CL = IOOpF
RL =
100kW
V
4.17
mV
0.3V
234
V
<Vss + 0.3V
0.19
V
> 1.0
1.$5
mA
> 1.0
1.03
mA
<5
> VDD -
Secondary Characteristics
Sym bol
Parameter
SR+
Positive Going Slew Rate
SR-
Negative Going Slew Rate
CMRR
Common Mode Rejection Ratio
C ondition
Av= IV/V, IV
Positive Power Supply Rejection
PSRR+@DC>6Ratio
PSRR-
Negative Power Supply Rejection
fed
Specified
Siu_
_
ted
U nit
Simulated
> 0.15
0.315
V/ps
< -0.15
-0.342
V/ps
Step
Av= 1V/V, IV
Step
@ DC
> 60
144
dB
@ DC
>60
"6
4
d
d
@ DC
> 60
".5
dB
<10
3.0
Ms
Ratio
Av= 1V/V, IV
t,
Value
Spec_
0.1% Settling Time
Step
10 Verified by CMRR simulation in Figure D-4.
"Conservative estimate from calculation.
12 Maximum output source current is measured when the other transistor in the output pair starts to turn off,
i.e. its current goes down to as low as IpA.
71
Discussion
The two proposed micropower op amp designs have a higher unity gain frequency
and
than the two commercial low-power op amp ICs previously mentioned, MAX9914
MIC861, when compared at approximately the same supply current and loading
when
condition. The design with HAECC offers a gain bandwidth product of 1.87MHz
compensated to have phase margin of 45' at 15pF load as shown in Figure 6-1. Table
6-3 summarizes the frequency domain performances of the proposed design and
MAX9914.
In addition, when the proposed design is biased at 5VA, the one with HAECC
at
compensation gives a gain bandwidth product of 375kHz with the phase margin of 45'
presents
5OpF as depicted in Figure 6-2, which is higher than that of MIC861. Table 6-4
the overview of the comparison between the proposed designs and MIC861.
d-
P
h
a
G
a
-
-
,,xi
=
~
-
-
-,-~-.
rrne
~rT
~q -i-m
rrm~ -w-rnr
~T~TT
rmn
:icii
I'
"S -14 Ik
r-ik
_ .5d-
rnrr
MIX
n
S
-91dd
- -9+~~14
d
I
-- 1--T
11te
-
---
- - -1
-------
e
-hi8d-225d-
-27ld-
-1i
s ..
-
-315d-36Id I.InHz
1.@Hz
IisMHz
1mHz
P(U(OUT)/(U(IMP)-U(IHt)))
1Oz
+
[2]
16Hz
Pr
PhsMr(DB(V(OUTW((P)-V(I
IKHz
1IOUHz
1
(Mz
18MZ
188Mz
Frequency
RS
RRSOueien
ikaluat000*e1
ZeroCross(D1(VOUT(V(N)-V(N .
1.3KHz
9(U(OUT)/(U(IW)-U(1H)))
1
..
54.
.g
5-
44so
Gain
Phase
Amp with HAECC Compensated Down to
Op
Figure 6-1: Frequency Response of 20pA Micropower
with MAX9914
Compare
to
Load
15pF
at
Have Om = 450
72
20pA Op Amp [Om=45 @ CL=15pF, vs
MAX99141
Frequency Response
CL
=
Off, RL
=
CL
lOk
=
5pF, R = 1OOki
GBW (MHz)
Om (*)
GBW (M]Hz)
Om (0)
Simple Miller Compensation
SMC
1.79
72
IAS
47
Hybrid Explicit Cascode Compensation
Hybrid Asymmetric Embedded
Cascode Compensation
HECC
1.63
68
1.56
46
HAECC
1.91
63
1.37
45
45
0
-_
-.
MAX9914131
Op
Amps
Micropower
20PA
the
Proposed
between
Frequency
Gain
Unity
Table 6-3: Comparison of
and MAX9914
P
h
a
G
a
j5
,.. . ..
...
,.,.
,. ..,,,,..
., , ..
,, , ,,,... .,, , , , .,, , . ,.. ,. .. .
,
i
n
5
280-
159
d
d
s.,, . .
-135d-
. . . ,..
., , .., ,..
, , ..
.. ......
. ,.
. ......
.
...1,-
...... , ...
.
. . . ..
......
r
-1USd-
1. A.
-225d-
..
.. .,
.,..... .....
oc
~~ . ... .
. ~
o - - -m
-279-
..
.
. .. .. .
- . ..... .. ......
-315d-3668-
".
1.Olz
13Hz
1.Hz
1mNHz
1Umz
P(U(OUT)/(U(IW)-U(III)))
f2]
+
1KHz
1.6KHz
IeHz
D(U(UT)/(U(IW)-U(IHH)))
Frtquency
1OWNHz
1.@NHz
1SHz
1@MHz
Mseatesgas
Zrro(D((OUT)(V")-VN..
PhaOWWseM(BOUT)(VYNP).
45843kM
5B
Gain
Phase
Figure 6-2: Frequency Response of SpA Micropower Op Amp with HAECC Compensated Down to
Have Om = 450 at 50pF Load to Compare with MIC861
73
Frequency Response
5pA Op Amp [PM=45 @ CL=50pF, vs
Simple Miller Compensation
Hybrid Explicit Cascode Compensation
Hybrid Asymmetric Embedded
Cascode Compensation
1O0kQ
C=
MIC8611
=
CR
1O0kD
GBW (kHz)
(D (0)
GBW (kHz)
DM (0)
SMC
329
81
267
45
HECC
369
79
327
46
HAECC
403
72
375
45
453
225
N/A
350
MIC861141
Table 6-4: Comparison of Unity Gain Frequency between the Proposed 5pAInicropower %YpAmps
and MIC861
Future Work
For the same op amp architecture, different frequency compensation schemes
result in different performance characteristics, especially the speed. One potential
direction to further this project is to improve the biasing scheme of the output stage. A
more power-saving biasing scheme for the output stage can help increase the speed of op
amps because more current can be allocated to the output pair and the differential pair.
Another potential improvement is to research on novel compensation techniques. This
work includes the optimization scheme in compensating an op amp such as how to
minimize the capacitors in the simple Miller path in the hybrid compensation while
guaranteeing op amp stability.
"3 The phase margin is not given in [4]. It is estimated from the datasheet that the IC has 2-3 periods of
decayed oscillation in the small-signal pulse response at 5OpF load.
74
Appendices
Appendix A
Schematics and Characteristics of 20pA Micropower Op Amp with
Simple Miller Compensation (SMC)
Appendix B
Schematics and Characteristics of 20pA Micropower Op Amp with
Hybrid Explicit Cascode Compensation (HECC)
Appendix C
Schematics and Characteristics of 20ptA Micropower Op Amp with
Hybrid Symmetric Embedded Cascode Compensation (HSECC)
Appendix D
Schematics and Characteristics of 20pA Micropower Op Amp with
Hybrid Asymmetric Embedded Cascode Compensation (HAECC)
75
76
Appendix A Schematics and Characteristics of
20pA Micropower Op Amp with Simple Miller
Compensation (SMC)
LIST OF FIGURES IN APPENDIX A
Table A: Characteristics of 20pA Micropower Op Amp with Simple Miller
Compensation (SM C) from Simulation..........................................................79
Figure A-1: Schematic of 20ptA Micropower Op Amp with Simple Miller Compensation
81
(S M C ) .......................................................................................................................
Figure A-2: Frequency Response with CL=I100pF and RL= 100k
....------.................
82
Figure A-3: Frequency Response with CL=O, 10, 100, 200, 500pF and RL= 100kQ -.----83
Figure A-4: CMRR vs Frequency with VN=0, 0.65, 1.3V..........................................
84
Figure A-5: PSRR+ vs Frequency with VN=0, 0.65, 1.3V ..........................................
85
Figure A-6: PSRR- vs Frequency with VIN=O, 0.65, 1.3V ..........................................
85
Figure A-7: Small-Signal Transient Response with CL=lO0pF and RL= 1OOk
-........
86
Figure A-8: Small-Signal Transient Response with CL=0, 10, 10pF and RL= OOkQ
....
86
Figure A-9: Large-Signal Transient Response with CL=100pF and RL=1O0kQ .......... 87
Figure A-10: Large-Signal Transient Response with CL=0, 10, 1OOpF and RL=
k00.. 87
Figure A- 11: Output Transistors Current vs ILOAD ---...........--.......................................
88
Figure A-12: Rail-to-Rail Output Voltage (vmN and VOUT with Av=5)..........................
88
Figure A- 13: Positive Output Voltage Swing vs ISOURCE ..........--...-.................
89
Figure A-14: Negative Output Voltage Swing vs ISINK
89
...................................
Figure A-15: Short-Circuit Source Current vs Supply Voltage....................................
90
Figure A-16: Short-Circuit Sink Current vs Supply Voltage........................................
90
Figure A-17: Frequency Response with CL=OpF and RL= 100kQ @ L= 1.0, -0.5, 0.0, 0.5,
1.O mA ........................................................................................................................
Figure A-18: Frequency Response with CL=IOpF and RL= I00k
@ IL=-1 .0, -0.5, 0.0,
0 .5, 1.0mA .................................................................................................................
77
91
91
Figure A-19: Frequency Response with CL=OOpF and RL=IOOk
@ L=- -. 0, -0.5, 0.0,
0 .5, 1.0mA .................................................................................................................
91
Figure A-20: Schematic of Bias Cell for 20ptA Op Amp with Simple Miller
Com pensation (SM C) ...........................................................................................
92
Figure A-21: Reference Current and Reference Voltages vs Supply Voltage..............
93
Figure A-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair
vs Supply V oltage................................................................................................
78
94
Table A: Characteristics of 20pA Micropower Op Amp with Simple
Miller Compensation (SMC) from Simulation
Simulation results are at 25 0C.
VDD
=
2.5V and Vss = OV.
Primary Characteristics
Value
Si____ ted
Specifed
Simulated
Specified
C ondition
Sym bol
Param eter
GBW 4
Gain Bandwidth Product
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
CL = IOOpF
RL = 100W
> 100
Is
Supply Current
No Load
<21
CL =lO0pF
RL = 100k
> 0.3
> VDD VINCM'
5
Input Common-Mode Range
(O-61.5')
19.95
1.25V
(Untrimmed) Input Offset Voltage
VINCM =
0.65V
VOUTH
High Output Voltage
ISOURCE =
VOUTL
Low Output Voltage
IstNK =
I.0mA
VOUT
I.OmA
CL = lO0pF
ISOURCE
Output Source Current
SINK
Output Sink Current
RL = I00kfl
RL = 100ka
sA
1.3
and includes
negative supply
voltage
V
4.1
mV
0.3V
2.34
V
<Vss + 0.3V
0.19
V
> 1.0
135
mA
> 1.0
1.4
mA
voltage
vos
MHz
dB
and must include
negative supply
-
U nit
<5
> VDD -
Secondary Characteristics
Value
Symbol
Parameter
SR+
Positive Going Slew Rate
SR-
Negative Going Slew Rate
Condition
Av= IV/V, lV
Step
Av=
IV/V, IV
Step
Specified
Simulated
Specified
Simulated
Unit
> 0.15
0.223
V/ps
< -0.15
-0.236
V/ps
"4 Gain bandwidth product per supply current GBW/ Is = 18MHz/mA @ CL = IOOpF.
'"Verified by CMRR simulation in Figure A-4.
Conservative estimate from calculation.
Maximum output source current is measured when the other transistor in the output pair starts to turn off,
i.e. its current goes down to as low as IpA.
16
17
79
CMRR
PSRR+
Common Mode Rejection Ratio
@ DC
> 60
Positive Power Supply Rejection
@ DC
@ C>084.5
>60
@ DC
@C>6099.4
>
Ratio
PSRR-
Negative Power Supply Rejection
Ratio
t,
0.1% Settling Time
Av= IV/V, IV
Step
80
144
dB
60
<10
dB
dB
529
s
0241 A
2.41 we
4
T2"
9
VT
2A1uA
0.241uA
2AA
0241uA
0.242uA
I
I fB 7
L
IL4U
4224
L '115
D
14-
10.3uA (@VSUIFL2.5V)
0.241 A
4
L
31
/2
_
II
I-
FLJ I
vOCm
i
1
10G
709
INP-
S5
50/10
L M23
Im
C
%t-
L 3i
$$UT
L
0
31.
*G
M
L
L
MN4
22/2
GNU
GNr
M1-
L
12
4
I
I
-I2es
LL
2PF
,1
GUT
IL
B13
I
0-2 C2PF
T1,
MA9L
1r
lei I
10-
L M6
3/VAO
I
,
3422
3'4C
I MEC
DO
3E ,
Figure A-1: Schematic of 20pA Micropower Op Amp with Simple Miller Compensation (SMC)
81
S/
Gd-
-9@d1
C
a
i
_-0-
n
Phase
d
B
II- o
..
Gain
-135d-
~~~~~
.
,4 4,
-iS9d-
.....
4,
.
4
Ls -----------
LJ. .
. J
-I
-225dU1
I~~~~~~
j
-270d-
N,
-IOU
As
J- j F
- A AA-
[I
-
ftLs4U
.LL
A,
...
IL
.
II I
L.
.
LU -CI . A~ .
..
-401
4i
U
IJ, IUJ
j-Uk--1
q
a
t
:.LL
4,...
1161..J1L
_1
1aA44
_u,ILA,
.
Is~
1u~ 0~ 0m z 1.H 10H 10.z 1
.
Freq uncy
L UI.J.1.
-
1
I0~
A
I
*JU 1 ..
~
A
.J
..
Is .L - -LJ
.
-
-- L--
..
LILUL
I
L'
U
L .A
.
U--
t-
A
..
I:U
--
L - 6 11
-
LU
JI.
I
---
J
1 - 1-1I*1-1LI--LU1
JL
U
-f*z I
1ff
K~
-6-JJWU.,
......
--
JJJU
L
I 01H
-
-315d-36 Sd-
Ev~W
P
~eernD~
meMmelt
erIosD((U)/Vl)Vl
(OT)/V(M)-Vo ..
jon~sgir(P(V(OLJT)Ay(1i)-V(I1...
Vaii.
.
359.82741 k
.61.4703
....
I~~.................
....
.....
---- ................................ ......................
-------I~ _- - .98178::
Figure A-2: Frequency Response with CL=lOOpF and RL=100kQ
82
.....
...............
-..
...........
.....
.............
p
h
a
S
Od-
C
200---
a
o0
4I2I~~
-45d-
n
e
-;,
-90d-
CL
j C, kii~i~w-
i
d
T I -
-
t, . I
,!,u
-
-
d
S ,
r
e
e -1U2d-
,, ,
I
-- -, - .
-
to
.o
Is
4-
j
,.a
a...
s s ,, ,, ., ..e a.,
--
-vol
-
L l., L a . w
I
- -- ---
--.-.-.-..-
.4m - - --
-
e -135d
9
----
,
., L,
..
It
,
9 ### , . . ..6,0 , , , ,""Nw4. *,1, ,.- . L ... ,,,,
',,
e , 1, 1. "...
e . e s ...
. , , s ..,
e
-OPhase
*.-.........-.-.
wo m n -- - -
-- ,L.
Symbol
(pF
0
- -
-0--.
---t ,
a j _-I to , _0.
I
.a
...
. . . v.
, , , ,a s ,
a , :,,
I
J
.
t
,
..e.,8
, a e ,,,,L
.
, ,
.
-- u .
1.
to..
-
.
,,,1
Gain
a j k -- ... 10 4JA U
1
. ...
-
t
1
J.
Phase
t
Gain
100
-225d-
Phase
-27@d-
NNNA--
Gain
o
-0- L A LUI
-315d-
#
I
too.,
-368d-
1. fmHz
pr
I lot.
i ,e s
, ,
I- -I. I . . .IA --- L . . .g
.,
ae....g , aae g
g
1.@Hz
11Hz
ImHz
1IbMHz
S oP(U(OUT)/(U(IEW)-U(IM
)))
Ull
00
-4
Evalute
17
I
1 . .o.,.i
Measwuemt
ZeroCross(D8(V(OUT)(V(IMP)-V(1IM...
PheMr(D(V(OUT)KV(W)-VO...
GnMrgin(P(V(OUT)((INP)-V(t)...
1
1
414.11136k 1
91.70296!
25.919361
11Hz
(1
.- , ,- .*J
' ,I'l.,
.g . .ea.se. g i i eii is a i
1KHz
100KHz
1.MHz
x 1, * DB(U(OUT)/(U(IHP)-U(IMH)))
Frequency
1.6KHz
I
2
41336830k
359.82741k-
87.91499
34.44376
81.47403
50.98178
4
299.75193k
a
LI~ e
47.30284
5672713
200
Phase
s
us I
1011z
IMHz
500
I
Figure A-3: Frequency Response with CL=O, 10, 100, 200, 500pF and RL=1OOk
83
S
La M
Gain
-0Phase
211.37438k
31 33518
64.51244
.
Gain
C law: 20A SMIC [Pl=60: * C =l9ppF1
V I NB= C-0
0. 55, 1:,-----3V I
------------ ----------------- ----------- ------------ ------------ L ----- ----- I ----t ------------ --- ----------------- ----------m
R
-------------------- ------------------------ ----------- ----------- ---------------------------------- -----------R
--- -- -- - - -- - --- -
--- -- -- --- --- --
-- -- -- - --
4
-- -- -- --- - --
-
VIN
M
- - - - - -
- - - - - - - - -
-0- -- -- -
d
B
----------
------------------------
------
I -----
-----
r - --- -- --- --
- - - - - ---- - - - --
------------ - - - -
-----
- -- --
------------ ------------
T ------------I------
------------
-----
------
-----r -----
----- I-
- - - - - - - - - - - --% - - - - - - - - - - ---- - - - - -- - - - - r
----------------------- --- -
-----
r -----
-----
----------------
-----
-----
-----
-------------------
-----
r -----
- --------- ------------ t------
-------------
-- -- --
-------------------------
------------- -- ---- - - --- -- - -- ---
-- - - - - - - -- -
--
-- -- -
- --- -
-- -- --- ---
-- --- -
-----------
-- - - - - -
-- - - -
- - - - - -
- - -
0
T ------------I-----------
------
----- I ----------- I ------
- - - - - - - - - -I - - - - - -- - - - - r - - - - -------
- -- --
- - - - -
- - - - -
-
--- --
-- -- --
------ - - - - - -
- - - - -
-- -- -
- ---
- - - - - - -
-
- ---
0.65
-V1.3
- - - - - -
- -- ---
-- --- -
- - - - --- - - - - -
I.ftoz
-- - - - - - - - - - - - - - -
-- --- -
- -- -
-- --- -- --- -
-- --- - -
- --- -
--- --
-- -- --- -- --
-- -- -- - -- --
- --- -- -- --- -
- - - - - - -- - - - -
-
-- - --
-- -- -- --- --
- --- -- --- --
- -- --- -- -- --- -- ---
-- -
-- - - - - L - - - - - - - -- - - -- -- -- - --- -- - -- - -- - --- - - --- - -- --- -- - - -- --T -- -- -- - --- -- -- --- - --- -- --- -- --
1 OMHZ
1 OOMHZ
DB(U(CM)/U(OUT))
I.OHZ
1 @Hz
-- - - - - --- - - - - - - - - - -
-- ---
- --- -
1 O@Hz
-- ---
1.M(Hz
- - - - -
- - - - - - - - - - -
- - - --- - -- -- - - -- ---
-- - - - --- - - - - -
- - - - - -- - - - - -
- -- ---
-- - - - --
- - - - -
I OKHz
- -- ---
I OOKHz
-- ---
-
- - - - - - - - - - -
1.@Mz
- - - - - - -
- - - - - -
- - - - - - - - -
- - - - - -
- - - - - - - - - - - -
- - - - - -
-
- - - - - -
1 DOMHz
1 @Mz
Frequency
-
Meammenmt RewAs
-
EVAN**
PF
PF
Measurenmt
lYaMDB(V(CM)/V(OUT)), I Hz)
lYdX(DB(Y(CM)/V(O(JT)), I OkHz)
-
1
2
144.14496 !
11 1.45M
1- 1
128.63895:
I
113.986431
-
3
103.33220i
............
...
...
77.41054
....
............................. .....
...
........
........................
-
Figure A4: CMRR vs Frequency with Vuj=O, 0.65,1.3V
-
-
-
r
-
84
-
p
les-
VINB=[
20uk SMC [PM:660 6 CL=;lOOpF]
s
R
R
............
...... L ........... ------------------------------------- L ........................ ........... ------------ ...........
------------ -----
-----
VIN
(V)
------------------ ------------------ I ----------- I ------------
------
-0..... .....
d
----- -----
----- ------
------------ ----- -
........................ .
------ ------------------
--- -----
------------ ----- ----- -------------
0
------------ ----- ----- ------------
------ ..... .....
S.,
0.65
------------ -----
............ ----- ----.....
------------ ------------------------------
------------------ ----------- ------------ ---
..... ............ ----- -----
---
--------- ----------- ------------
------ ----------- -----
----- ------ ------------
............ L ..........................I---------------
----- -----
I @mHz
I GmHz
I flnHz
INZ
1.6Z
..................
............
----- ------------------------ ------------------ ----- -----
l.MHZ
I 98HZ
I smz
1.M z
I 8MNz
1 MHz
-V1.3
DB(U(UDDA)/U(OUT))
Frequency
EI*W*
I
Me~*M*M
I
F
IYdWDWAVMA)/V(OUT)), I HZ)
F
FF
-jYdXMXWVDDA)IV(OU'r)),IWft)
1
1
2
04.567541
i7EbiiT
3
04 -54W I
37M I
. ..........
............
.1 -1-11-11-
Figure A-5: PSRR+ vs Frequency with VIN=O, 0.65,1.3V
p
loo-
(TITW;
...........-,II--------------I----------------
----------- ------------ ----------- ------
R
R
...................
Vm
------
------ ,------------- ........... - ----------- ------------ L---------
d
B
----- ----- ............. ------ -----
VINB=1
i: -----------
----- ............ -------------------------------- ----------------*1"
......
--------
m
............
. ............
------- ...... .
-- ----- -----------
-00
SO-
------ ----- -----
------------ ------------ -----
----- ------------------ -----
------------------------------ --------------------............
------
----------- ----------------------------------- ------------ -----
----- -----------------------
----- ------------
-----
----- ------------ -----
f-------
-----
-----
I------ -----
--------- ------------ -----
L ----------- ------ ----- -----
----- ...... ..... L----------- ------------------ ----- ------------ -----
----- -----59,
I. OmHz
------------------ ----- -----
L ----------- ------ ----- -----
----- ----- ------ ------I-----
----- I------------ I-----
----- --------------[ ...........
----------- ------------------ ----- ----I . MHz
I liffiz
I ONZ
l.Mz
I sSmNz
I SmAz
OB(U(USSN)/(U(OUT)))
I MHz
0.65
--
------------------------ - ---I
----- ------------ -----
-0-
------ ----
-V1.3
----- ------ ----
------------------- ------------ --------I $MHz
------- --------
1.@Mz
ISNHz
Frequency
"mmen"m
I
pr
jYdXMWVVnSNYMOUT))), I 04z)
F
Cr
IYatX(DBrVrVSSNW(OM). 10ft)
R*W"
..........
9912763!
I
35BM
35.74MI
Figure A-6: PSRR- vs Frequency with
85
VIN=01
350
0.65,,1.3V
729MU
SMC
20uM----------------
----------- -----------
------------
---------
I------ -----
L ............
-- - - ----- -- - ---- -- - -- - -- - --
---
- - -- ---. .. ..
.. . .. ..
. .. . . ..
- -- -
.. . .
- -- - - -- -- - -
VINP
VOUT
680MU
-----------
..... . ...
........... -------------
--- -
-----
...........
-----------
I------ I ..... .
----------- -------I ....
-- ------------------- -----------
- ---------------- -------------------------------- ----- - ------------------
I649MU
----------- ................... ----- ----f
-----------
----- ----
-----------
----------- ------
...........
-----------
----- ----------
........... ......
...f
------------
6 99MU -
-----
-----
----
-------------- ...........
----- ----2 JS
Isus
1 @us
5us
............I -----------
........... ----- -----------------------------------
-----------
569AU 1
as
-----
-----
----------- ------
----- -----
Q(OUT)
U(IW)
Time
I
As"emon"4tassuft
I
E.*Wo
F
Me"WeIn"A
IS&*oTIM XRononM Qj
I
--
VAN
I:W1
I
-.-
Figure A-7: Small-Signal Transient Response with CL=1OOpF and RL=100kfl
I I
I I
fzMW-------------- ---- ..... .....
----------- --------------------------
..........
----------..... 20uA.SMC-..-,,..... ----- --------------- ---------------- ......I ----- 11
..... ............
VINP
6oftu...........
------------- ---------------- -
VOUT
----------- ------
---
-----
CL=OpF
------
----- - -------------------64@RU....................... .....
...
-------------
--------------------------
.................... ................
........
........... ------
........ ..
VOUT
.. .....
-----------
---------- ----- --------- ----------------
---------------- ------
-----
L .....
-----------------5690U
Is
Sus
UOUT)
U(IW)
Evaksoo
Mbftafi"
-----
................. ......
.......
...........
-----
-----
-------- -----
-----
---
-----------
----------- -----......*
----------- -----------
----------------Isus
1 ous
2 JS
Time
Meounvak"t
ONOWY(M ). 0.1 -SM
1
3
004 1
...
.........
..........
2..,.4rO .%.....
..
..
....
.....
...
....
.....
...........
Figure A-8: Small-Signal Transient Response with CL=01 10, IOOpF and RL=100kfl
86
CLOODF
I ...... -----------
VOUT
CL=1OOpF
1 1 2"
>I:Jr~
-
j
j
2du% SHjC
...................
LU_
LVIN
1~~~~~~
......
L
..........
1
-
-----------------
_
es
U(IW)
----
_
_..f
_I
_
2Uus
ISus
IUss
Sus
&U(OUT)
3 is
25Sus
.
35
Time
i
17 1swTsey qmqmn. T, 0.1, su..
_
_
__
6*6~
I__
_
_
------------ _ _ -.- .......
_
i.....
..
Figure A-9: Large-Signal Transient Response with CL=IOOpF and RL=lOOkfl
.1
____
2"0A,
-El)-VINP
/
I1.
VOUT
-+-
.
.
.
.
.
.
.............
..
/...
------__--I--------I
I/-
9.
CL=OpF
VOUT
Ci=l~pF
you'
I5
Is
25 us
I Sus
I *us
Sus
SJ(IHP)
U(OUT)
Time
Evahai.*
h.MOSPOMN
F
*WOL
I
2
1
1SwTkmne)RmigV(OUT),0.1, Su.
I
5u.
6.11003u!
6f318U
5.285M u i
1
29.55.'
529k
222
ll
6
Figure A-10: Large-Signal Transient Response with CLO,1 10, lOOpF and RL=1O0kfl
87
as
Ci=lO0pF
.................................. w ....WP...wiW ...%W...Ih...
i Sm
-1. .4
...........
till
111F
fit
.............
............
------------------......
...........
I sun
............... Mt'!
...........
......... .............
MrMM!MMI
............... .
2
----------------- ----
lD(MH2P)
....
.......
...
...........
- .
........I ---K
MMMSM!
...........
..................... ....
lilt 111MMMM
...........
...........
-------------
ISPA5
-3. MR
........
;- -Is
....
....
...
3. 80A
2. IRA
1.811A
[LOAD
6661*WWFWt PAIDURS
evome
E
v
i
I
a STA)
YdXM(MM2N), 0-10A)
YdXMCAM2P), 1.ftA)
d)((C (MM2011. 1.0MA)
Current in
NMOS
Transistor
M2N of
output
Pair
3.9MI U
11
Figure A-11: Output Transistors Current
vsILOAD
...
...............
....
....
............
A.
....
..........
I
2.
PMOS
Transistor
M2P of
output
Pair
-- 0.-
---------....
........
.....
............
....
....
......
.....
- ...
........
....
-- -- --------1..................
....
......
....
10.1842OU
.............
..
S04.663WU
4 663eSu
jYoM 4Xh#A2P),0jft A)
YstX(" MMZQ, OA)mA)
Yam-Q(MMVI
6 i
Val"
U0114141reamd
Current in
IMN
1 -------0momOmfim ....................
mdlml ...1 ---f::: F
F:
....
.... ....
...
.... ....
------r ----
-1.01101
-1.011A
-2. ORA
lD(HN2N)
-. qjMmm
.......
. ...............
mhm hm hm hm momnomimd
.......
In.
..................
. ..............
!HFMFH!MH
I ..........
..........
....
-- - -------- ............................ ..........
!MMMM M!MMM!M!!
....
. ....
-----------
..............
1111l
..........
91111
14
..........
....m!"mm",
-- G.1DM2P
..................
2
P
I
..... AV-4h .94 J,
-------------VINP
........................
. . : I
..............
....... .......
.....
...............
.........
..........
............... ...................
.......
......
.....
VOUT
..................
...............
..............
-- --------------I.
GO-
..............
---------------------.........
.
.............
.........
------------------------.. ...............
..........
----------
........... ...
5 @us
as
U(IW)
. . .........
--- ----
I IOUs
........
ISSUS
---------------
---- --- ----
---- --L------------------
250us
299tis
- U(OUT)
Tim
vsklo
+
F
" Oun)
Im
lmr<v(okm)
----- ---------
:!
-iww2ft I
Figure A-12: Rail-to-Rail Output Voltage(VINand
88
..
.....
.....
.....
VOUT
with Av=5)
HI
..............
2
------------- ................
....... ......
.....
.
I
---------- ---W- ...... .....
I
............
.....
...................
- ...............
.. ..I.....
..... ..
........
..... ......
W -
..............
ou 4--L
N
C;OR
3.SFA
3. IRA
2.SMA
2. IRA
I.SNA
1. am
4. "A
4.50A
S. GOA
U(OUT)
ILOAD
No"m
Evokuto
vwkw
Mommonwo
2SM 1
2
lydw(OIJT). ODRA)
lydw(OUT). 014m)
jymmmoun, la")
pr
F
Figure A-13: Posilfive Output Voltage Swing
0
u
t
p
vsISOURCE
4.W..........................
.............. ...........
.............
.................
...............
.........
..............
..............
.......................
....................
........
.................
t 3.*Uu
........ ....
...........................
.................
-----------
...........
t
2.OQ-
------------------
...........
e
......... I------ --
............
........
...... .......
...........
u
........ ...........
........
.............
J-
J-
.. ........
-----
--
L.
..
........
L.
OU
-4.SRA
-5. &A
U(OUT)
Eva"*
-4. sm
-3.50A
-3.00
-2.50A
-2. 9MA
-I.SNA
-1. sm
L
-0.50
ILOAD
Momwanow
YdXMOUD. OnnA)
Ystxm ouT). -0.&" )
me"w6mont
vow
2133828n
.......
.......
89.1 4874M
_ 187.3=3m
L'' -.1-1-11
J- - -1-
.......
----------...
..
..
..........
.......
..........
1.....
Figure A-14: Negative Output Voltage Swing vs
89
ISINK
---1-*I++11--I+--+I-ll ..........
---------.......
...
....
.................
......
......
............
I
s
a
U
................ -------- -------T
1,
-- -- - -- -
-- --- -- - -- --
R
C
E
20uA:SMC
................. ...............................................
-----11---., --1. ------------------------------- -------------------- --------I----------------------- ---------------- -r - -- - -- -I,- . 7
-.r - -- T
--------
------- ---
--- ---
----------- ----------------
--------
--- ----
--- ---
i --- ---4 ----
....................... .......................
-------- ---
....... ........ ................ ------------------------------
------------ ................
---- -------
------- --------
4 ---4 ------------
i ---4 ---4-
i ....
................ L ----------- . .......
................ ........ ...
............ .................
........... ................................ -------........... ...
----------------------- ..........
............ ............ .........................
....
........
..................... ........ ..................w --ORA -----------------
-------
-------- -------
I ---I ------r --I ------I ...I --------- r ......I ......... I ---I ------I---I ---I---4 --- ..........
SAI
2.5U
. .. . .. ..i . .. .
- --
3.W
-- -
---
4 ---- ......................
............. 1 ---
I ........
-------- ;
......
L .....................
... .
- -- -
.. . .
............ L ......................... ......... L ...
................ ----------------I ---I ...
........r... I ...I------------I ---I ---I
7 ...
-- - -- --
--- - -- -- -
L
I
I
I
3 .5U
of .w
6.W
5.5U
5.W
J1.5u
I(UISCH)
UUCC
Figure A-15: Short-Circuit Source Current vs Supply Voltage
---------------------
...............
----------------
............
-----------
..................... -----------
.................
...
..............
..........
I......
. . ... . . . .. .. .. . .. .. .
- -- - -- -- ---- -
.
.................
.......
- -- -- --
. .. .. .. .
-------- r---I---I------T--- I----
. .. . .. .. .. ... .. . .. .. . .. .. .. .. . .. .. r . . .. .. .
.........
-1-- - - -- - -- -- I -- -
. .. .. . . . .. .. .. .. ...... . ... . .. .. .. . . .
.. . . ... .
........
-------- .......
I--------
. .. .. . ..
. .. . .. ..
-- - -- -- - -- -- -
... . .. . .I .. .
. .. . .. ..
... . .. ..
a
- -- ---- -- -- - -
.. . .. .. . . -- -- ---- --
--
. . . . . . . ... .
.. .. .. .. . .. .
- -- -- - --
-- -
-- -- -- - -- -- -- -- -
- -- I
-- - -- -- -- - -- -- -- --- - -- - -----
2.5U
" f(UTSCH)
3 . IU
.. .. ... .
. .. .. . .
.. . . .. .. .. . .. .. .
I . .. . .. .
.. . .. .. . .
.. .. ... .. .. . .. .. .. . ..I.. .. ... .. . ..
-- -- - -- -- -- - -- -- - -- -- --- ---- -- -- - -- --
-22M
.. .. . .. .I .. . .. ..
-- - -- -- - -- --
- - ----- -- --- -
3. SU
-- -- --- -- - -
.. . . ... . r. - --
T
-- -
4.5U
4. su
5.9U
UUCC
Figure A-16: Short-Circuit Sink Current vs Supply Voltage
90
5.5U
6.9U
061
I
9
2"
a
5d-I
S-
I
159- -+
-90d
(
-+HiN
+H
--
N
4-
-+
i0 - --
ti
-
-4414
-4 4 --
M
i
H-444
-4H
---
++
W
it
--
--+i
-
iHMH i i--- H4+N ----
-- ++t-
d
-1-6
-135d
-1U1d-225d0
-
"3
-
4 -;
-~~~- --"
-
-
}N'
=
7 R
;
-11--
4
--
-
-
-44 ,4
;.
7 !
-27d-9150-
-i-4+MR
-36d'
IAMz
---------
e-:-i4X----H 4
16Hz
I .Hz
16IMUz
P(U(OUT)/(U(IP)-U(INN)))
1Iftz
H
-
-
HM
1MHz
1.3Hz
166Hz
-
0(U(OUT)/(V(
.
2
i
1706
9--7I
9
.925It
.E.49.jdbl
161
17
1
Fde4.
45d-
i
~g 4~
W
IL=-l.
0
- -
-4-i+:-
--++ |--++i~i -+H
-
----
a
n aei-+4-4-74
0 430,947
43343
4
4I 1
.Ev.udon F.sd.
Figure A-17: Frequency Response with CL=4pF and RL=10Ok @
11 1.1 1 " -,"
: ...."
, Pa . -"N -.
i8
11Hz
1Gz
161
_ )-U(I))
4m482
41062 421 26483k I
ZeorssD~~u~VB)-VtL
41411136k
40s6
~iw cH((v(ouT)4-w-v
TPN-VI -MO
VOCiWV
1. 1z
163Hz
Frequency
, ,
PeakSDUV
:--44
I
MA)
-1.0
I
F443
Evuhitn
1.a
N ++.4I
--++t
-
t W4
Gain
-0.5
d
--
-
-- 16-M
.....
150~~"1
)0
-.-
- -+-......,.....
Gain
..
... .....
8-160d
Phase
e
"...I--E
y t
p 4W
........
"".
-135d
-0Phase
, -0.5, 0.0,0.5, l.0mA
*64
Symbol
Phase
-225d
-270d
a
u~
~~
-315d
-3660d1.
I
......-
16Hz
1. Hz
14MlZ
P(U(SUT)/(U(IW)-U(INN)))
1nz
@Mlz
~ -U ~ -
-
M
s z
1
1
0.5
NZ
1
.Nz
Gain
;t
1111z
1.UMz
15Hz
Phase
1 9IHz
0(U(IIUT)/(U(Il)-U(I86)))
[-
Frequency
e,,aue.
tog *
ZIeoCmo9(
F
o0MM~rgxvOUrXvteN -v
421
4121424k
41336926k
£7009
433.66420
32444376
189
Figure A-18: Frequency Response with CLi=0pF and RL=100kf @
I
6
266-N
20
a
6
-'85d
-9d-90
.
.---
-
dN
-
~ ~ ~~~~
- -i-ia
1
94074364
82
22
.0, -0.5, 0.0, 0.5,
.
--
-~n
:-
Phase
1.OmA
Gain
-
-
-
d
(
8
....
.......,..
l
I=-
1.0
__430_45686r4
96221001 9711496 9449091)-V
227273
94319
2010MI
Gain
I
4*
2
1
e( JTf)(( y)-V L
H
---
n
.l -.-..-..---
1. 1LI
--
-1250
-225d0
)s
-270
-815d0
-360d
-160
1. n4z
1
[0)
A
Z4")CrO..<D(U"
P h sa M
e
6nIz
e-
16Hz
1.^Hz
1 SJIz
P(U(SUT)/(U(IWP)-8(116)))
U)V(%u )-V(
) V
(v
.,.
__
*
L
166Hz
[b
1.
5Hz
15HNz
165Hz
D60((8 UT)/(U(IHP
FrequeuclI
34143 -kI
8 1. 9 1 0 1 9 0 _
4L--"S21
1
1111Hz
.11Hz
_
_
43773
9
4 0 2
1
r A Fr
Figure A-19: Frequency Response with CL 100pF and RL=IO0k0
91
1611H
9-(4111)))
@ IL =-.O,
17 7 1 9
-_d = k -0,- -. , .,0.0,0.5, I.OmA
-0.5,
9 1
A 5 1 4
Start-Up Circuit
4. GnA(@ VSJP=2
J
03E-N9
STARTUPF
.
10:
1!100 L
5.)
4.17nA
4.03nA
0.~f
Bias Voltages Setter
0 241uA
0235uA
Reference Current to Op Amp
IREF Generator
0.241uA
0.241uA
0.241uA
'ii''
-
L110
1H40
L W~OO
L, 10140
L,10/40
L.
flae
I
0- 2 35607
,CC
i
'fa
MW
I11n L
101
Hs
r
I
l-I
oil
G1
L-
L
MOWL
10/
0
tj
6t,
F
I
I
STARTUPR
vcc
V/100L
WSO
L
2/1201
/100 X&s
L McL
G/
L
_I
_
IIIINCS__ODE_
L8
fl314
N 17
RE
1c
Figure A-20: Schematic of Bias Cell for 20pA Op Amp with Simple Miller Compensation (SMC)
92
, ;4 ,Ak
;RU
I
1.6u-
.
11
I -- -- -- -- -- -- -. ..
L
A -- --
-- -- -- --L
-- -L -- --L - -
t -- --
- -- -- --
I - -- -- -- - ---- - -- &---J
-- -- -- --
- -- -- -- - ---- L
I - -- -- -- - --- -r
.1
- - - - - - - - - - - - - - - - r - - - - - - - --- - - - - - - - - - - - r -- -T
-,r
L -- -J --- -- -- - -- --- -- -
- -- -- -- --
. .
- - - ---- - - - - - - L
.. ... .. . .. ... .. .
-- -----------Z*--------- - -------- -------- --------------------------------------- --------- ----------- -------------------------- ---------------r
T -- - I -- -- -- -- -- -- -- --
I - --
- - - ---- - -
Reference
Voltage for
NMOS
Cascode
Transistors
----------------
----------------
't - - - ---- -- -- -- r - --
1.2U
U(HCASCODEB) * U($G-UCC)
-- -
U(PCASCODEB)
-- -- -- - --- -
A - -- J - -- -- -- - --- -L
- - - - - - - - - - - ---- -- -- --r -- -T
&...J
.. .. -- -- -- --L -- -A
I-- -- -- -- -- -- r - -- T
I - - - ----- - --- -
J - -- --- - --- -- L - - -I
J-- - - - - - - - - - - - L
I - - - ---- - - - - - - r
X - - - J - - - ---- - - - - - - L
Vw-
I - --
VKASCODEB
A
icr
Mania -
9
L - - - A,
J -- --
- -- --- -L.
I
-j - - - - - - - -
---------------------------------
SEL>>
-- -
L
------------
-----------------
-------------
I - - - -I - - - - - - - r
2.SU
1,ID(NHB11)
r
3. ou
3.5u
o - ID(HSTARTUPREF-MS2)
T . . . . . . . .... . .
----------------r ---
1
4.SU
4. OU
I ---
I ---------
r -------------
Pr
Pr
Pr
PF
;or
Meamwenmt
YdXM(MMBI 1), 2."
Yetxm(w" 1). 6.0v)
Ya0((-D(MSTARTLPW MS2), 2.5V)
jYa0((-DMTARTLPREF MS2),6.M
IYWVMASCODEB), 2.5V)
jYstX(V(NCASCODEB), 6M
lYaiX(V($GYCC) - VTCASCODEB), 2."
lYat)((V($0 VCC) - V(PCASCODEB). 6.OV)
IDMB11
I IN 0 1 MA -PAMUN*
N
Reference
Voltage for
PMOS
Cascode
Transistors
Bottom
-- 0-
S.SU
UUCC
Evaluge
rior
Pr
Top
-43VI#CAXODEB
- - -- -- --
-- -- -- -- -- -- -- -- -- -- --- -- -- - -- -- -r -- -T
- -- - --- -
- - - ---- - - - - - - - - - - - - - -
- -- -- -- -- -- -- -- -- --
-
Reference
Current of #*
Vdtle
..
240SW
.. ....................
7n
........
.......
......
.
.................................... .....
24322219inill
.........
...........
...........
............. ...........
..
.........
........
......
4D=
n
3i9iF2i-ln
.......
Op Arnp
........... ..........
1354781
1.46MS,
Il
.........
..
Figure A-21: Reference Current and Reference Voltages vs Supply Voltage
93
-- *.IDMS2
I
Current in
Transistor
MS2 in StartUp circit
L--- 1 ... j ---- -------- L --- 1 --- j-- -- -- --- -- - - - - r---T
j ------------- L -------- j ---- ------------------------------ ------ ----- -r
T
- -- -- -- ---------- - -- - --- -- --- -- -- -- -- - -- - ---- -- -- -- -- -- -- -- -- - -- -- - -- -- --- -- -- -- -- -- -- -- - ------ -- -- -- -- -- -- ---------
-- -- --- -- --- - -- -
- - - - - - - - - - - - - - - r--.T
- - - -I- - - - - - - - - - - - r - - - - - - - - - - -
L - - - I - - - J- - - -I - - - - - - - - L - - - I - - - J- - - ---- - - - - - - I
- - - - -- - - - ---
- -- -
, - --
A - - - J - - - - - - - - -- - - L
-.1 - - - - - - - - - - - T - - - I - - - - - - - - - - - - - - - - ---
I - -- -- -- -
J -- - --- -- -- --
IIOUA
-------------------------
--- ----- - --- -r -- -T -- ------ ----- - --- -
------------ L
- - ------ ----- - --- -
T - -- ----- ----- - --- -r
--------------A --r ---
T ---
I ------------- r ---
-------- r ---
T ---
I ------------------ ------- I ----
IIIIA
---------- ---
----------I -- -2
L - --
-- -- -- --L - --
-- -- --- -L
---
--
r ------------
r --------------------
-------- r ------------ --------
- -- - - -- --- - r -- T - - ----- ------ - --- -- ------ ----- - ---
----- -- ----- ------ - --- -r
-------r
- ---
-- ------ ----- -
j ------------------
- -- ----- -- -- - --- -r
.-
-- -- -- --- -- -
-IOUA-
-n
A. - - -
-- -- --- -
--
---
----------------
---
----------------
---
---------------- L ---
--- j -------------
--------------
--- I
-------- r------- I --------------- ---------------------- ------------- ------- r --.................
-------- L
1-- )----------- L ---L ------------------ L ---1 -1 ----------- L---I --------- -------- L ---L ---j----- --- --
- --
I - -- T - --
-26uA 1
2. SU
j ----------
j - ---
-- -- -- --
--
- -- - - --
- -- T
- -- -- --
:r
"I
- - - --- - - -
.
-
-
. -- - - - - - - -
- - - --- - - -[
- - - - - -
- -- -- -- -
-- -r
I - - - j - - - --- - - -
4. SU
4. w
S. OU
S.SU
6 . ou
meawmenwWA Retake
w
17
1
FF
Quiescent
Current in
NMOS
Transistor
M2N of
OuUM Pair
17
IDW17
3 . ou
3.SU
ID(MM2P) * ID(MM2N) v ID(MM617)
UUcc
EvdLK"
pr
PMOS
Transistor
M2P of
Output Pair
IDWN
- -- - - - - - - - L
. . . . . . . .. . . .... . . . . . . . . . . . . . . .. . . . - - - - - - - - --- - - --- - - ---- - ------------------------- L --------
IDWP
Quiescent
Current in
I -- --#-- ----
----
-- -- -- --
A -- -i -- -- -- -- -- --- -- -
--0-
Measurenwnt
YatX(l)(W42P), 2SV)
YatX(K)(WA2P), 6.OV)
YaO((K)(MM2N), 2.5V)
YatX(V(MM2N). 6.OV)
Yat)((D(MMB17),2.5V)
jYdX(D(MMEM 7), S.OV)
Vakw
I
-10.1 6430u' :
...........
....
............
...........
- .1.......
........
-1 2.Obl 89u I
.
...
.......
........
........
........
........
..
.......
......................
I n.1 642&j 1
...
.........
.
.......
12.06226u
.............. ...
.............
................ ......
-2.40866U I
-2.4M92u;
..
.........
........
....
...................... ..
......
.........
. ......
.......
................................... ....
Figure A-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair vs Supply Voltage
94
Quiescent
Tail Current
of Differential
Input Pair in
Biasing
Transistor
MB1 7
Appendix B Schematics and Characteristics of
20pA Micropower Op Amp with Hybrid Explicit
Cascode Compensation (HECC)
LIST OF FIGURES IN APPENDIX B
Table B: Characteristics of 20pA Micropower Op Amp with Hybrid Explicit Cascode
Compensation (HECC) from Simulation......................................................97
Figure B-1: Schematic of 20tA Micropower Op Amp with Hybrid Explicit Cascode
C ompensation (H ECC ).........................................................................................
99
Figure B-2: Frequency Response with CL=100pF and RL= IOOk-----------................-
100
Figure B-3: Frequency Response with CL=0, 10, 100, 200, 500pF and RL=100k.-
101
Figure B-4: CMRR vs Frequency with VIN=O, 0.65, 1.3V .............................................
102
Figure B-5: PSRR+ vs Frequency with VIN=O, 0.65, 1.3V.............................................
103
Figure B-6: PSRR- vs Frequency with VIN=O, 0.65, 1.3V .............................................
103
Figure B-7: Small-Signal Transient Response with CL=100pF and RL=100
104
-........
Figure B-8: Small-Signal Transient Response with CL=0, 10, 1OOpF and RL= 00
.. 104
Figure B-9: Large-Signal Transient Response with CL=100pF and RL100 k.......
---
105
Figure B-10: Large-Signal Transient Response with CL=0, 10, 1OOpF and RL=I00kQ 105
Figure B- 11: Output Transistors Current vs ILOAD-...----------------......................................
106
Figure B-12: Rail-to-Rail Output Voltage (VIN and VOUT with Av=5)............................
106
Figure B-13: Positive Output Voltage Swing vs ISOURCE-...............................................
107
Figure B-14: Negative Output Voltage Swing vs ISINK ...........-------........................-------
107
Figure B-15: Short-Circuit Source Current vs Supply Voltage......................................
108
Figure B-16: Short-Circuit Sink Current vs Supply Voltage..........................................
108
Figure B-17: Frequency Response with CL=OpF and RL=100
@ IL-1-0, -0.5, 0.0, 0.5,
1.0mA ......................................................................................................................
95
10 9
Figure B-18: Frequency Response with CL=1OpF and RL lO0k @ IL=-1-0, -0.5, 0.0,
0 .5, 1.Om A ...............................................................................................................
109
Figure B-19: Frequency Response with CL=100pF and RL1I0kn @ IL-1.0, -0.5, 0.0,
0 .5, 1.Om A ...............................................................................................................
10 9
Figure B-20: Schematic of Bias Cell for 20pA Micropower Op Amp with Hybrid Explicit
Cascode Com pensation (H ECC).............................................................................
110
Figure B-2 1: Reference Current and Reference Voltages vs Supply Voltage................ 111
Figure B-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair
vs Supply V oltage ...................................................................................................
96
112
Table B: Characteristics of 20pA Micropower Op Amp with Hybrid
Explicit Cascode Compensation (HECC) from Simulation
Simulation results are at 25*C.
VDD =
2.5V and Vss = OV.
Primary Characteristics
Value
Unit
Symbol
Parameter
Condition
GBW 1'
Gain Bandwidth Product
CL = 100pF
> 0.3
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
CL = IOOpF
RL = 100k
>100
120
dB
Is
Supply Current
No Load
<21
193
pA
(Om-61.2')
RL = I00k
> VDD -.
VINCM 19
Simulated
Specified
Input Common-Mode Range
2
5V
negative supply
(Untrimmed) Input Offset Voltage
VOUTH
High Output Voltage
VOUTL
Low Output Voltage
VOUT
VINCM=
0.65V
ISOURCE =.OmA
SINK =
1.OmA
CL= IO0pF
ISOURCE21
SINK
Output Source Current
Output Sink Current
RL= I00kD
CL= OOpF
RL = Ik00k
V
voltage
voltage
vos
1.3
and includes
nregaive supply
and must include
-
MHz
4.33
mV
0.3V
2.34
V
<
Vss + 0.3V
0.19
V
>
1.0
1.55
mA
> 1.0
104
mA
<5
> VDD -
Secondary Characteristics
Value
Symbol
Parameter
SR+
Positive Going Slew Rate
SR-
Negative Going Slew Rate
Condition
Specified
Av= IV/V, IV
Unit
Simulated
> 0.15
0.271
V/ps
< -0.15
-0.298
V/ps
Step
Av= IV/V, lV
Step
'8 Gain bandwidth product per supply current GBW/ Is = 25.5MHz/mA @ CL= IOOpF.
'9 Verified by CMRR simulation in Figure B-4.
20 Conservative estimate from calculation.
21 Maximum output source current is measured when the other transistor in the output pair starts to turn off,
i.e. its current goes down to as low as I pA.
97
CMRR
Common Mode Rejection Ratio
@ DC
> 60
126
dB
PSRR+
Positive Power Supply Rejection
Ratio
@ DC
> 60
72.4
dB
@ DC
> 60
62.7
dB
440
ps
Negative Power Supply Rejection
PSRR..@C-6
Ratio
Av= IV/V, IV
0.1% Settling Time
<10
Step
98
0197uA
197A
1.97uA
VCC
197uA
T
0
197uA
0 198uA
a MuA
0197uA
1
}A
3
I
0
1 6SuA
SuA
8&A@
395uA
VSUP= 2!
8
13
ICAOLL
li'4:
L
L
1
vc
V234
CIlsc
I
ja5{J
V
II
II
~
I
iI40
L
21
II
4.
L4 32
iE
1,
71OG
";A
LL
L
2 212
5
KG
5.1151
33C
1
91I12
LL
275:e e
IX2
'X/2
222
5-32 L
,t,3(
I r2
L
1C
L
s14
-1-
L
L
AE2
2
L
Il-
~~31
2
331
C - 1
7
w I2L
L
40613
N1I
3v4f
L
|
L ME20
ir 3111-
L 1625
A r23
L W,27
3/40
1
6 IU
-
Figure B-1: Schematic of 20pA Micropower Op Amp with Hybrid Explicit Cascode Compensation (HECC)
99
3;43
IC9
-
L
Me29
3/
7
0
3
I
p
h
a
0
a
i
150-
-0--
S
e
Phase
-90d-
d
e
d
~
-.
B
. . .~.-.-- . .
Gain
-135d-
r
e
e -lO9d-
U
-225d-
II
~~~~~~~~~~~~~~~~~~~~
a-1_
-
.I.,
j
V,
I
L
.J
J
A.
.5
I JJJ
.
5J
L
M
.
L
I
.. L.J
IIU
5
.5
1
-m111W0m,
1
~
l
1 0Hzi
16z11z1
.1
.L*.
.5.
- -K~
-0~
1-
-6~
.LL
..
.A5LL
. .JJ&
..
1.. LL.
.
IU
LIASJ
JJU ... I.JU
1 -H 10 -1z 1406 z
.F..e..u..n..
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I
61.194961
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Figure B-2: Frequency Response with CL=lOOpF and RL=lO0kfl
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Frequency
x
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PhaseMurgn(D(V(OUT)KV(W)-V(L
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507.07923k
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82.68383
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Figure B-3: Frequency Response with CL=O, 10, 100, 200, 500pF and RL=10kfl
101
5
325.27533k:
30.42577
14.65101
Gain
Phase
--- I
I
C
?OuA:HEd
rv
R
V4NB= 0,0.b5,1:..3V1
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VIN
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I. SHZ
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1 OKHz
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Frequency
p
measmeam"t
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PF
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&Auto
I
Measmem"A Resuks
2
1
1
125.523471,
10825M
A
3
9BZ2840
79.10015
106.96550
Figure B4: CMRR vs Frequency with VIN=O, 0.659,1.3V
102
...
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..................
........
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p
s
2CuA HECC
R
R
0'4
[pm= o
CL=100pf
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(V)
----------............ -------------
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186z
I INZ
I.Oz
I @GnHz
I Saft
00((U(UDDA)-U($GUCC))/U(DUT))
I OpHz
0.65
-------I ----------- I .............I
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h1s,
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I 9KHz
1.4mZ
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Frequency
EVAU"
i
17
F
p
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2
1
72-41219
72-473791
me"Womment
jYMVXMW(VDDAYWOLff)), 14M)
?DDA)OV(OUT)), Iaft )
lysm
71-94W i
..........I..--- -----------------
-------------
m m ?K- ------------
Figure B-5: PSRR+ vs Frequency with VIN=O, 0.65,13V
VINB=(
?0 A: HE CQ I P6=60 * CL--1 00pF I
------------ ------------------------ ------------------------------------------- ......................................................
R
R
-------------------------------------
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(V)
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IANZ
I @@MHz
I ftmz
DB(U(VSSR)/(U(EOUT)))
INZ
I.9KNZ
I IM
I MHz
IGUNZ
Frequency
EVAWO
jYGtX(D9(VNSSAW(EOM), I HZ)
jYaIX(OKVSSAW(EOUO), I OkHr)
----- i ------------ I
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------
measuronma
2
1
? 1...............
62.792!
.
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14.343W I
14+2MM I
3
30871L .........
13.67M I
Figure B-6: PSRR- vs Frequency withVIN=0,0.65,13V
103
0.65
----- ............
I.INHz
I lmZ
1.3
I I
:
20uA HECC
. .. . .. .. . .. . .. .. .
.CL-=.tppp
.RL.=
...........
tA.........
--------------
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VINP
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6890
-----------------
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es
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Monewomew Re"s
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p
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Figure B-7: Small-Signal Transient Response with CL=lOOpF and RL=100kfl
I
20uA
HECC ........... ............................. .CL=.[-O.l
------------------
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s
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1
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3
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Figure B-8: Small-Signal Transient Response with CL=O, 10, 100pF and RL=100kfl
104
VINP
VOUT
CL=OpF
VOUT
CAOpF
i
VOUT
CL=1OOpF
--------------
Isus
I *us
--Cl--
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1.3U-
26u
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Time
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Pr
-----------
270MOM
9&WRd&jft9-MffQSMOUT), Su
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FF
Figure B-9: Large-Signal Transient Response with CL=IOOpF and RL=100kfl
I .3V-
41 CL=100 F1
20tiA lf -C PM=60I ......
I.. T ..
I ...
.......
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u
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f ...
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CL=OpF
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CL=lOpF
.......
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I ---
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0
ISUS
29us
25us
3lus
U(OUT)
Tim
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ft*.Ko
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--
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1
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is-"".......
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j9"R*--Fd-M-P(V(OUT), 26U... . 1 ........
i
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....
2
1
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2SOM34k:
S
I
4.40273U 1
2702M71
....
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-------.k ....................
-298.1 S351 k I
....
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Figure B-10: Large-Signal Transient Response with CL=01 10, 100pF and RL=100kil
105
35
........ ....
IWAMMM
MIUMMUM!
II
....
..........
. .......
............
t ---::K:
....... .... ..
2
P
N
I
MMPP': ..
. ....
...
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....
I.-.,
Current in
PMOS
Transistor
---- M2P of
---SM "T- -------- ----IIIIIIIIIIIInTrM
output
Pair
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4103W
Figure B-1 1: Output Transistors Current
aIS
ru
;
;
...........
_x
4
.
...
----...
;
K.M
0
t l.SU_
--------.........
- ----------- ---
e
S.SU-....-_
....
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-------
U(IW)
I IOUs
U(OVT)
......... -------
......... Z.
.............. L....
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N, J_
SOUS
Is
399us
Time
vow
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T))
...........
.......
......
.....
.......
Figure B-12: Rail-to-Rail Output Voltage(VIN and vOuT with Av-=5)
106
VINP
VOUT
.... ...
------- - - ------ ...........
............
-- ---......... ......
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......
----
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... ..........
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A
.........................
...
--------t
--_4 ...
P
0 2.IUt
Current in
NMOS
Transistor
M2N of
output
Pair
L ". ..........
.......
...
.1 -1
lyGtx(_IXWW ).OBMA)
9
M!t .................... ....................
.........
..
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t
p
t
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............ I.......... ........... ........ .....
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W_
.. ........... .........
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U(CUT)
4.50A
4. MA
...............
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SAMA
MOM
Mes"emom
Vd"
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lyd w (OUT). I DNA )
pr
pr
pr
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2,421091
Figure B-13: Positive Output Voltage Swing vs IsougcE
................. ...... ..................
....................
........ ..........................
................................
t
--4-+n'
u
t
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............ o
............. I.....
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U(DUT)
EV&kw*e
17
pr
A-
F7
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-1 SPA
-1.00
m
-8.50A
ILOAD
Moaswenwm
IYGtX(V(OUT), OMA)
IYStX(V(OIJT), -O.SMA)
IY*W((XM. -I.ftA)
--------------
......
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..........
Vdue
21.90152n
91.731 5ft I
..
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...........................
..
.
.....
....
....
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....
............
Figure B-14: Negative Output Voltage Swing vs ISINK
107
-----.......
....
--...
---------------
I
I
& Ab..A
I Is
0
u
R
c
E
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m 4.
2 .5v
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4.5u
S. w
4. ou
3 SU
3. ou
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r ---T *..I...I
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------------------------------- ---
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-------------
--------
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20xA.......................
------- ---- -----
-------6. GU
uucc
Figure B-15: Short-Circuit Source Current vs Supply Voltage
-7-7
I
s
I
I---------------
H
K
...........
.......... 2NP
-------I ....... L.......
I....
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l_
........ u ------- 4..- ------------
--------------- ------------------ -----------------------------..................... .................... .....................
................
-BRA
-------- --------------- ........
----------------12MA
---
..........
--------
-------------------
........
....................
............
..
.....................
........ .................
............
-------- -------............... .
............. .......
-------- ......... ----------- --------- ------------- ---------............ --------
-160A
---- ----------- ......................
- ---------------------------------------- -----------............ ---........
............
................
...
......
1
2.5U
I(UISCH)
3. W
3.5u
4. ou
------------ ----..........
------------- --------........
--- ---.......
-------............
...........
...
........
5.5u
4.5u
uucc
Figure B-16: Short-Circuit Sink Current vs Supply Voftage
108
......
I
6.GU
. . ..... - e...
on
... .....
.
-968-
I
dI
I1 ,44,.,4 ,
..... . .......
-
7--
I
-
...
.~
.n
..
. ..
c.*
..
..
; .... .....
0
- -44-
'4
-
......
Wi
- -
-. - -
-
-135d-
.
. ......
.
FL
. 1 --. ...-
. n
72g
n
5*
+
I
_______
_______
2N6G
-
S-1Sd3-
-
-~i
i
-
-225d-
-27d-315d-
+
-II
1.SUNz
-SOd-
Kx
+.2,44, -- ++
-
-- +
1104z
1 8z
z
1
1H.z
':
-+4+* 4 -w 4+...
+
4
- +
44x
++
1.M32
1 @Hz
1WHz
- DH(U(DUT)/(U(IW)-U(IM)))
*--
1800z
111HNz
1 .WHz
11Nz
[1
.P(U(OUT)/(U(IW)-U(I13)))
[.{
4
-- +H
44b44
-+
IL
Frequency
naM.
52.89484k
87 1235i
(..
)
PhwsIMvg4(D((OUT)4V(-V4*
28
85 2589 I
.Zi 0 P d.
......
2451847
87.18727
27.492 ...... .ve~e
183.
5
3 8
03
_S.1M
53 81927k
8878815
5..9....k 1
529.42157k
.
-1.0
1!!4 3 9_
k
.i
262Pid
Pie..L d-_ --j'...... ..*d
.v , w....
26.1706
.
77
2..
.7
a
a
..
....
Gain
-0.5
.........
k 1., 4121
...
.......
-U-
Phase
8877888
Figure B-17: Frequency Response with CL=OpF and RL=100ka @ IL=-1.0, -0.5, 0.0,0.5, 1.OmA
h
Symbol
(mA)
:I:'&
AWn
-45d
S
S
e
9
-9d
B
-135d
)
44 -
1 -18Wd-
4
-
4
.-4-44-
*4*-
4444:
4 -
-
-
4.4-4 -
-
-4-
-_444
*
-
* 4-
44*".
4-5*
-4
- *
'
*
- *
------
*
-
--.
Gain
-4
-44
4--
[ 0.0
-225d
-~
--4
-~"MM
F.5
-27Wd
-36Wd194I2
1.WI~z
[I]I
.
10In4z 1.
P(U(SUT)/(U(
1Hz
03(U(SUT)/(9(IW)
^
1334Hz
1332
1.3hz
1666Hz
166Hz
1.5Hz
161Hz
11Hz
I)- (9(1))) I I
Phase
)-(913)))
Frequencp
MI.-_
M( OU)(J )-V
r)-
h
O
.
OUn
90.249128
86.942[
I
~VrV
98.4758
4EV d24.93W4
)
540.221214
21.11787
22.h7337
Sd
d-
g
. IL.O, -0.5, 0.0, 0.5, 1.OmA
230-+*+4 --
+X-1
-45d-
so- -+ ++t -+i18
-
-.-
e-1368
H;4-4
--
+-MM
-- 4 t
-- f-f
+H
+!HM +++E-
...
. .... ........
ii
p -135d-
--
++-
M --
.-
An 1se- -++HM!++~
(
23A9443
1EvgjmFaud
n,
Evu
Gain-
2.285.
885245
EVS4Id*OPF**s
1.0
I
1
53182.2.3
773
22.V=
)-I.82024
(
4
S
Iall s em
__
0 529.23750k
Figure B-18: Frequency Response with CL=1OpF and RL"100kfl
..
..
...
m+
-+-+u
++t
++m.-
i+Ht -+ ++o -+ +9 -
sg-sw:--+n:+H~-+
tit ++
+t
-
++s
-++2
+
4H
t
-225d_27W-_
-315d
-
6
Gain
Phase
Gain
-315d
a
s
Phase
-4
-*
-
I
9d=
-1
> -+ -1
-
4
laz
1.8'z
M88IOE@1MO
-
12!nOrgn(P
V(OIR
)
i
)) )
Eva84n4~
1.34Hz
IIN3Z
H
1
IHz
DB(UVT)/(U(I)-U(qn)))
3
55J73~
7
1
V(H)
.
111HZ
+
-
-++4
Frequtncp
533 871
Zeors(iVOTO P-(~l 5314438
_)
1ONz
1.MNz
163z
.+P(V:0UT)/(U(:W)-U(IMi)))
Evdi
--+
+-X
_____-+__--+__-+___+H__-++4__+4:-+Hx
lI z 1-mz
1.Uiz
-+-
--+X-
*-+H4-
2
---+-4
44 ---4 -+4 --- :-+4
-+
24.8842
._
4
54325~
811849
4 84441811
)84.68-
8430372
4
'-
_.121
5_VI
Fi.a
12323
.Evi'a
17_2973
nfilled. 4
S
4434
4
1499323
15M021
--
Figure B-19: Frequency Response with CL=100pF and RL=100kl @ Ik=-1.0, -0.5, 0.0,0.5, 1.OmA
109
4 03nA(@
011 DSN
IREF
Bias Voltages Setter
Start-Up Circuit
VSUP=2.WV)
4.D3nA
c
0.197uA
4.17nA
Reference Current to Op Amp
Generator
0.197uA
0.197uA
0.192uA
MEl
*,
1014C
L
0. 197uA
3I
1C40
ME
10/ L
10140
A
,1C
101
1117 L
wL
WC
-, 14
fl~t1
Maic
Lu1/l
I
ME3L
L 20
F
WS4 L
2A7
1.77
LIM35
2/10
GNO/
----
GN6
I
*ti 2-
-BI
0:63t
INL
Lj *
16;1 F
C
PE
Figure B-20: Schematic of Bias Cell for 20pA Micropower Op Amp with Hybrid Explicit Cascode Compensation (HECC)
110
1.6 U_
1.
I - --
-- - --- -I
- - - ---- - - - - - - - - - - -
---------------
A - --
---- -- -- -- --
- - - - - - - - I- - - - - - - -
- - - - - - - - I- - - - - - - - - - - - -
T - - - - - - - ---- - - - - - - r
IM
lr--
VNCASCODIEB
- -- -- -- -
- - -----------
--------------------I -- -- -- --
I - -- -- -- - --- -- - --T
- - - - - - - - r - - - - - - - --- - - -i-- - - - - - -
- - - - - - - - - -'-l
- --
VKASCODEB
Reference
Voltage for
PMOS
Cascode
Transistors
- -- -- -- -- -- -- -- - - - - - - - - --- - - *- - - - ---- - -
I - - - - - - - - - - - - - __.,
-- -- -- --- - -
-- -
aA___j ----------- L ---A ---- ---------------- L --........................ --------------
- -- - --- -- -- -T
- -- -- --r
4. su
4. lu
3.5U
3. ou
ID(MM11) * -ID(HSTARTUPREF-M2)
v -- -
5. ou
----- - ------- - 6-OU
- - - - -- - - r - - - T - - - --
SAU
Me
0%
Resuka
EVakUgt*
Z LI
I
vam
IYAWAD(MM81
I 5V)
1). 26.OV)
Y&VWMW 1)
197
.
FF
17
1
w
0
i
pr
-
lYdM WTARTLPREF MS2),2."
YaOMMSTARTUPREF MS2), 6.9
YGtX,(V(NCASCODE9), 2.5V)
1Y*WMASCOM), 6.OV)
YatXM$OYCC)-V(PCASCODEB), 2.
jYatX(V($GYCC)-V(PCASCODE8). 6-OV)
I
7nl
- - - -- - - - - -
I
I
Reference
Voltage for
NMOS
Cascode
Transistors
Vw-
--- I ------------- L --- I
- - - 1- - - - - - - -
o
11
---11 ---J....
-------- L --11
&---j------------- L---A--------------- ----- -------------------6;j
r
- - - -- - - - - - - - - - - -
0
---------I - - -
a -- -
TOP
__O_
.1
---- -- -- --
a
29@nA--a
8A A
2. SU
j -- -- -- -- --- -L
I -- -- -- -- ---
J -- -
-------------------- -----------
r--- 4---!SEL>> ----1.2U
,zU(tCASCODEB) * U0GUCC)-U(PCASCODEB)
40§nA.1
.--r - --T
I -- -- -- -- --- -r
I ---------------r -- -- -- -- -- -- -- -- -- -- L
11
--- -- -- - --- - -- --- -- - --- -- -- - --- - -r --- - -- --- -- -
-- - --- -r -- -T
T - - - ---- - ----
- - - - - - - - --- - - - - - - - - - - ---- - - - - - - r
I
....
......... ...
.....................
....... ....... ....... ...... --
III
IMB11
Reference
Current of the
.-.......... . ..................... ...... . ........ ...... ....... ...
199.90350n
.......................... ...... ..- -.................... ...............
.........................
..........
......
.02927n
............
....
..........
.........
- ............ ...
-329.021 " n
......... ................. ...
...
. ...... ...... ......... . .......
. ................ ....... .
......- -.......... ............ ..
1.352401
............. ..
......... ...........................................................................................
..........
...........
......
...
....
.
. .......................................
...
............. .............
1.45911
........ ......
............... ....
....... ............
.................................. .......................... ........-__....._.- .............. .................
.............
....
...
1.46M i
Figure B-21: Reference Current and Reference Voltages vs Supply Voltage
.---- BMom
__O_
.IDMS2
Current in
Transistor
MS2 in StartUp Circuit
I Uum-
------------
------ - --- -L
-- 0-
- -- --------- -r- -- -- ------ ----- -- -- --- -- - --- -- -- -- -- --- -- -- - -- -- --
- -- -- -- --- -- -- -- -- -- ----- - -- --
IDWP
I- - - I
-- -- -- -- r
- -- -- -- - r - -- T
I - - - - - - - - - - - - - - - - - - - - --- - - --- - - - - - - - - - - - - - - - - - - - - - - - - - - - - I- - - -
-- - T
J - - - --- - - - - - - - L - - - - - - -
- -- - --- -- .. . ... .
- -- -- -- - L
- - - - - - - - - - - - -- - - -
.. . . . - - - - - - - - - - - -
L- - -
Quiescent
Current in
- - - - - - - - r
- - - --- - - - - - - - L
A - - -
uA-
PMOS
-- ------ ----- ----- - --- ------ I- -- ----- ----- T - -- --- ----- -- -- -- -- ------ ----- ----- -- -- ----- -T -- ----- ------ - --- ----- -T- - ------ ----- - --- -L -- -I -- --I--- -- ----- -- --- ----- -- -- -- --- - -- -- -- -- -- -- -- - -- -- -- -- --- - -- - --- -- -- -- -- -- -- -- -- -- --- -- -- -- -- --- -- -- -- -- -- - -- --- - --- -- -- -- -- --
-- -- -- --- -- -- -- -- -- -- -- -- -- --
------------------------------------------------------------------- T ---------------- r
Transistor
M2P of
Output Pair
- - -- --- -- -- -- -- -- -- --- - --
------------------------------------ - -- -- --- -- -I -- ----- ----- --
@Ar ------------- ---------r ------------ -------------------------------- r --I --I ---I-------------I --I ----------- r --I ---I -------------------
---- -------------------------------------
--------------------- --------------------- ---
IMAM
Quiescent
Current in
NMOS
Transistor
M2N of
Output Pair
17
---------------
- -- -- -- -i - -- ----- -- -- -- -- -- -- T- -- ----- -- -- -- --- r - -- T - -- --------- -- -- -- --
- - -T --- ----- ----- --- - - -- -- T- -- ----- 7 --- ----- ----- - --- ---
-5uA ----------- 2-----------------L
-------i ---j ----- - -- --- -- -- -- -- --- -- -- -- - --- -L
-- ----- -- --- - -- -- -- -
r
I ....I----t-----
--------
------------ --------------
I - -- -- -- -- -- - --- --- -- I- -- -- -- -- -- - --- -
- -- - --- -
- -- - --- -r- - -T- -- ----- ----- ... .. .. j - -- ----- - -- - --- -- -- --- -- -- -- ----- - --- -- -- - - - ------ -- -- - --- ----- ------ -- -- -
- -- - --- -
I-
r -- -T
i -- --- -r
T -- -
- -- - --- -r -- -- --- -- -- 13
4. ou
5 . ou
S.SU
6 . OU
UUCC
Meastwenuft Resuls
Evaksde
pr
p
FF
TF
measmemerd
YatX(K)(MM2P), 2.5V)
jYadX(ID(MM2P), 6.OY)
dXMWM). 2.5V)
IYatX(K)(W#M4),6j0V)
YatX(D(MMOI 7),2.SV)
jY8dX(D(MW 7), 6..0V)
.
.
IDMB17
93
-1 OUA
2.5U
3 . ou
3 SU
n ID(MM2P) * ID(MM2H) v ID(MMB17)
Quiescent
Tail Current
of Differential
Input Pak in
Biasing
Transistor
I
MB17
Vakto
-8.31879u
.....
.....
........................ .....
......
.......
..........
......
....
......
...
...........................
-9.91 346u I
......
....
..............
..................................
.........
.......
...... .
......
.......
8.31852u ...
...................
................
.......... .....
.................
.......
.......
.......
......
.......
........
.....
. ......
........
.........
.................
.......
.......
.........
.........................
......................
...............
.......
9.91404u I
I .......
...
........
..........
.......
.......
........
....I....
.......
..........
.....
.........
........
.............................. ........
-1.973&5u:
T
......................... .......................... .....
.................. ....... ....... ......... ....... ....... ................................ ...
Figure B-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair vs Supply Voltage
112
Appendix C Schematics and Characteristics of
20pA Micropower Op Amp with Hybrid
Symmetric Embedded Cascode Compensation
(HSECC)
LIST OF FIGURES IN APPENDIX C
Table C: Characteristics of 20pA Micropower Op Amp with Hybrid Symmetric
Embedded Compensation (HSECC) from Simulation.......................................115
Figure C-1: Schematic of 20pLA Micropower Op Amp with Hybrid Symmetric Embedded
Cascode Compensation (H SECC) ..........................................................................
Figure C-2: Frequency Response with CL=IO0pF and RL= 100k-------------..............----
117
- 118
Figure C-3: Frequency Response with CL=0, 10, 100, 200, 500pF and RL= 100k.-----.119
Figure C-4: CMRR vs Frequency with VIN=O, 0.65, 1.3V .............................................
120
Figure C-5: PSRR+ vs Frequency with VN=0, 0.65, 1.3V.............................................
121
Figure C-6: PSRR- vs Frequency with VIN0, 0.65, 1.3V .............................................
121
k.......
-122
Figure C-7: Small-Signal Transient Response with CL=100pF and RL= 100
Figure C-8: Small-Signal Transient Response with CL=0, 10, 1OOpF and RL= 100k .. 122
Figure C-9: Large-Signal Transient Response with CL=100pF and RL=1OOk ......... 123
Figure C-10: Large-Signal Transient Response with CL=0, 10, 1OOpF and RL= IOOk
Figure C- 11: Output Transistors Current vs ILOAD -------
----
123
----......................................---- 124
Figure C-12: Rail-to-Rail Output Voltage (vm and VOUT with Av=5)............................
124
Figure C- 13: Positive Output Voltage Swing vs ISOURCE----------------................................
125
Figure C-14: Negative Output Voltage Swing vs ISINK
...........----.................................
125
Figure C-15: Short-Circuit Source Current vs Supply Voltage......................................
126
Figure C-16: Short-Circuit Sink Current vs Supply Voltage..........................................
126
113
Figure C-17: Frequency Response with CL=OpF and RL=I00kK2 @ I=-1.0, -0.5, 0.0, 0.5,
1.0m A ......................................................................................................................
12 7
Figure C-18: Frequency Response with CL=IOpF and RL=lI0kQ @ IL=-1.0, -0.5, 0.0,
0 .5 , 1.0mA ...............................................................................................................
12 7
Figure C-19: Frequency Response with CL=lO0pF and RL=1k00M @ IL=-1.0, -0.5, 0.0,
0 .5 , 1.0mA ...............................................................................................................
12 7
Figure C-20: Schematic of Bias Cell for 20A Micropower Op Amp with Hybrid
Symmetric Embedded Cascode Compensation (HSECC)......................................
Figure C-21: Reference Current and Reference Voltages vs Supply Voltage................
128
129
Figure C-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair
vs Supply V oltage ...................................................................................................
114
130
Table C: Characteristics of 20pA Micropower Op Amp with Hybrid
Symmetric Embedded Compensation (HSECC) from Simulation
0
Simulation results are at 25 C.
VDD
=
2.5V and Vss = OV.
Primary Characteristics
Value
Condition
Symbol
Parameter
GBW 22
Gain Bandwidth Product
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
is
Supply Current
0.3
0.617
(0m =60.6*)
CL = IOOpF
RL = 100W
>100
123
dB
No Load
<21
1943
pA
CL = I 00pF
100W
RL =
>
VOS2 4
(Untrimmed) Input Offset Voltage
=
0.65V
High Output Voltage
ISOURCE =I .0mA
VOUTL
Low Output Voltage
'SINK =
I.OmA
ISOURCE25
Output Source Current
CL = I00pF
'SINK
Output Sink Current
L P>
RL= 100kW
RL = 100W
MHz
1.3
mul lachis
and includesy
negaive supply
negative supply
VOUTH
VOUT
V
ul
-ngati
VINCM
25
and must include
-
Input Common-Mode Range
Simulated
Specified
> VDD -1.
VINCM 2 3
Unit
_.--...---....
voltage
voltw
<5
417
mV
> VDD -
0.3V
2.34
V
< Vss +
0.3V
0.19
V
1.0
1.55
mA
1.0
1.4
mA
>
Secondary Characteristics
Value
Symbol
Parameter
SR+
Positive Going Slew Rate
SR-
Negative Going Slew Rate
Condition
Av= IV/V, IV
Specfed
I Specified
S____
_ted
Unit
Simulated]
> 0.15
0.254
V/ps
< -0.15
-0.269
V/ps
Step
Av= IV/V, 1V
Step
Gain bandwidth product per supply current GBW/ Is= 31.8MHz/mA @ CL = IOOpF.
Verified by CMRR simulation in Figure C-4.
24 Conservative estimate from calculation.
25
Maximum output source current is measured when the other transistor in the output pair starts to turn off,
i.e. its current goes down to as low as 1pA.
22
23
115
CMRR
Common Mode Rejection Ratio
@ DC
> 60
147
dB
PSRR+
Positive Power Supply Rejection
Ratio
@ DC
> 60
S.
dB
Negative Power Supply Rejection
Ratio
@ DC
@C>0103
> 60
PSRRt
0.1% Settling Time
Av= IV/V, IV
Step
116
< 10
dB
12<t,<20
ps
0.A93oA
I
Ti4-
T
L,
193uA
1.93uA
0 193uA
1.93uA
0 193uA
0.193uA
0.3uA
1.92uA
1.5BuA
1
8.25uA
~
I
*0
T
L
1-t40
10,4C
10/43
0
L
'CE
L440 6 La
Wr0o
PCASOOBy
L
!
A-'
' cc
1
402-i I
lk0/1
4(12
L-
3fl
I
-
I
INP
VE07
I IN
M12C
l r%13 t
FT
L
2NG
M
K414
r
I
0
I-,'-
M'12
L
CAcfDr 3/17
W21 L
C-4 r
314C
I,,22
Al4l
4919 L
3/40
340
L
L MBZ3
3/40
MN2,
340
T
1r
4
-M
325
_ [~
S(3
5"T
Figure C-1: Schematic of 20pA Micropower Op Amp with Hybrid Symmetric Embedded Cascode Compensation (HSECC)
117
-t
M
5'0
a
----
-----------------------------..
d~-
iT:.
Phase....
------------
ai
.. .. . ..
-2 d
.. .. . .. .
.. . .. . . . . ..
..
-271
1 lot,
LIJ
135d-i
-J
JJ
LL
LL
JJ
U
.5IUII.
JII
--
J~
isLI
I
I.
I I JI I.,
...
I
I I to$#,
I
JGain
I
~Zors((U)VNVH.I
TL
I
LIII
kIAIUL.
-3Ills-I
p
I
----
66937
IL IL
ILI,
~ ~ Fgr CLA--A-A-: Frqec
......
.......
L- -
---
Response with CL-lOAp
118
an
RLO k
\90632
LWL
-&.J
- 6:%--ul
I
I oLAL
Sd-
p
a
a
i
n
S
API)-
280-
C
h
-----...---
e
d
..... , , .... . . ..... . , ..
d
e _135d-
9 r
CL
Symbol
0
-0Phase
.....
. ........
10
--
e
..
Phase
-I %- ....A- - - - A
--
J.Jl
.IM
-
I
-
A u
Gain
1 -11 --- --
-.
.I
w
..........J
~
u
-.
-
-
uu
-
.
-L
J
u
,
.-
&
...
-225daaa ea e a a~sa a a a ea taasat.s e aa e a a ea sa
a a ea s sa
a
a e sa
a
a ase
e - a ame
.160
e a a ase~a
.
Gain
"...-L
I L
100
Phase
a a a .
-279d-
Gain
-315d-
Phase
-36Sd1.80z
Ewsku*t*
p
__
ImHz
OD U * v
1.3Hz
1Hz
113mHz
* P(U(OUT)/(U(INP)-U(IHH)))
8easurmnt
zerOCrOLk(D 8
((U)V(-
)-V(MN...
PhawMrgn(DB(V(OUT)XV((W)-V(l
1
566.99779k
9177091
15Hz
(I
x
Measurenm
2
1KHz
1.UMUz
1.5KHz
15Hz
* DB(U(UT)/(U(IHP)-U(INM)))
Frequency
131hz 16MHz
Gain
A
500
ntemi
3
616.94367k
60.5874i
579.10957k
88.97918i
534.45336k
4415234;
8.58531
14.54808!
9.06325!
20.68351
P' ain~r(P(V(OUT)(V(WP)-V(E)...
Figure C-3: Frequency Response with CL=O, 10, 100, 200, 500pF and RL=10kfl
119
Phase
6
4
37225664k1
30.124241
.399
Gain
C
m
R
R
----------------------------- -----: I- -- L ----------1 j3VI
5,-----------I
"
VIIIB=[OOq
CL410
20tiA
HtECC
IPM460
---------------------------------------------- ----- ------------------------ - - - -
-
------------------
VIN
m
------------ ----------- ------------------------ ----- ------------ -- ------------ ------------- ----- ----------- -----------------------d
B
----------------
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I OGMZ
I @MHz
1. @Mz
c * v DB(U(CM)/U(OUT))
I.Niz
1 Niz
L -------
-------------------
I. OKHz
I OKHz
I OOKHz
-----
-----
-----
I . vMz
I @Mz
------------ ----------------
------
I olMz
Frequency
A
Meastweniat Rest*s
EvakWe
lYatX(DB(V(CM)IV(OIJT)), i.OHz)
pr
YaiX(DO(V(CM)JV(OUT)), I OkHz)
------ -----
----------- ------------------ -----
-----
I Offiz
----------- ------
------------
------
-----------
-------- ------
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1
iol.sm
2
1
3
lillQiOl
146.746401:
...............
......
...
71.84682
1002171ll
Figure C4: CMRR vs Frequency with VIN=O, 0.659 1.3V
120
--------------
1
SH
-0-
..............
lzi
q;lAt,(3uanbaiA
AVI '59*0'0="'A
1696 Z*cc
QMVK
. ................
..
....... ..........
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1
t
SA
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4
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d
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L
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ZHUOU
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p
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mA
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K= ... IMM I.
------------------
dOT=I:), 0 OV=Wd
=8 IA
Rl
SH tMOZ
rrul
F7.
s
I
d
ICL=100PF
............. ..........
20uA:HSE(.C
-----------EPM=60
:------
-------------------
I
,-
-r-
79ANU .
I
CL=
:9
I
VINP
IL=dMA
----------- ------
VOUT
---------------- ----------------------
------ - --------------------------------- ------ -------------------
....... ...
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----------- ------ : ------------ ........ ..
-----------
L ........... ......
-----------------
....
.......
----------- ------
I...............
----------- -----
I------ ..... .....
-----------
690mu........................
----------- -----
-----
I
----29us
Isus
1 @us
U(OUT)
Time
vow
evomao
W
I------ -----
------
5us
U(IW)
......I ------I -----------
----------- ------ ................... ........... ......I -----------------
-----------------------------
es
-.Ar-
---- --------------------.....
----- ----- ----------- ------ ----------- "--------- --------- ------ ------------------ I- -------------------- -----------
----------------- -----
560MV
-n-
i"Nut
I
ISetOmTkMXRWO&rV(OUn.O.i.S.Ou$.I&nI
Figure C-7: Small-Signal Transient Response with CL=lOOpF and RL=100kfl
I
-
=.(O J-I
IPM=60 a ICL=100P
20uA:HSEI,C
. .................I ......I ..... 'CL
.....
------------.....1_90k
-----------
RL=
- - -- - -- -- -- - -- -- - -- - -- I --
---
--
--
-
-0-
VINP
----------
69 emu -
---
. .. ... .. .. . .. .. .
- -- - -
- - -
-
-
- -
-
-- -- -- - -- -- - -- -- -
. .. . .. .. .. . .. .. ..
. .. .. . .. .. .. . .. . .. .. .. . .. .. . .. .. .
. . .. .. .. . .. .. .. .
. .. ..
........... ------------
.................... -----
----------------
. .. . .. .. .. .. . .. .. . .. .. .
I-- - -- -
v .. . .. r. -- -- -- - -- -- - -- -- -
VOUT
CL=OpF
. . .. .. .. .. . .. .. .. . .. .. . .. .. . .. .. .
I ..... . ...
----------- ------
----- --
-----------
-----
--
-----------
VOUT
-----------
-----
-----------
CL=lOpF
emu --------------------------------- ............. I------ I------ ----................. ...................................
. ................ ...................................
....
----- ------------------L ...... I -------------------------------56 INU +
85
U(IW)
Sus
U(OUT)
29us
Isus
I ous
Tim
MWOMOMatrasuft
Evehow
M***w*nm*
1
2
1
1
1.01MUE
1.80475U I
1.81 2*u i
I 1W Isoff"Tko )(Rwxwv(OUT). 0.1. S.. 1
Figure C-8: Small-Signal Transient Response with CL=01 10, 100plF and RL=100kfl
122
VOUT
CL=100pF
I
r-T.-
20u
.. . .. .
.. .
-0-
8SECC: IM40 ;9 ftilOOP ] i
.. . .. ..
.. .... .
. . . .. .
. . . ...
VINP
A
- - - -- -
-- - -- -- - --- ---
-I&VOUT
......
-- 4 ------ ---------
-i ---i--
--......
------------------
........
... .... 1---
.. ----------
...... I...
CH
..........
..... ......
. . .. .. .
Sus
Is
U(IW)
. .. .. .. . ..
20us
ISUS
I @us
351
Hus
2 us
& VOUT)
Tim
I
I
EVAW*
W
ISSMVTWW
F
WdW
I
MWxWWWnjo.I.Su
ISWMWejdXftnpMOUT). 25u-.-
436363U i
-----
2W.OiWn:T
I
Figure C-9: Large-Signal Transient Response with CL=lOOpF and RL=100kfl
I I . I
4 all
200 8SE -C: IP41=60
I
-- 0-
VINP
. ..
........
... ........
- -- - -- ---- -- -- -
I. . .A . .. .. .
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-- ---- -
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---
---
----------------------
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. ..... .. . .. .. .. ...
------ - - -- -
VOUT
- - - ---
CL=OpF
-- -f - -- -- ---- -- T - -- - -- -I- --
9.5u.
.................. ...........
--------------- -..........
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--------------
... ......
------
------
VOUT
......
.............. .....................................
...................
--- ---------
CL=lOpF
......
--------------------------
i
I .......
VOUT
I
ou-L
85
1 @us
5US
U(IMP)
ISus
35t
3ius
25US
28us
U(OUT)
Tim
FF
ror
IS-ftvTft-MffQKv(oM, 0.1. Su...
IS*w"eJ'd--Xftr9eKWOM. Su."
jSewR@te-FdXRWVe(V(OUT), 25u. -
4 0 54SU!
4.41423U
4
.....
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....
....
..
. ...
------
-271.35MM
-270.568M
-2MM3M
Figure C-10: Large-Signal Transient Response with CL=01 10, IOOpF and RL=100kfl
123
CL=100pF
.... .
............................
w..
........ lM!j3m*m!j5!!!r!........
-U-
...........
D
........
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. .. . ....
... ... .........
N
IOWA-
2
P
i SUA-
Im! Im!pm !"M
PT
-------HIMEM!
Ul
M MH
:::*
..............................
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1 . OUR-
....
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ID(MMM)
DOW)
................
MMMIHMM
I
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...
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................ ...
-:::
-------------...........
,
.
I
3. &A
2. SPA
i WA
w
V4kW
Figure C-1 1: Output Transistors Current vs
..............
..............
....
tU 2.W-
---------------------------------------
0
..
. . . . . ......
. .*.
. .....
..............
......
. .
.....
VOUT
........... .... ............
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....... .............. . . ..
.......
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--------... ....
....
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I lu-
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Slus
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I IOUs
.........
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286us
15SUS
....
....
.......
...
....
....
25 Sus
39SUS
Time
vam
P
...................
..........I .....I ....
L
... ....... ......
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---------
------------------- - ----------------....... .................. ....
.........
....
....
....
....
U(OUT)
KM0LFF))
Imin YOM )
...
- .............
..........
U(IW)
.......
...
--- -- --- ----
won"Ilt meows
48M3
0.43M M
............
Figure C-12: Rail-to-Rail Output Voltage(VINandVOUTwith Av 5)
124
VINP
........ \ .
.............. ....
........
.. .
t
lLoAD
..................... .. ....
....................
.... .... ...
a
9
e
lDM2N
Current in
NMOS
Transistor
M2N of
output
Pair
.....
..
....
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....... ......
...
..
. ........ ..........
....
....
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7 1
:
..
....
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...
...
...... . ..........
.............
...
.
.....
....
.........
. ......
.....
.........
........
9 ru
......
PMOS
Transistor
M2P of
output
Pair
...
...........
....
. ...........
.......
...
.......
...........
2360Ui
8.1 235W 1
Yllm -O(W AV). O.OMA)
, Onm)
Ydx(
YOM4>04W), O.W)
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bMA)
.lDWP
Current in
!!!IITM
. ....
----------- ------------------
..........
--------
ILOAD
M"*Wemom
or
HMM
............
.
............. IMMIT!,
. ......... ............................ ....
ISPA-3. @M
......................
7TII 111141!!" H
.. ..................
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3
TM
p:.3
....
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MI
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7
2 I.Gnhm
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D
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3-ou,
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p
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t
--------
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W-
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F
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F
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0.50
4. "A
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i
-- '-i42W
2
IYWMOUT),OrrA)
ly"MOUT), 0.10")
lyamwoLm. I
i#.W - : .I I
. .I
----------------
Figure C-13: Positiv e Output Voltage Swing vs lsojjRrE
. I
I : :
(PEI:
C;,
I
............... : : : : ..... ..
...........
......
....................
.......
-. 1-----...... 1....................... ... ................
..........
--------
T
..........
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. . . .
....................
t
S. GmA
4 SPA
ROAD
--p
U
----------- ............?:
t 3. IN U
9
3. INA
2 SrA
2 IWA
U(OUT)
........... L
..............
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2.@U-
................................. .........................
...........
........
........ ..........
...........
.........
.....
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-5. W
- U(BUT)
-4.80
-3.'SPA
-3.'@M
M"m
M*40wenmvt
FwaksWo
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17
17
lyotx(v(ouT), -I.*")
Figure
......
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.....
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ILOAD
?A*%"
-2. GM
-1.5,A
-1.80A
-6.5VA
0
A
vakm
.........
...........
...
..........
.......
......
.-.......
................................
..
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....
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...
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....
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- -----'I*l
I
j- 11111-1"1..
........
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...
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...
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.....
........
........
.........
.....
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........
.'..............
:4645ft
- ---C-14: Negative Output Voltage Swing vs ISINK
125
.
A. A.'a
r-
I
s
0
U
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C
E
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.
.
.
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a
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OUA MSE :C :[PM=F)O *:CL
..................
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--------
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-------
A
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.
....... ......
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........................
------------------------------------................................. ............... ....... -. ---. . . .
. . . .
.
. -----------.........
------------ -------............ ----------------
I
- I
2.5U
1 I (U I SCH)
3. w
6. OU
5.5U
5. OU
3.5U
UUCC
Figure C-15: Short-Circuit Source Current vs Supply Voltage
I
s
I
SE( :C iM=6
OLJA
iCL;
0
L
A
I ....
..............
H
K
L.........
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--------
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-----------
................
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2.5U
-, I(UISCN)
................
....... -------- -------
--- ----------
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-------
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3. su
B.SU
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.................... . ................
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L ... A --- I--- I
-------
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I ---I---7- 1.........I --1 ...
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------------
----------------- ...I...
---------I ---I ---
....................
4.5U
4.m
...... ......... ....... ......... ...
-
---------
5. su
UUCC
Figure C-16: Short-Circuit Sink Current vs Supply Voltage
126
----
--------
5.5v
6. lu
a
I
_______
68
4
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2116
a
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n
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H
----
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1
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1.MHz
IPJ
571.27932k
16 6-.. . .
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(1A)
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2.39'M1
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EvodanFm89.
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5621mTk
26.09727*
samas ...
23.9014
66Fa0- d
.
a
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5
n
d
8
299 .
9-18
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---
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----
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---
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---
r -135d-
: :
-FE.---
-ffJ
-9-:At
Symbol
_10
94B4M
2374197
Ev'iak dFab4
1
Figure C-17: Frequency Response with CLOpF and RL=100kil @ IL=- .O, -0.5, 0.0,0.5,
k(DB(MOUT)V()-v())),1)
I0 9"z
1I~z
1.Mlez
0(U(CUT)/(U(IWL)-U(IM0)))
596.997196
344103
Fals&
I GUNZ
1sjuz
-- ;
-1hz
4 4.
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( -..-1- X -l-) -- ----- IW
...-.- --I A 1, ---- - - - - - -- - -- --- - --
X
-
2
OUT)V(W)-VO9
-Evadon
~-NI
-+z
4
-
2
574.994444
1
7319991
I
11k
D
Frequency
-
-
7:
- -
- -- --
1 uz
I W .
1SANZ
P(U(CUT)/(U(lIW)-U(IMC)))
ZWOOOBSP"...
usmln J
mlEaU
Phas...
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.
-
li
S. .
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+
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1Hz-i
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8
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mit-
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Phase
- -IMII
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Gain
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i
-- 41
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1
-- i,4-
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Mz
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14KRZ
1.GKNZ
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1.Miz
D(U(OUT)/(V(IWf)-U(IM@)))
- 09
P(V(OUT)/(U(lIH)-U(IM1)))
.
Phase
19"2z
Frequency
I Evdate
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Maewua
p
.
evOUmv
v
I
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2
575012
31.SI1521
4
FdS
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t
14.5M
30.74409 1
iOn
So
1
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994.0241k|
1.0
21.3037
2DA3354
Phase
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.EvkjdianFd.n
Eve.ianeds
dal
Gain
4
2
579.10967k
99.17919
9.2.43196m
1 0
Figure C-18: Frequency Response with CL=10pF and Rl=100kf @ IL=- . , -0.5, 0.0, 0.5, 1.OmA
299
od,
h
aa
5
C
-45d-
n
-98-
d
- +
.-q-
1-- 'A
:i
q:2:i!!:4
<:.
|N
:
-----
+: -444
-4 444 -- 4-
0.,P~ [-- e9=)
-+
ax
+4
- -- + H4 4 - Md - +4 "44 --- 11
--- +411 +4 ...-
+
14-44-
+:+:N:
9
----"
......
-- it..
~ ~ ~ ....
~
150 ~
e -135d9
r
*,1-
-:+.+......
-
.
"
4;3 .. . .
4 -
41 4
IIV
-4-
-
-
e -198 -
--
- -+
-- -
-225d-
-
-
-
-
-315d-
-M.-
1.&lz
M -- M-N
--
1ooz
P.us.we~(0w
(vOUT)(WP)-VQ~
Peah(DE(OUT)(Y)v),
,
: -+-:+11
x
-+
-
H t
-
-,t
.
199HZ
2
___
l1.1417
*evsluwmnFww&
EvalmFit
1599Z
4
1247%
~
1UIz
1.Uz
1MHz
bo(V(UT)/(U(IW)-U(INM)))
Frequency
A
p anagnPvOT((P-(0).
1)
1-IAHZ
1669z
[2]
1
Zeross(Cv(OUTP)-v(i
---+
........
1l6z
1.9z
1I oz
P(U(OUT)/(U(lIw)-U(Ilh)))
Evasu
- Hlx -
-- - -N
+nxt -+ mtim 0 E
. -.
-> ..
-36W3-
-- :+H
11-41
-
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14
.....N,---i-x---m"
-
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;is
8i
6199327k
d J 9O9W
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dEvkaban F8&
33275s
k
_2243
1174109
Fdc
9274014
_
.EvaFl
_
1_986{
FdI
Figure C-19: Frequency Response with CL=100pF and RL=100kfl @ IL=-l., -0.5, 0.0, 0.5, 1.OmA
127
Gain
- -
-
Bias Voltages Setter
Start-Up Circuit
W3nA@ vDD=25V
STARTUPR Yf
60,2
1!1()C
403nA
M KO
2 1,100
417nA
SIN
1OO
MS
1193uA
I I
_______
_____
Mb
10.'0
1011 L
0 193uA
I I
_________
1
1/16
Reference Current to Op Amp
IREF Generator
0.1uA
S
1B:
L
0 193uA
H
0 193uA
10I,40
'1
I
'1"
-FCASCODEB
-
CI
01
ID-
11
WC
NO
L 2120
ST ARTUPO :F v i
WS4 L
211C
GNUC
L M35
:2/IL
NCI
ME3
ND
L
_1~~1
IL
N-CASCCOEB
L0
2
R6
210
ND
IE n
i
Figure C-20: Schematic of Bias Cell for 20pA Micropower Op Amp with Hybrid Symmetric Embedded Cascode Compensation (HSECC)
128
I
1.6U-
I
I
I ------------I
I ------I
I
-----------... ...
........---
I
.
TOP
-- 0-
I
I
I
I
I ------I I -------------I
-------------------------------- ----------------------------------------------------I ---------------- L ---L --a -- -.j ------------------- --I --...-------------L ----------------------L .-- A --- ,j -------------.........
VNCASCOOEB
I .4U_
- ------------ --------------- -- --- ---------------a------------- --------------------- ------- --------------------------------------------- ---------------------------------------------- ---- ------------------------------- ------------ -------------------- -------------------- --------------I
I -------------I
I
------11
---I
-------11
-.1
--I
I
--------------- k ------- l ----------------------------------L ------- I ---SEL>> ------------1 .2U
U($CUCC)-U(PCASCODEB)
U(HCASCODEB)
408nA 1.
- -- - --- ----- --- -- ----- ---- -- - --- ------ -- -- ---- --- -- - --- -r -------- k--------I---I-------- r------I---L --- A --- J ------------- L --- A --- J ----
j - - - - - - - - - - - - - - - - L. - - - .- - __:
--- -- -- -- --- -- -- -
-- - --- -- -- --- -- - -- --
.1 - - -
- -- - --- -L -- -
--- - --- -
L
-- ------------A_ j----------------- -------- Mzjhw__4*
------- I ----------------r
9A
2.5U
4.SU
4. ou
3.SU
3 . OU
ID(MM811) * -ID(HSTARTUPREF-MS2)
VDO
VPCASCOOEB
a
Reference
Vottage for
PMOS
Cascode
Transistors
-- --- - -
-- - --- -- -- -- ---
20§nA--------- ----A. -- -J.--------- ---1 ---------------
Reference
Voltage for
NMOS
Cascode
Transistors
--------I
I- - - - - - - - - - - -
. . . . . . . . . . . .I
5 . OU
----
-------S.SU
- - - --- - - -
6.W
&*OM
__O_
UUCC
IDMB11
EVAIMO
I
i
r,,r
17
YalX(1XMM1 1). 2.5V)
Ydx(D(MMBI 1), 6 DV)
YatX(EMTARTUPFEFJ62),25V)
jY*tX("WTARTLPREFW2),6ffV)
atX(V(NCASCODEB), 2."
YGtX(V(NCASCODEl9), S.OV)
Ya0((V($OYCC)-V(PCASOODEB). 2...
JYdX(V($GYCQ-V(PCASCODEB). 6...
Reference
Current of the
2p 8TP
vam
192.66457n
........
.........
195.16307n
4.02927n
...
l-___..__..,...-329.0211 In I
I ...
.......
1 ............
II.......
......
.....
. 1.34M!
1.34932
1
1.44455'
-.-..-.-- ..........
I ...............................
__ ..........
............
-................
--..........
.....
...
..........I.............
I-
....
....
... ..............
- -..
....
........................
Figure C-21: Reference Current and Reference Voltages vs Supply Voltage
129
.10MS2
CLffrent in
Transistor
MS2 in Startup Circuit
.
-------------
--------
------------
+
--------
-------
.........
---------------
---------------
v ----i - -- ---------- - -- --- ---- -- -- -- -- --r - -- --- ----- ----- --
--------- -- -- -- -- --- - --- - --- -r
I -- -- -- -- --- -r -- --- -- -- -- ---------- - -.......................... -------------------
----------------------------- r -----------------------------
-- -- -- -- --- ------ ----- -- --------- -- -I -- ------ -----------------------------------------------------
uAr
-------------a- --
I ------------------ r
r --- T -----
-T ----------------------- T -------------- *------
- -- --- ----- --- - --- -r---T - -- ----- ----- - -- -- i
- -- - ---- -- -- -- -- --- --- -- -- ------ -- -- -- -- -- -- - --- - -- -I- --
J-
- -- - -- --
. .. . ... .I
-- -- -- --
-------
--------
-------
-------- r ------------ -------- I... I--- I ---- --------
-- ------ - --- -r -- -T - - ------ ----- -- --- r
r -- ----- - --- -r -- -T --- ----- ----- --- -- r - -- T - ------ -- -- -- -- ---
7 - -- --------
-- Ir
I
-- GIMP
Quiescent
Current in
PMOS
Transistor
MY of
Ou4M Pair
I - -- --------- --
OA
- ---- - - - - - - - - - - - - - -
j --- ----- -- ---
I - - - ---- - - - - - - r - - - T
I - - - - - - - - - - - - - - - r - - - - - - - - - - - ---- - - - - - - - - - - T
- - - - - - - ---- - ---- - - - - - - r - - - - - - - ---- - -I - - - - - - - - r
- - - - - - - - I- - - - - - - -
-- -- -- --
- -- ------ -- -- -- -- L
I -- -- -- ----- -- --- -I
-5uA-
-. w- - - ---- - - - - - - r - - - - - - - ---- - ---- - -
-- -- -- -- -- -- --- - -- -- --- -- -- --- - -- --- -- -- -- -- -- --- -- -- -- -- -
T --- ----- -
- -- -- -- r - -- T -- ----- ----- -- --- -I
-- --- -- 7- -- ----- ---
I--------I------- r--------------------- r---I---------- r----------------------------- I---I---T---- -- - --- -- --- f- -- ----- ------ -- -- I- --
- -- - ---- L
- ------ -- -- --L -- ----- ----- ------ - --- -
-- -- -- -- r
i - -- -
- -- ----- --- - ----
---
- -- --
-
4. SU
4-BU
S. OU
--------------
S.Su
UUCC
hoessweRmt
PF
pr
pr
pr
measuremelt
YaW("WW). 2."
YddX(V(MM2P). 6.OV)
YdX(O(NM2N),2."
YdX(DOMW , 6.OV)
YatX(D(MMBI 7), 2.5V)
jYstX(D(MMB17),6.OV)
T - ------ ----- --- ----- --
- -- -- -- -r
I
-IIOUA- 3.5U
3. OU
2.5U
c ID(MN2P) o ID(MM2N) v ID(NNO17)
EV*kM*
-- -- --- -- -- -
Quiescent
Current in
NMOS
Transistor
M2N of
Output Pair
-VL-
PAMURS
Vakm
p
6. OU
IDW17
Quiescent
Tail Current
of Differential
Input Pair in
Biasing
Transistor
MB17
...
.........
.......
..-8.12359tj'
...........
.........................
..
...
....... -------.............. .....................
......
...........
----------..........
.....
...
...
........................
....
......
I..........
........
....
.....
.................
.....
................ .....................
............................ - ..............
.......
..
...........
.I-9.68356u!
............
81 2359U
...
......
...............
.....
...
................
.... ..........
..
....
....
................
....
...............
..............
9.68392u*,
................
..........
...............
................
..................
..............
....
......................... ...............
....
...
.................... ..
.........
...............
...
:
...................
.....
..............................................
......
.......................
.....
........
.......
.
.......
.........
..-1.92664u
.............
.....................
-%214u
Figure C-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair vs Supply Voltage
130
Appendix D Schematics and Characteristics of
20pA Micropower Op Amp with Hybrid
Asymmetric Embedded Cascode Compensation
(HAECC)
LIST OF FIGURES IN APPENDIX D
Table D: Characteristics of 20pA Micropower Op Amp with Hybrid Asymmetric
Embedded Cascode Compensation (HAECC) from Simulation............................133
Figure D-1: Schematic of 20A Micropower Op Amp with Hybrid Asymmetric
135
Embedded Cascode Compensation (HAECC)........................................................
Figure D-2: Frequency Response with CL=l00pF and RL= 100k
136
---------................------
Figure D-3: Frequency Response with CL=0, 10, 100, 200, 500pF and RL=100k
-. 137
Figure D-4: CMRR vs Frequency with VN=0, 0.65, 1.3V.............................................
138
Figure D-5: PSRR+ vs Frequency with VN=O, 0.65, 1.3V ............................................
139
Figure D-6: PSRR- vs Frequency with VN=0, 0.65, 1.3V .............................................
139
Figure D-7: Small-Signal Transient Response with CL=100pF and RL100k. .......
140
Figure D-8: Small-Signal Transient Response with CL=O, 10, 1OOpF and RL= 100 k..
140
Figure D-9: Large-Signal Transient Response with CL=100pF and RL=100
........ 141
Figure D-10: Large-Signal Transient Response with CL=O, 10, 1OOpF and RL= 100k2 141
Figure D- 11: Output Transistors Current vs ILOAD .------------------......................................
142
Figure D-12: Rail-to-Rail Output Voltage (vN and VOUr with Av=5)............................
142
Figure D- 13: Positive Output Voltage Swing vs ISOURCE ...............................................
143
Figure D-14: Negative Output Voltage Swing vs ISINK ....----.---.----.................................
143
Figure D-15: Short-Circuit Source Current vs Supply Voltage......................................
144
Figure D-16: Short-Circuit Sink Current vs Supply Voltage..........................................
144
Figure D-17: Frequency Response with CL=OpF and RL 100M @ IL=-1.0, -0.5, 0.0, 0.5,
1.O mA ......................................................................................................................
131
14 5
Figure D-18: Frequency Response with CL=IOpF and RL=1I
k0M @ IL=-1 .0, -0.5, 0.0,
0 .5 , 1.0m A ...............................................................................................................
14 5
Figure D-19: Frequency Response with CL=IOOpF and RL=1I0kn @
=- 1.0, -0.5, 0.0,
0 .5 , 1.OmA ...............................................................................................................
14 5
Figure D-20: Schematic of Bias Cell for 20ptA Micropower Op Amp with Hybrid
Asymmetric Embedded Cascode Compensation (HAECC)...................................
Figure D-21: Reference Current and Reference Voltages vs Supply Voltage................
146
147
Figure D-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair
vs Supply Voltage ...................................................................................................
132
148
Table D: Characteristics of 20pA Micropower Op Amp with Hybrid
Asymmetric Embedded Cascode Compensation (HAECC) from
Simulation
0
Simulation results are at 25 C.
VDD = 2.5V
and Vss = OV.
Primary Characteristics
Value
Spec_ fed
Simulated
Specified
Condition
Symbol
Parameter
GBW26
Gain Bandwidth Product
AVOL
Large-Signal Voltage Gain
(DC Open-Loop Gain)
CL = IOOpF
RL = IOOkL
>
Is
Supply Current
No Load
<21
MHz
> 0.3
RL= I00k=
dB
100
Input Common-Mode Range
. 5V
and must include
-
negative supply
(Untrimmed) Input Offset Voltage
VINCM=
0.65V
1.0mA
VOUTH
High Output Voltage
ISOURCE
VOUTL
Low Output Voltage
IsINK = I.OmA
VOUT
=
Output Source Current
IsNK
Output Sink Current
and includes
negative supply
mV
4.17
<5
> VDD -
V
V
2.34
0.3V
___
CL =lO0pF
ISOURCE29
1D
voltage
voltage
vos2
pA
19.95
2
> VDD VINCM27
Unit
RL = 100kW
CL= I0OpF
RL= 100kW
< Vss + 0.3V
0.19
V
> 1.0
1.55
mA
> 1.0
1.03
mA
Secondary Characteristics
Sym bol
Param eter
SR+
Positive Going Slew Rate
SR-
Negative Going Slew Rate
C ondition
Av= IV/V, IV
Value
Spec__
_ed
Specified
Siu_
_
ted
U nit
Simulated
> 0.15
0.315
V/ps
< -0.15
-0.342
V/ps
Step
Av= IV/V, IV
Gain bandwidth product per supply current GBW/ Is= 29.5MHz/mA @ CL = I OOpF.
Verified by CMRR simulation in Figure D-4.
28 Conservative estimate from calculation.
29
Maximum output source current is measured when the other transistor in the output pair starts to turn off,
i.e. its current goes down to as low as I pA.
26
27
133
Step
CMRR
Common Mode Rejection Ratio
@ DC
>60
144
dB
PSRR+
Positive Power Supply Rejection
Ratio
@ DC
> 60
84.6
dB
Negative Power Supply Rejection
Ratio
@ DC
>60
9.5
dB
< 10
3.70
ps
Av= 1V/V, IV
t,
0.1% Settling Time
Step
134
0.24luA
2.41kA
2.4luA
4
I-! -I, IFO.241uA
2.41uA
xc
24IuA
-f
T
2AIA
0-241 A
0.241 uA
0.242tA
2AluA
O24IuA
0.241334
0.242uA
10.3UA
0.241uA
IO3uA
0241uA
1/64
II
I
LI
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L
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4
l0 1
4 FlI4F
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7 D2 41 07
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1',=2 41 E
406
07
____________________________________________
I
I
Figure D-1: Schematic of 20pA Micropower Op Amp with Hybrid Asymmetric Embedded Cascode Compensation (HAECC)
135
Ac0
20t
200-
Od -
E-C
.~~:
.
j
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ots
1.1
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136
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a
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os
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1 wiz
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* v * P(U(OUT)/(U(IW)-U(It M)))
.
1 0 4 M
16Hz
M
.AI
- ,
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L%
A .
--- J L
i
..
.. LA U - -e - L-L a "I U
Ul
1.MHz
16KHz
1KHz
1.6KHz
* D(U(OUT)/(U(IW)-U(IMl)))
x
Frequency
S
ZerCrows(DB(OUT)V()-V(NB...
Ph__ _rg_(D_(VUT)_(
r
OanArgn(P(V(OUT)(V(I)-V(NM).
1
586.83775k
__P-V(L77.484671
25.51093,
589.27467k
75.90232
20.97270
61.81028
12.701531
557 47221k
4937346
10.83002
Figure D-3: Frequency Response with CL=O, 10, 100, 200, 500pF and RLlOOkf
137
200
Phase
16MHz
Gain
I
4
3
2
58890541k
z
1I
MaswesmatitMS
Masuemt
EvuAte
Phase
Gain
---
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I
I I I'll,
L-Li1j,"i
lots
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Ii iI Iaa
Gain
"
-271d-315d -
-0Phase
Gain
-
10
-186d-
I
Symbol
CL
444.19937k
31.60080
9.32663;
Phase
Gain
C zoom
----------- ------------ -----------
------------
-----------
------------
------------
-----------
------------
-----------
------
20uA MECC: 1PN--60 0 CL=1000F]
VINB=1:D,0'155,1:3V1
------------ ------------ --------------I--------------I ------------ -------------------------------------- ----------------------------------------- ----------------- -------------------------------- ------------ ----------------------------- ----- ------------ ----- ----- ------------ ------ ----- -------------r ----- ----- I------------ Ir ----- ------ I------- ---I----- ----- ------
R
R
d
8
-7: ----------------------------------------------- ------------------ -----------
------ L -----
------------
I------------ j------------ L ----------- i------------ L ----- ----- ----------------- ----------------------- ---------- ------------- ------
------------I------------ -----
-----
------------ I
------------
------- ---- ------------ -----
-----
------------
---- ----------- J,
------------ L ----- ----- -- ----- ---------------------
VIN
m
-00
------
----------- ------
------------ L ----------- ---------------------
0.65
100------------
-----------
-----
-----
-------
------------ ----------------------------
------------
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-----
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-----
------ ------------------ ------------ ------------ -----
----------------
-----
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\
------
------
------------------------------------
------------------------------- ----------- ----------------------- L ----- ---------------------------------------- -----
i
0-
------------ r-w---,w --------r ------------11
------- r ----------------------- r -----
------------ ----------- ----------------------------------------- ---------
I.
----
--------------------
------ -----------
zzz-;
...............
r -----------------
--- -------------- w --------------- ------------------ ---------------- w -------
-----
OmHz
I OmHz
I O@mHz
c * v DB(U(CH)/U(OUT))
----------- ------------ -----
------
l.wiz
-----
1 olz
-----
------------------ -----
I G@Hz
I.OKHz
-----
I @KHz
------
I @OKHz
-----
I.
-----
z
1.3
------
I OHNZ
-----------
-----
-----------
-----
-----
------
I OOMHZ
Frequency
Measwenwm R*sults
EvakmW
pr
pr
Measmeffmt
lyatX(DB(V(CM)/V(OUT)),l.OHZ) =
lYatX(DB(V(CM)/V(OUT)), 1 OW"z)
"
1
1
128.63%51
2
1
144.144971
98.43440:
A
3
103,33220:
..
............
Figure D4: CMRR vs Frequency with VtN--O, 0.65,1.3V
138
.
................
...
....
.......................
...
.................
...
I
p les-
26uA FAEcd [PM=60 i CL::lOOpF]
------------ I ----------- -----------...... ----------- I .............I ----------- I--------------I -----
s
R
R
+
------------
------ ----------------- ------ ----- j ------------ ----- ------ ------ ----- L----- ----- ---------- L ----------- -------------------
d
B
............ ----- ----- ............
..... ..... ............ ..... ..... ------ ----- ----- ----- ------------
VIN
M
-00
---- ............. ----- ------------ ....
----------- ------------------ ----- ----- ------ -----
0.65
------- ----- ----- ---------------- ----- ----
........... I------------- ----------- ------------
I.ORHZ
mooomen"m
I
jYdXM8(VV#VDA)N(OUT)), I aft)
IYWOWVCVDDA)N(O(JT)), I01ft)
I.NHZ
19ONZ
Iffiz
1.$Hz
IOBNHZ
I @Mz
DB((U(UDDA)-U($GLUCC))/U(OUT))
Ev*We
F;r
----- ----- ------------- ----- ----- ------------ -- ------ ------ ------
------
-------------------------
------------
------ ----- ----- ----- ------ - -------
------------
........... ............
-V1.3
Frequency
m"emonmamomm"
1
2
1
1
I . smZ
I siNitz
IsiNz
lImZ
1
ox-,OU401 ......
04-%121
.............
......
....
56.4*3669
.........
.......
.... 84 58M
.........
I
Figure D-5: PSRR+ vs Frequency withVIN=O,) 0.659 1.3V
p
S
120-
I 48= Ir
v ---------
20uA HAECC IP1=60: 0 Cl.=100 F)
------------------------------------------- ------------------------------ ----- ------
R
R
............ ........... ------------ ............ ............
--------- .........
------ ----- ------------ ------ -----
d
---------- ----- ------ ------------------- I ------ -----
VIN
M
............
-00
------------------ L ........................L
........... ............ ------------------------ ----- ----- ------
----- ----- ............ ..... ..... ------------
------------
------------
------------ ........... ------------ ------ ----- ------------------------ ----- ------
-------------
----- ----- ------------ ........... ------------ ------------------------ ..... .... ---------- - - --
...........
I.
- -- - -
- - -- - - -- - -- -
- - -- - - -- - - --
------
-----------
-
----------------
I OHz
I.Oz
I $@MHz
I GaHz
@MHz
o v DO(U(USSA)/(U(EOUT)))
-- - - -- - -- - -
-----
------------
-----
------------ [ -----------
1. MUZ
1961Z
-----
I MHz
--------\ .
- -- - - -
....
----------------
...
. . .
.
1.$Mz
I 9@KHz
C7
IYatX(D8(V(VSSA)/V(EOUT)), iHz)
P
JYdX(DSMVSSAYV(EOUT)). 10ft)
Frequency
1
1
3
.
I
51.4mal
51.41-too I
Figure D-6: PSRR- vs Frequency with VIN=O, 0.65, 1.3V
139
.
- - -- -
-------------------
Afmam4awnt Room"
EWAW*
0.65
............ ----------- ------
..............
i IHHz
-171.3
IOM=6'
iOuA:HAE( 'C
............
------------
......
............
......
-r-L-
M
I
"Y0 Aml
, L = I 00c
. . .90k
-----------------
IL=OMA
------
------------
VOUT
699MU----------
-----
......I .........
...
I------ ------
----------------------I------ - ---
VINP
-16r-
- ---
---------------------
_ ----------- -------648MU....
----
...............
..........
-----
I ..... I.....
.......... ......r ----- r ----------- ------
-----
.................
....
---_----------
-------- _ ------- ------
----
A
6 OW
----------I ----- I ---------
I ..... .....
-------------- -_ ------ _ -------
I------ ----I------------------
----------
.............
I----- _--
20us
I U,
'I ous
5US
......I -----------
---- ------ --------
--- ------
------I -------------
U(OUT)
U(IW)
-----
Time
Wastwenw" Rest**
E-kag.
F
VAW
MM
Wasuiroamd
XRWITWVI OLM 0.1.5
ISOOKUT
.................
Figure D-7: Small-Signal Transient Response with CL=1OOpF and RL =100kfl
I
0
20uA:HAE(:C [OM=66
---------------------------------------
------------ ...........
-----------
---------------------------
------------
IL=OmA
VINP
- T-i
688MU_
.....
----------
....
------- -----------................... ....
I .....
----------- -----..... . ...
7
----------- -----
- --------------------- ----------- ------ ------------------- -
-------......I ......I -----------I ....
.....
------ --
64@W----------- .....
...........
VOUT
-------- --
-----------
---------- ----- j .............
-----------------
- ---------
--- ............ ..... 11----------- ......
VOUT
CL=OpF
---------------- -................ ............ ..... ..... ..
---------------------
CL=1OpF
6 @GNU
--
U(IW)
&NkMe
W
UOUT)
_ ------------------29us
Tim
2
Mosowan"
ISOMMUM XPMWM(V(OUT), 0.1. 5
-----
I Us
I Us
as
I
-----
----------- ......
----------
568W
-----------
.....................................................
...............................................
---------
-------
----------- ...
---------- .......
I
1.46326ut
1.40845W
IMM I
Figure D-8: Small-Signal Transient Response with CL=01 10, 100pF and RL=lOOkQ
140
VOUT
CL=1OOpF
-Ir-
VINP
-AVOUT
...... q
f ------ i .......
.......
.. ---
------
.......
......
.......
------
...... ......
.......... ...
------------
......
- -- ---
---------- .......
...... -----......
I ... ............................ ......... ....... --------------
............. ---------- -
.............
....
.........
..............
......
.....
Sus
Is
U(IW)
as
3lus
25us
29us
Isus
I Ws
& U(OUT)
Time
Memwenwm Row**
Evakide
mo~*nmd
Vakw
rwr
01 Su
qt'AffmTbm
jSWwRd&jft&_VUrWMOUT) Su...
Fr
j9ewRde-FmLXRWqWWO(JT). 2W
I
..
......
..
...............
------...
- - --------------------- --
3BO783U 1
314 'SWSk -----------
-Ul.7em !
Figure D-9: Large-Signal Transient Response with CL=lOOpF and RL=100kfl
4
.'
an
20uk 6AE:C:
lp 40 '* I:L=;10DP51
1
......................
I
-- 0-VINP
..............
VOUT
CL=OpF
... . ...........................I---
4
------
..............
..........
------
------
------
------
......
......
..
VOUT
-----------
L........
4...
..........------------
CL=lOpF
i
VOUT
ou4--i-;
es
I Sus
5us
U(IW)
15us
U(OUT)
26us
25us
351
39us
Time
100"WOMMA FAMUft
sGftvn=-Mnj*(WaM, 0.1, su
qewRde-ffi--Atwve(v(OUT)'
mwmuteFai_)owwv(oun. zu..T
4MM :
MW2M 1
4DW7U
370MU
T
-Me-14"UM
-41 ADM j
Fieure D-10: Large-Sianal Transient Response with CL=O, 10, 100pF and
141
-----------------
L=100k.0
CL=lOOpF
MM M : N
.......
I.......
.............
-F t
.................... ............
............. ......... . . ...............
It
M
IM! IM! VM
IN
F! I I
.......
.....- --------........
-
I ........
I ovum M
2
P
T
.........
1
TT I fit h filial
IIUA-
1 ---11-------:
...................
........
I ......... .............
-!!!nTTTffnT
........
....
2 I-m-A-
MMI
- ------------ --189PA- --...............
..
ID(MWP)
E*AU"
.............
........ ..............
........
..............
------........
-----.......
............. .
------- - ------- ---T --- - --- - ---- '.
,
.
.
S. "A
2. SMIA
1.90A
1016M
, Do")
:-;Q
.......
..
........
.....................
. .....
....
.
W
..........
..
...
.....
. .................
, * **
-- -, --'*----**--*-'*****'**"*'* .................
..............
---------------....................
..........
...........
-S04 863 &)U
...........
..........................
-..- --..........
........
.......
3.W35lU 1
Figu re D- 11: Output T ra nsisto rs Cu rrent
I
I
.
.20
-----------
MAEU ........
..............
vsILOAD
:
.......
10
I
;
.....
t
..........
............
.......... I
a
........ ..
I
.... ...
.
............... .................
................... .
I .........
..........
........
.....
...... ....
00W)
...........
........... ...
.......
....... ...
...........
Slus
WOUT)
I----- ......
IMuM OUT,
---....
---.
....
.. ,
------------....
........
....
..........
........... ........ ..........
.. ...............
x
I...
I ---I ---I ....
... ..
......j
......
.. ........................ .......
.....................
....... ........... I....
.............
.
..
... ..........
.........
... ---.. .. ....---... ...
209us
ISIUS
I Ms
25 @us
time
Nbeswen"M m
vak"
P
...................
..............
............
.........
I.SU- -
---
I
VINP
..........
..............
0
I
;
..........
...
..........
tU 2.SU- I
IDM2N
Current in
NMOS
Transistor
M2N of
output
Pair
won
9 al
-
..........
---------................ .....
ILOAD
M"*wennm
YOM-DON01), ODMA)
yLt
I
#A
-1.1"
-2.90
- ID(WVN)
Ydx(4xmmv). 0-14")
YdxM0&W ,0&rA) .
YsM -ID(WA2P), I.OMA)
Yotwo(MM2N), ta")
PMCIS
Transistor
M2P of
output
Pair
........ . ..........
.......
. NIMMMM' U.N.-
-----....=
.. .. ..
ISPA3. am
...... ..
...............
IM! PM I,
FM! 0 - P 0:H P
MMYiMMMI
.IDM2P
................
.............
..... ....
...........
...........
F
Current in
..............
.... .... ......
I NO -
-U--
-------- ------
I
.......
...
I......
12 W44M!
Figure D-12: Rail-to-Rail Output Voltage(VINand vouT with Av=5)
142
Salus
VOUT
I-
a -mu I . . . . I . . , - I , , ,
.
I ,
,
,
I ,
.
.
.
I -
,
I . Ou -
! ! ! ! I
- ! ! ! I
# - - , I
! :
: !
.. .............
..............
---------- --
.............
.....
.....
I------
-------- ........ ..
........
.. ........
IAMA
I
-- --------
.. ................ ..
9.50A
.
.
........ ........1 -. ----- ----- ----.. ..........
..... ......
m
-
4.50A
4. WA
3.50A
3. @nA
2.SMA
2. GOA
1.50A
U(OUT)
ILOOD
Vdu*
PF
17
Figure D-13: Positive Output Voltage Swing vs
0
14. ou -
u
t
p
t
.........
........ ...........
........... .......
3. Ou -
-------- I--,....-
.. ........ .......
u
0
...............
..............
..
................
... :.---.--l,-
.. ........ .......
ISOURCE
.................
20W H a C:- -EP11-t 0-.*..............
...........
...................
....... .................
....
...............
....
.
...
......
....
.........
......
.....
...
......
---------- - ..........
..
...............2.SM
-4
...............
...
...
....
lyatxm ouT)IOMA)
IY*W(OM. 0-5")
lyotx(V(OUT). I IWA)
...........
.. ...........
...........
.. ........
t
2.@U.
Su i
-4.5MA
-S.&A
0 U(OUT)
------------------
--------
-------
u
-4. GmA
-2.5mA
-3. &A
-3.5mA
..... ...........
.. ........
.................
-2.@RA
...........
...........
-1
SMA
-1
fta
-9.50A
ROAD
WOW- m
EW*W*
E
M"owonm*
. ft A)
YstxmOuT)
(XJT). -0-4M)
4mm"
Vdae
21 33e28n
.....
..........
..........................
.L....
...........
YatXM
Yatxmotm,.1
.........
.....
....... ..
......
..
.........
Figure D-14: Negative Output Voltage Swing
143
vslSINK
........
am
.
k Mb..&
I s
-------------............ --------
_OdA -- A-E C i(PH=66 OiCL
............
-----------
............
-------------
I
I
I
I
.......
............
---------------------
.....................
R
C
E
f ---4 .........
3W
-------------------- _ ------------- _ ---------------------- -------- .................... ...................
--- --Ir --I ---------------- r ---I ---I --------
.......
............. ........
-----r - --
200-
------- -----r ---lb
--------------------------------------------------
4
----
--
--------------
I-------- 1.I-------- ------ --- .........
--- ---
i ---4 -----.. 4 ---
1
------------ --------
---
--- ----------I....
------
.......... ---------------------------------
---
--- ---
-------
..........................
3. OU
_4
--- ---
4 --- ----
---------------- -------
2.5U
U I(UISCH)
...........
----------- ------- - - ....... ............
-------------------------
f ...4 ------ --F ---
- -- T
.......
.........
-------------
................... I
------- ---
----
j&.5U
3.5U
................
.........
-------- --------
........ _ .
I .......
--- --6.9U
S.OU
UUCC
Figure D-15: Short-Circuit Source Current vs Supply Voltage
I
s
I
N
K
------------
A
AECC iPti=6d
OLiA
........ ............
.. , ....
.........W A -. : :
4 ---a :W.10'
I ...
I ..............
........... ----- ------------------ ----------------------- ---------------------- ---------------------- ----------- _-_........
I --- ----------------------------- --------------- ------------------------------------.......... -------I--------------f ...
- .4 --...........
-----------
I ...
.........I ...
........ -------
..................I ---- ------- ---------.......
........ 1.
I--------------------- ---------------------- --------................ ---------r ------------ ........ r-.-,
-----
--------
-------------------
-1 IRA
-------------------------- ---------------------------------- -------
---
-----------
--- ---
--------------------........
i --3.9U
.............
................
------------------ _ ----- --------
................ ............
--------
----- -------------------- ---
-2901
2.5U
. I(UISCN)
-------- ------------ --------
r
-------
_150A
------------
.........
-------------- ----------- _ ---------
............
...
........
................
.............
r ------------- ------- r ..............
-------..........
--------
------ Il------------
--------
-------------
n
......... __ ----
---------
--------
##.SU
3 sU
5.W
UUCC
Figure D-16: Short-Circuit Sink Current vs Supply Voltage
144
6.W
-
_
_____
28-
_
_
-I
.
." .......
I
'~~i
-~
n
96d-
6
1
M-4
-+++-
+4+
1ss-
-135d-
;
-4+
..
...
.
....
-14W
.-..
.
1
d
4st4e-
---
5.7
-225d
i4 r4--
1
-+
--
-_q~
-- +-H6,*
t-6
6,
+Hi6*
66-+60
-NR-
+
f
-I
-- --- 4 +--R
I X -l:
-. " -I
4I I
i6
M E---
-+t6
6663
-+
-270d-
-315d-
--
-+
dIz
1
1.mInz
1. 6z
181z
T)
- P(
IVweu~t84
+H-M
666
-+
ED
(U(
Frequency
1.s.
.........
584,55041k
M.-
.
-
6 3
-
-
+
++-
1. 3hz
1868Hz
168Hz
U(IH.)))
UT)/(U(I.)
183Hz
134Hz
IL
4
375
5
78.88615
see rinDvou vs)vL 78.407971
3228878
3425113
-EvskuNOnFaled- 4Ev~kAfFdG&
p P-k(DBMvOUrvVMP)-VOW0)). 1)
EvAnieonFeledEo
-1.0
_7_37_453
M aa
-0.5, 0.0,0.5,
ie
Figure D-17: Frequency Response with CL=OpF and RL=100kfl @l=-1.0,
-0-
Phase
324538
7t.35283J
32.78838
~
25.103
Symbol
(mA)
50.28884k
4489
881A
7748467
S
--
. .
+
3i
584.D7888k
_
+H
--
1.6Htz
186H
16Hlz
U(I )))
U
v(
++9
1.OmA
Gain
g20
_4d-
-0.5
Phase
7 -I=--
-90d-
-
- -
0
Gain
0.0
Phase
-
-
-225d-
X
--
-27W4
I.4
._
-
-- -.
Gain
0.5
P(1u)((le
._4 ,-114
...
I [j1
.,481: ---
-2 2 5 d
1-(ts)
..
I
..U)(
..
..
.qjt,-- ..
..
(4.]
Phase
41U
Fr
)-4444))
+tFr
Gain
EOO.
p Zee~rsa(D~v~UT)v~iev(SL
(
p ipiOUT3(v(W)-v04vD
,1)
42108
lkelW"A
2
1436701k
5042"M7N
3
SeS.991k
7a.56s
764A0st
30.42M88
EVa.I F
-28.28781|
.
7617828
2918M
Faled. 4VWUM
29W7
4n
4Ev
Fd&
Evs8.
M
--
266,
--
6...
--
-964d-
6
--
a
3+3
6--:--:-
-
--
I
66*.. ...
44-3-+ 3+336
-;
-A--
6
6
666-- 4*H
6663
664
Phase
FAdNO
IL=-.O, -0.5,0.0,0.5,
Figure D-18: Frequency Response with CL'=10pF and RL=100kfl @
I
1.0
5).7.2m2
WJ1M261k
75.0232
20.7270
2844117
5
4
E3
.
.....
---++
--+-
64663
~
6-
666++
46+
n
d
I -135d-
e
-4
4 t
11WH
66 336 663
46 --
-3-- -- 6
43336
6~6K 664 66-31
~
-
-366
-3
3- 64
-1864-
---- -
-----225d-
-in.
5
-270d-
-+ 2.-36,
6
-- ++ r 6663
-- ++M
64
3*.
-
-
66
6t+t
.... --361
+-44-4380
-
6 66
iM-- -4+++6*
6664
6 +
666
-6663
+
6 66-+3663
- -- 6H'N",
m
+i
3----6+
--4-i"+
6----H- 336
..... ---
----- 3 -- -- 66:
- 66 6
66
6
-3-63
6--6-
3-3
H
-- 46
-315d-
-368d-
1.
d4z
EU
1
mlz
.
-
16Hz
1. Uz
1864Hz
. .... ))
P(U( UT)/(U(
IW)-.(..
M
y
Fiur
P-k(D
Frqu
1368Hz
8.(4.(.T)/(U(I
1.6H1z
1631z
1661Hz
)-(I.I.)))
Frequ86lc5
valnew
78.812411
31951872
.8v48vdoonvue)-vf
-en )),)
168Hz
1.68Hz
186Hz
R e elnn wii
818138
12713
77D387
-t'E-
Figure D-19: Frequency Response with CL=I00pF
t
i3"
CLlO p 1AX4a
and
RL=IO0kQ @
145
9861
4
81987
-IL=-1.0, -0.5, 0.0, 0.5, I.OmA
87
n"aI--
1
1.0MA
203M v#?"
RL=pf l al - 0
H
6M6
-363-63
Gain
Start-Up Circuit
JD3nA@
Bias Voltages Setter
4.03nA
\)D=2.SV
I
03E-09
vCc
STARTUPR 3: MS2
1.109,1L
~
0.241uA
4.17nA
ID=-4
-09
,
vCC
MS3
L 1/100
00,0
I0=
17E09
0.241uA
I-
E-7
140 L
L
Reference Current to Op Amp
IREF Generator
0.236uA
,14O
0.241uA
I0=-2 4-07
E-07
L
0.241uA
E-2 41
7
L,100
10/4
ID= 241E07
11 C
10/1 L
D=
41
HD=-2
.7
11= W41E-07
35E-07
v/L
1V14L
4101
10/1 L
-1..
Ci-0
IMelc
L,1011
P
ID=-1
P
L
-12
L
MOISE
1143
10503E 09
MS4LL
.110
GNID
VCf
STARTUPR
-FS41
tiOwoL
L2M9
E210
VI4 03E-09
----
10 1 E-07
GNUD
1:63t
I
NCASCIDDIE
IL
ny I
"LlM
RB
9
0=4172 09
L6*
WI
i
0
-
-
-
-
Figure D-20: Schematic of Bias Cell for 20pA Micropower Op Amp with Hybrid Asymmetric Embedded Cascode Compensation (HAECC)
146
1.6Ur- -- T
- - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ---- - - - - - - -- - - - - - - T ---------------------- T - - - ---- - - - - - - - - - - --- - - T - - - - - - - --- - - -
-
-1
I - -- J - -- -- -- --- -- L - ---
v
--
------------
r
SEL>>
I
----
r-- -
T
J -- -- -- -- -- -- -- ----------
------------
-----------
------------------ ---
- -- -- --- -- -- ------------
-- ----- ---
-- -
z
-- -- --- -
------------
,3 I
-- -
- -- -- - - --
Reference
Voltage for
NMOS
Cascode
Transistors
- -- -- --
------------
---------
r .................
.. .. .. ..
. z u
4OOnA-
U(HCfkSCODEB) * U($G-UCC)-U(PCASCODEB)
1.
r -----------r
y -------- ---------1.
--------r
L
I
.
-- -- -- --
-- -- --- -L
A . ..
- - - ---- - - - - - - L
VDD
----------------
------------------ -------
. .. -- -- -- -- L
L - - - j - - - - - - - - - - - - - . . . . . . . ...
VKASCODEB
L - -I -- -J -- -- --- - --- --
28@nAL---
--------
1
-------- L ---L --J ---I-------- I----------j-------------------------------------------------------------- ---------------- ------------I ----
r ------------ i-------- r---T-
2.5u
--------- --- I ---
4.@U
3.@U
3.SU
ID(MMB11) * -ID(MSTARTUPREF-MS2)
4.SU
-.1 -------- --- I --- I ----
5.9U
--------- --- I --- I----
5.5u
uucc
Evduat*
pr
For
pr
P,
PF
6.@U
Reference
Voltage for
PMOS
Cascode
Transistors
.---- BMom
--Glowil
Reference
V&kW
Current of ft
1..
240.8W7n
.........
.......
.
......
........
....
......
I..............
................
..............
___OkA
........
.....
........
................
....
....
........
........
.9221
gn
........
......
. .....
....
.......
.......
.......
........
.......
...
........
............
.....................
....
..........................
......
..
4.02927n;!
.........
.
..........
........
..
.......
.........
.................................
.......
.......
......
-329.0211
..............
...........
...........
.............
......
...........
.....
........
.......
.......
..........
........
..
-...
............................
....
........
.. In I........
Currentin
1.354781
.......
.....
........
.........
...................
......
.......
..........
.......
........
........
............
Transistor
1.358M ...
...........
...........
........
-- ..........
.......
....
.................
.........
MS2 in Start-
MeawNeume
YatX(DMOBI 1). 2.5V)
YatX(D(Wffil 1), 6.OV)
Y&tX(DMTARTLPW MS2),2.M
YatXM(MSTARTUPREF
YeamNCASCOMB), 2.M
iYetX(VOCASCOM), 6.M
lYdX(V($GYCC)-V(PCASCODEB). 2..
YefX(VW VCC)-V(PCASCODO). 6...
TOP
-- GVWAXWEB
-------------
v
- - - ---- -
-----------
.. .. ... .
-- I
- - - - - - - - - - --
v
-- - - - - - - - - - - -
--------
--------
-----------------------------------
IAU
- - - - -- - -
Ii
1.46035 ;
IAMI I
..................................
Figure D-21: Reference Current and Reference Voltages vs Supply Voltage
147
Up CjraA
L -- - -- ----- -- -- -- L - -- L
j -- -- -- -- -- --L
------------
---------------- ---- - - - - - - - - - -
I OUA-
-- -- -- -- -L
- -- I
I -- --I -- - --- -- -- -- L
-------------------------
I - -- - - - - - - - - - - - -- - - - - - - - - - - - - - - --- - - - - - - - -
------------- :--------
-------- L
---------------------------------
------------
- -- ------ -- - -L
------------------------------------
--------
---------------------
--------
- -- - --- -I- -- T
i--
- J- -- ----- - --- -L --- ----
---------------
-- ------ -
IMP
- -- - --- -
- -- -- -- -
Quiescent
Current in
I--------- --i---j ---L--------------- L ------- ------------ ----- ---I--J----------- L--I--I-----------------I--A-----------I---------
-------------------------
--------
r -- -T- -- ----- ----- - --- -r -- -T -- ----- --- -- - --- -I -- -T -- ------ ----- - --- -I -- -T
-- 0--
---------------------
--------
---------
-- ----- -- -- -- -- -T -- ---------- --
- ------ - ------ - ---
---- , ----
--- f -
PMOS
Transistor
M2P of
Output Pair
8A
lvt
--- -------------- --------------- ------
---- C
--------- -------------- --------- --- ,.L
---
----------------I-
------- r--a--, *
1,
-------------------- f --- j ------------- L
-T -- ------ ----- - --- -
-------- --------------------- -----------------
-- -- -- --- -- -T
1
'
1; 16----
-------- L --- I --- I ------------- L --- 1
---------------
------------
- - -- -- -- r - -- T
- ------ -- -- - -
IDM
.
-. 1 --------
--------
-- ------ -I- -- -
-1 OUA ------------
n----------------------
------------11---
--------- I ---
------------ r
----
----------I
----- r ---
11 ----
-------
---------
-------- r ---------------------- r --- T ---
----
---
M2N of
T - -- ---- ------ - --- ----- -T -- ----- ------ ------- -------------
---- r --- f
'N ----
- - - - - - - - r - - - T
Output Pair
-V-
'I - - - -
IOMB17
-20UA i
2 SU
ID(HH2P)
3 . OU
ID(MH2H)
3.SU
ID(HH817)
4. OU
4.5u
UUCC
Measmenwit
YGMONMM. 2.5V)
yefX(D(W##12P). 6.M
IYOOMMM2N), 2,M
I
I
----------------------
- --r - -- T - -- ----------------------
Quiescent
Current in
NMOS
Transistor
F
YatXtD(MM2N), 6.OV)
YaMD(hW 7), 2.M
F7
JYGDMWOEI 7) 6.OV)
.
.
S. OU
5 .5u
Quiescent
Tail Current
of Differential
Input Pak in
Biasing
Transistor
I MB1 7
...........
.....
...........
6. OU
Measuteroett ResuRs
Wakle
-10.1
. 643OU
.......................
-1 2.06189U::
...........................
......
..........
.......................
..........
.......
.....
.......
............................
...
.............
......
.....................
.................
...........
............
.....................................
10.1 642OU ----------------------.......
......................
........
............
......................
...
..................
.....
......
........
............................
....
....................................................
...........
12.06226U ...........
. .....
.......
11
...........
......
.-.,..
...............
...........
...........
............
......
.....
-2.40866u
-2.43992U
Figure D-22: Quiescent Current in Output Pair and Tail Current in Differential Input Pair vs Supply Voltage
148
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