Digital Systems Laboratory
ECE230L – Spring 2011
Draft
Lab 9
Lab 9: Introduction to Sequential Design
Objective: Transition from combinational to sequential circuit design.
Lab Details:
A. Below is an implementation of a gated D latch, found in figure 7.8 from your reference text (pg. 391).
Using Xilinx schematic capture, duplicate this circuit and use traditional combinational test bench
methods to test the circuit. Build a table of test cases that will completely exercise the circuit. For
every case, determine what the expected value should be. (If you consider the fact that a signal could
change its value at any point in time, you should have a total of 16 cases - but when applied to the fact
that Q can have two possible states, the total cases are then 32.) If you don’t test for all 32 cases,
write a justification as to why a smaller number of test cases is adequate to completely exercise the
circuit. Your test bench should show all internal signals (give them a good name and show on wave
form).
Implement the design on the Basys2 board by assigning the two inputs C and D to switches, and the
output Q to an LED. Check-off will require that you can demonstrate usage of switches.
Demonstration description should be in report.
Check-off ______________
Symbol for D latch (above)
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Electrical and Computer Engineering Department
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Digital Systems Laboratory
ECE230L – Spring 2011
Draft
Lab 9
B. Below is a master / slave D Flip-flop created from the D latch in part A. As in Part A, exercise this
circuit with the traditional combinational test bench methods, use the same set of test cases (32) and
verify the results. Also verify the circuit using the clocking method, and make sure that every path of
the state diagram is exercised.
Implement the design on the Basys2 board by assigning the D input to a switch, the Clock input to a
button and the output Q to an LED. Check-off will require that you can demonstrate usage of
switches and buttons. Usage demonstration description should be in report.
Check-off ______________
Symbol for D latch (above)
The following item might be required in user configuration file.
NET "Clock" CLOCK_DEDICATED_ROUTE = FALSE;
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Electrical and Computer Engineering Department
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Digital Systems Laboratory
ECE230L – Spring 2011
Draft
Lab 9
C. Below is an implementation of a T Flip-flop created from the D Flip-flop in part B. Verify the circuit
using the clocking method, and make sure that every path of the state diagram is exercised.
Implement the design on the Basys2 board by assigning the T and SET signals to switches, the Clock
input to a button and the output Q to an LED. Check-off will require that you can demonstrate usage
of switches and buttons to achieve results. Usage demonstration description should be in report.
Check-off ______________
Below is a screen capture of the Xilinx tree for the previous circuits and the associated configuration files.
Boise State University
Electrical and Computer Engineering Department
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Digital Systems Laboratory
ECE230L – Spring 2011
Draft
Lab 9
D. Below is a design that uses T Flip-flops from the Xilinx library. Implement the circuit and explore the
circuit to discover what it does. Use the two signals connected to the LEDs as indicators of the state
of each flip-flop and the overall state of the circuit. Verify the circuit using the clocking method, and
make sure that every state of the circuit is achieved.
Implement the design on the Basys2 board by assigning the Sw0 signal to a switch, the Btn (Clock)
signal to a button and the outputs LED0 and LED1 to an LED’s. Check-off will require that you can
demonstrate usage of switches and buttons to achieve results. Usage demonstration description should
be in report.
Check-off ______________
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Electrical and Computer Engineering Department
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Digital Systems Laboratory
ECE230L – Spring 2011
Draft
Lab 9
Deliverables:
Check-off:
Check-offs for Parts A-D by end of lab period
Submission:
Due by Midnight Thursday 4/7/2011
Email:
To: ece230lreport@gmail.com
cc: your team partner
Subject: Lab9_TeamX report (X is your team no.)
Attachment: Lab9_TeamX.zip (contents as listed below)
Attachment:
(must be zip format – no others accepted)
Contents of zip file:
1. Report File: \Lab9_TeamX_Report.pdf
Report Content
(create in Word using template previously provided)
Clearly and completely describe your analysis as noted above, techniques and trade-offs that you
have made. Be sure to include
1. Simulation waveform
2. Results and reflections
3. Anything else that you need to completely describe the process
After report has been created in Word, create a pdf and then zip.
Boise State University
Electrical and Computer Engineering Department
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