Spring 2011- Syllabus
Digital Systems Laboratory
ECE230L
ECE 230L - Syllabus
Instructor:
Arlen Planting
Office: MET 227
Phone: 426-4826
Email: clarenceplanting@boisestate.edu
Office Hours:
Mon/Wed/Fri 2:30-3:30pm or by appointment
Lab Assistants:
Andrew Landoch, Vikram Patel
Course Description:
Design, build, and test small digital logic circuits using TTL gates, CMOS gates, flip-flops, registers, counters,
LED, infrared LEDs, and Xilinx Spartan 3E FPGA.
Prerequisites:
COMPSCI 117 or COMPSCI 125, Co-requisite: ECE230
Lab Meeting Times:
Section 1: Tuesday 9:15 AM to 11:55 AM
Engineering Bldg, Rm 312 (ET 312)
Section 2: Thursday 9:15 AM to 11:55 AM
Engineering Bldg, Rm 312 (ET 312)
Required text:
No required text. Laboratory instructions are provided on course/laboratory webpage.
Course/Lab Webpage: http://coen.boisestate.edu/aplanting/ece230spring2011/
Laboratory Objectives: After taking this laboratory, the students should be able to:
• Design and build the functions described by given specifications,
• Analyze and simulate the functions described by logic diagrams,
• Implement functions in logic gates (TTL and CMOS gates) and FPGA of given specifications,
• Develop circuits using combinational and sequential components, and
• Design, simulate, and implement state machine using Xilinx ISE, and BASYS 2 board.
Grading:
Laboratory Assignments / Reports
60%
Hands-on Quizzes
20%
Final Project (with formal report)
20%
Grade determination: 100%-90% = A, 89%-80% = B, 79%-70% = C, 69%-60% = D
Lab Requirements:
There will be lab check-offs, lab reports, and lab quizzes. The labs will be performed in 2-person teams, with
check-offs and lab reports as a collaborative effort between you and your lab partner. Lab reports are due by
midnight on Thursday of the week assigned. When check-offs are required, check-offs are due by 11:50 AM of
the lab period to which you are assigned (e.g. if your assigned lab session is Tuesday, your check-off will be due
by 11:50 AM Tuesday). Lab quizzes will be performed individually, to test the skills of each team member.
Final Project:
Final project description will be given during a later lab period. This project will not be completely defined. We
will go through a few negotiation sessions. You get to ask all the questions you want. The final lab will require a
more formal lab report than previous labs.
Boise State University
Electrical and Computer Engineering Department
Page 1
Spring 2011- Syllabus
Digital Systems Laboratory
ECE230L
Tentative Schedule of Laboratory Assignments: (to be updated on course website)
Week
1
Lab
0
Laboratory Topic
Introduction
Details
Xilinx ISE Tutorial
2
1
Basic and Tutorial: Introduction to
Digital Systems Laboratory
Introduction to discrete logic prototyping board, logic components,
and Xilinx ISE and ISE Simulator). Implement functions in logic
gates on discrete logic prototyping board with 7400 series chips.
3
2
Combinational Circuits: Universal
NAND
Build basic logic with just NAND and NOR. Design & Simulate
with Xilinx and ISE Simulator. Build circuits on Proto-Board with
7400 series chips.
4
3
Advanced Combinational Circuits: "Bad"
Logic Circuit Re-Design
Derive Boolean expression from existing circuit. Simplify output
equation. Re-design circuit of simplified equation.
5
4
Introduction to FPGA: Digilent BASYS 2
Work with busses and create custom chips.
6
5
Introduction to FPGA: Seven Segment
Display Driver
Derive Boolean expression from truth table. Design & Simulate in
Xilinx. Implement circuits and test their functionality with FPGA.
7
6
Adders & Subtracters: Arithmetic Unit
Modular Design. Design a 4-bit adder by using 1-bit full adder
modules. Build an adder/subtract unit with add/sub control bit.
Test on FPGA.
Lab Quiz #1
Derive: Truth Table, K-Map, Simplify Expressions, Design
Circuit, Timing Diagram/Simulation, Test on FPGA Platform.
8
9
7
Multiplexer, Encoder, Decoder:
Multiplexer and Decoders
Design simple MUXs & Decoders with logic gates. Implement
certain Boolean Expressions with MUXs and decoders.
10
8
Adders & Multipliers: Yet Another
Arithmetic Unit
Design 4-bit fast adders & multipliers. Multiplex signals from
multiple sources into one common data bus.
11
9
Verilog, Latches & Flip Flops: Verilog
& Simple "Memory" Circuit
Design a logic circuit using Verilog instead of Schematic Capture
in Xilinx. Understand/show the differences between latch and flipflop.
12
10
Counters: Latch, Flip-Flop, Up-Down
Counter
Design a 4-bit up-down counter and download the design to FPGA
13
11
Finite State Machines: Sequence
Detector
Design a state-machine sequence detector. Show state diagram,
state table and assignment table, K-maps, equations, logic circuit,
download design to FPGA.
14
Lab Quiz #2
Design a state-machine sequence detector. Show state diagram,
state table and assignment table, K-maps, equations, logic
circuit, download design to FPGA.
15
Final Project
Details given in lab
Boise State University
Electrical and Computer Engineering Department
Page 2