Gate-All-Around Silicon Nanowire MOSFETs: Top-down Fabrication and
Transport Enhancement Techniques
By
Pouya Hashemi
B.Sc., Electrical Engineering, University of Tehran 2003
M.Sc., Electrical Engineering, University of Tehran 2005
Submitted to the Department of Electrical Engineering and Computer Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering
at the
Massachusetts Institute of Technology
September 2010
© 2010 Massachusetts Institute of Technology
All rights reserved
Signature of Author ______________________________________________________________
Department of Electrical Engineering and Computer Science
September 3, 2010
Certified by _____________________________________________________________________
Judy L. Hoyt
Professor of Electrical Engineering
Thesis Supervisor
Accepted by ____________________________________________________________________
Terry P. Orlando
Professor of Electrical Engineering
Chair, Department Committee on graduate Students
Gate-All-Around Silicon Nanowire MOSFETs: Top-down Fabrication and
Transport Enhancement Techniques
By
Pouya Hashemi
Submitted to the Department of Electrical Engineering and Computer Science
on September 3rd, 2010 in partial fulfillment of the requirements for the degree
of Doctor of Philosophy in Electrical Engineering and Computer Science
Abstract
Scaling MOSFETs beyond 15 nm gate lengths is extremely challenging using a planar device architecture
due to the stringent criteria required for the transistor switching. The top-down fabricated, gate-all-around
architecture with a Si nanowire channel is a promising candidate for future technology generations. The
gate-all-around geometry enhances the electrostatic control and hence gate length scalability. In addition, it
enables use of an undoped channel, which has the potential to minimize threshold voltage variation due to
reduced random dopant fluctuations. However, there is little known about carrier mobility in Si nanowire
MOSFETs. Because of the different crystal surface orientations, the nanowire sidewalls are expected to
influence carrier transport. In addition, sidewall roughness due to non-ideal lithography and etch processes
can degrade the carrier transport. Technological performance boosters are thus required to enhance electron
and hole transport. Uniaxial strain engineering and maskless hydrogen thermal annealing are investigated in
this thesis to enhance carrier mobility in gate-all-around nanowire MOSFETs.
Uniaxial tensile stress of about 2 GPa was incorporated for the first time into suspended Si nanowire
channels by a novel lateral relaxation and suspension technique. Gate-all-around strained-Si nanowire nMOSFETs were fabricated with nanowire widths in the range of 8 to 50 nm and 8 nm body thickness,
demonstrating near ideal sub-threshold swing and an enhancement in long-channel current drive and
transconductance of approximately 2X for strained-Si nanowires compared to control Si nanowires. Lowfield effective mobility of these devices was extracted using split capacitance-voltage measurements and the
two-FET method. The analysis indicates electron mobility enhancement for strained-Si nanowires over their
unstrained Si counterparts, as well as over planar SOI, specifically at high inversion charge densities.
However, the mobility of these nanowires was shown to decrease with decreasing nanowire width,
consistent with reported data on unstrained Si nanowires. A simple analytical model was developed to
investigate the contribution of the sidewalls to the nanowire width dependence of the electron mobility.
A new design and process technology was developed to accurately investigate the hole mobility of gate-allaround Si nanowires. A conformal high-κ/metal gate process, enabling uniform gating of the nanowire
perimeter, was combined with a maskless hydrogen thermal anneal to reduce sidewall roughness scattering.
Using this optimized process, long-channel devices with ideal sub-threshold swing (~60 mV/dec) and
enhanced current drive were demonstrated, indicating the excellent quality of the nanowire/high-κ interface
and low-roughness sidewalls. Capacitance-voltage characteristics of sub-micron-long Si nanowires were
accurately measured and verified by quantum-mechanical simulations. Increased effective hole mobility
with decreasing nanowire width was observed down to 12 nm for hydrogen annealed nanowires, attributed
to the smooth, high-mobility non-(100) sidewalls.
Thesis Supervisor: Judy L. Hoyt
Title: Professor of Electrical Engineering
4
To my dear mother, Azam Yazdani, for all her love and dedication
‫ ای ﻤﺎم ﻖ و ﺪا ﮐﺎر ﺶ‬، ‫ ا ﻢ دا ﯽ‬، ‫م‬
‫ﻘﺪ ﻢ ﻣﺎ‬
To my kind aunt, Sima Yazdani, for all the invaluable guidance and
instruction, toward this end and throughout my life
‫ ای ھ ﻪ را ﻤﺎ ﯽ و آ ﻮزش ی‬، ‫ ﻤﺎ دا ﯽ‬، ‫ﺑﺎ ﻢ‬
‫ﺮ ﻖ ا ﻦ ﺪف و ﺮا ﺮ ز ﺪ ﯽ ﻦ‬
5
‫ﻘﺪ ﻢ ﺧﺎ‬
‫ا ﮫﺎ‬
6
Acknowledgments
First of all, I would like to express my sincere respect and deepest gratitude to my principal
research supervisor, Prof. Judy L. Hoyt. During the past five years, Judy was the most influential
person to me. She generously helped me in all the ups and downs I encountered in my research and
student life at MIT. She patiently followed every single step of all my experiments and helped me
troubleshoot the process failures and technical difficulties. I would also like to thank Prof. Dimitri
Antoniadis, for all the technical support and helpful discussions on various projects. In fact, I
learned so much from his extensive experience in semiconductor devices and his deep insight to
the device physics. I’d also like to thank Prof. Tomás Palacios for contributing to and enhancing
the quality of this thesis.
The financial support by the FCRP Materials, Structures, and Devices Focus Center and IBM
Ph.D. Fellowship program is acknowledged. I had a great opportunity to discuss to and get
feedback from many professors and industrial directors through annual reviews and teleseminars.
Over the past five years, I was honored to work and collaborate with many outstanding
students, scientists and research staffs members at various universities and industries. Dr. Michael
Canonico of Freescale and Dr. Christian D. Poweleit of ASU are greatly acknowledged for the
Raman and XRD measurements. I would like to thank Mark Mondol, Joel K.W. Yang and Prof.
Karl K. Berggren for spending many hours with me to develop and improve the quality of e-beam
lithography. Dr. Leonardo Gomez , Gary Riggott and Meekyung Kim are highly acknowledged for
helping me with the epitaxial growth and substrate preparation and analysis. Special thanks to Dr.
Leonardo Gomez for being a great officemate and a trustworthy friend. Many thanks to James T.
Teherani who helped me with the device simulations and being a nice friend during my summer
internship at IBM.
Moving this project forward was not possible without assistance and guidance of many staffs at
MIT Microsystems Technology Laboratories who helped me bringing new materials and processes
7
to the Integrated Circuits Lab. I would like to acknowledge Vicky Diadiuk, Paul Tierney, Bernard
Alamariu, Eric S. Lim, Robert Bicchieri, Donal Jamieson, Paudely Zamora, Dan Adams, Kurt
Broderick, and Dennis Ward for trainings and troubleshooting the machines. I am thankful to my
fellow lab members past and present: Dr. Hyung-Seok Lee, Dr. Ingvar Åberg, Dr. Ali Khakifirooz,
Dr. John Hennessy, Dr. Osamah Naygeh, Dr. Andrew Ritenour, Nicole Dilello, Dr. Kevin Ryu, Dr.
Jongwoo Joh, Will Chung, Dr. Daehyun Kim, Dr. Luis Fernando Velásquez-García, Stephen A.
Guerrera, Bin Lu, Omair Saadat, Dr. Jae-kyu Lee, Dr. Ryan Lei, Kevin McComber, Jing Cheng
and Jerome Jianqiang Lin. I acknowledge them for valuable conversations and assisting me with
design of new processes. Special thanks to Leo, Will, Jing, Kevin, Jerome, Kevin, Bin and Joel for
being my lab buddy on weekends and after hours.
I would also like to express my gratitude to Judy’s assistants in the past and present: Rose
Previte, Michele Hudak, and Whitney Rokui. They were great help with administrative tasks. I
would also like to acknowledge the MTL’s administrative staffs and specialists: Deborah HodgesPabon, Pat Varley, Samuel Crooks, Mara Karapetian, and Michael McIlrath. I am also thankful to
the staffs at Department of Material Science and Engineering of MIT: Dr. Yong Zhang, for training
me on TEM and SEM, Libby Shaw for training me on AFM and Dr. S. J. Chen for training me on
the new FIB machine.
I am truly indebted and thankful to my former research Supervisor, Prof. Shams Mohajerzadeh
who motivated me with the world-class research in the field of microelectronic devices. I would
like to show my gratitude to Dr. Ghavam G. Shahidi, Dr. Devendra Sadana, and Dr. Davood
Shahrjerdi for mentoring and supporting me with the industrial research at IBM.
I am heartily thankful to my mother for all her love and dedication and my aunt, for all the
invaluable guidance and instruction, toward this end and throughout my life. My siblings Kousha
and Dena for continuous love and encouragement. Special thanks to my uncles, Dr. Ali and Akbar
Yazdani for all the generous financial and mental supports throughout my life. Finally, I’d like to
thank my love, Azadeh, for bringing happiness to my life and for all the wonderful moments we
had together during the past year.
8
Contents
List of Figures...................................................................................................................................... 13
List of Tables ....................................................................................................................................... 25
Chapter 1: Introduction ................................................................................................................... 27
1.1 Thesis Introduction and Motivation ....................................................................................... 27
1.2 Thesis Outline ......................................................................................................................... 31
Chapter 2: Thesis Background ........................................................................................................ 33
2.1 Introduction to Multi-Gate Devices ....................................................................................... 33
2.2 Scaling Theory of MOSFETs and Advantages of Nanowires .............................................. 36
2.3 Carrier Transport and Scattering Mechanisms....................................................................... 40
2.3.1 Mobility and Velocity ............................................................................................. 40
2.3.2 Scattering Mechanisms ........................................................................................... 43
2.3.2.1 Coulombic Scattering .............................................................................. 44
2.3.2.2 Surface Roughness Scattering ................................................................ 45
2.3.2.3 Phonon Scattering and Confinement ....................................................... 46
2.3.2.4 Thickness Fluctuation Scattering ............................................................ 50
2.3.2.5 Remote Phonon Scattering ...................................................................... 51
2.4 Transport Enhancements Options for Multi-gate MOSFETs................................................ 54
2.4.1 Surface Crystallographic Orientation and Channel Direction ............................... 54
2.4.2 Strain Engineering ................................................................................................... 57
2.4.3 Technological Implementation: New Materials and Processes ............................. 61
2.5 Mobility Extraction for Gate-All-Around Nanowires MOSFETs ........................................ 63
2.6 Chapter Summary ................................................................................................................... 70
Chapter 3: Asymmetrically Strained-Si and Ge Channels .......................................................... 73
9
3.1 Biaxial to Uniaxial Strain Transformation ............................................................................. 73
3.2 Asymmetrically Strained-Ge Nano-Bars ............................................................................... 75
3.2.1 Fabrication and Metrology ...................................................................................... 75
3.2.2 Strain Characterization ............................................................................................ 76
3.3 Suspended Uniaxially Strained-Si Nanowires ....................................................................... 79
3.3.1 Fabrication of Strained-Si Nanowires .................................................................... 79
3.3.2 Raman Characterization and Stress Mapping......................................................... 80
3.3.3 Vertically-Stacked Strained-Si Nanowires ............................................................. 85
3.4 Chapter Summary ................................................................................................................... 88
Chapter 4: Gate-All-Around Uniaxially Strained-Si Nanowire n-MOSFETs .......................... 89
4.1 Introduction ............................................................................................................................. 89
4.2 Device fabrication and Metrology .......................................................................................... 90
4.3 Electrostatics and Threshold voltage ...................................................................................... 93
4.4 Performance Evaluation.......................................................................................................... 96
4.5 Mobility Characterization ....................................................................................................... 99
4.5.1 Split CV Measurements .......................................................................................... 99
4.5.2 Electron Mobility .................................................................................................. 102
4.5.3 Width Dependence of Electron Mobility.............................................................. 104
4.5 Chapter Summary ................................................................................................................. 109
Chapter 5: Device Design and Process Technology for Gate-All-Around Si Nanowire pMOSFETs......................................................................................................................................... 111
5.1 Introduction ........................................................................................................................... 111
5.2 Device Design for Accurate Mobility Extraction ................................................................ 112
5.3 Hydrogen Anneal Process .................................................................................................... 117
5.4 High-κ/Metal Gate Process................................................................................................... 122
5.4.1 ALD Al2O3/WN Stack with O3 Surface Passivation ........................................... 123
5.4.2 Planar SOI Mobility .............................................................................................. 125
5.4.3 Tungsten Nitride (WN) Workfunction ................................................................. 126
10
5.5 Chapter Summary ................................................................................................................. 127
Chapter 6: Hole Transport in Gate-All-Around Si Nanowire p-MOSFETs ........................... 129
6.1 Introduction and Process Splits ............................................................................................ 129
6.2 Device Characteristics .......................................................................................................... 130
6.2.1 Drain Current and Electrostatics ........................................................................... 130
6.2.2 Performance Enhancement by Hydrogen Anneal ................................................ 132
6.3 Hole Mobility Characterization ............................................................................................ 134
6.3.1 Capacitance Measurements and Mobility Extraction .......................................... 134
6.3.2 Charge Distribution and Capacitance Simulations .............................................. 135
6.3.3 Hole Mobility Investigation .................................................................................. 138
6.3.3.1 Nanowires without Hydrogen Anneal................................................... 139
6.3.3.2 Nanowires with Optimized Hydrogen Anneal (Condition B) .............. 140
6.3.3.3 Nanowires with Non-Optimized hydrogen Anneal (Condition C) ...... 143
6.3.4 Width Dependence of Hole Mobility ................................................................... 144
6.4 Chapter Summary ................................................................................................................. 148
Chapter 7: Summary and Suggestions for Future Work........................................................... 151
7.1 Thesis Summary.................................................................................................................... 151
7.2 Suggestions for Future Work................................................................................................ 155
7.3 Contributions ......................................................................................................................... 156
Appendix A: E-beam Lithography with Hydrogen Silsesquioxane Negative-Tone Resist.... 157
A.1 Hydrogen Silsesquioxane Negative-Tone Resist ................................................................ 157
A.2 Hybrid Lithography ............................................................................................................. 162
A.3 Fabrication Process for Ultra-Dense Si Nanowires ............................................................ 164
Appendix B: Raman Spectroscopy of Strained-Si Nanowires .................................................. 167
B.1 Raman Characterization of Suspended Nanowires ............................................................. 167
B.2 Raman Characterization of Ultra-Dense Strained-Si Nanowires ....................................... 169
11
Appendix C: Fabrication Flow and Stress Characterization of Vertically-Stacked Strained-Si
Nanowires ......................................................................................................................................... 173
C.1 Starting Substrates ................................................................................................................ 173
C.2 Fabrication Steps .................................................................................................................. 176
Appendix D: Process Flow for Gate-All-Around Si (Strained-Si) Nanowire n-MOSFETs .. 177
D.1 Fabrication Flow .................................................................................................................. 177
D.2 Gate-Alignment and Stringer Etch ...................................................................................... 180
Appendix E: Process Flow for Gate-All-Around Si Nanowire p-MOSFETs with Highκ/Metal Gate Process ...................................................................................................................... 183
E.1 Fabrication Flow................................................................................................................... 183
E.2 Polycrystalline-Si/WN Gate Stack....................................................................................... 186
Appendix F: Si/Ge Core-Shell Nanowire p-MOSFETs .............................................................. 189
F.1 Fabrication of Si/Ge Core-Shell Nanowire p-MOSFETs.................................................... 189
F.2 Electrical Characterization and Mobility Calculation ......................................................... 191
F.3 Appendix Summary .............................................................................................................. 195
Bibliography..................................................................................................................................... 197
12
List of Figures
Figure 2.1:
Schematic diagram of (a) planar ultra-thin-body SOI, (b) double-gate FinFET, (c)
Tri-gate FET and (d) gate-all-around nanowire FET, viewing in a direction
perpendicular to the current transport, representing the evolution of nanowire FET
from an ultra-thin-body SOI FET. The required criterion on the Si thickness (tSi) for
a given gate length (LG) to have acceptable electrostatics is also shown, indicating
more relaxed channel dimension available for nanowire FET (compared to other
architectures) to be considered as a candidate for a given technology node. ........... 35
Figure 2.2:
Universal dependence of (a) subthreshold slope and (b) drain-induced-barrierlowering (DIBL) on the scaling parameter, for gate-all-around and double-gate
MOSFETs with various oxide and Si thicknesses. Data from Ref. [44]. ................. 37
Figure 2.3:
(a) Capacitance circuit model and conduction band profile of a MOSFET,
introducing the capacitances of source (Cs), drain (Cd) and oxide (Cox) as well as
surface channel charge (Qch) [46, 47]; (b) Simplified capacitance model of the gate
of a MOSFET (CG), displaying the physical oxide thickness (Cox) and the quantum
capacitance (CQ). .......................................................................... ............................ 39
Figure 2.4:
Schematic sub-band structures of two-dimensional electrons for bulk and ultra-thinbody SOI MOSFETs. Structural confinement of the inversion layer in ultra-thinbody SOI MOSFETs decreases the average thickness of the inversion layer (Zav) as
well as phonon-limited mobility and increases the inversion layer capacitance and
threshold voltage (After Uchida et al. [63]). ................................ ............................ 50
Figure 2.5:
Schematic of (left) interface-roughness induced thickness fluctuation scattering and
(right) variation of conduction band due to thickness fluctuation scattering in ultrathin-body SOI channels (After Ref. [64])..................................... ............................ 51
Figure 2.6:
(a) Calculated effective electron mobility of Si inversion layers of MOS system
with insulators indicated. Remote scattering with surface optical phonons,
anisotropic scattering with acoustic phonons and empirical scattering with surface
roughness have been considered (b) Calculated total electron mobility in the
13
inversion layer of a HfO2 /SiO2 /Si system as a function of thickness of the
interfacial SiO2 layer for the three indicated values of the electron concentration in
the inversion layer. The horizontal lines at the far right are the asymptotic limits of
infinite oxide thickness (Results from Fischetti et al. [70]). ........ ............................ 53
Figure 2.7:
Effective electron and hole mobility of Si as a function of inversion charge density
for (100), (111) and (110) surfaces. Mobility is isotropic (direction independent) for
(100) and (111) surfaces. Among all surface/directions, (100) and (110)/<110>
have the highest electron and hole mobility, respectively (Results from Irie et al.
[73]). .............................................................................................. ............................ 55
Figure 2.8:
(a) Schematic of Si conduction band’s equienergy ellipsoids, displaying Δ2 and Δ4
valleys; (b) Equienergy valleys of Si on (110) surface. Four valleys with heavy ml
and two valleys with light mt contribute to the conduction along <110> direction;
(c) Equienergy valleys of Si on (100) surface. Two valleys with heavy ml and four
valleys with light mt contribute to the conduction along <100> or <110> direction,
offering lower conductivity mass compared to (110) surface. .... ............................ 56
Figure 2.9:
(Top) energy and (bottom) equienergy lines of the lowest-lying subbands (HH, LH
and SO) along with the position of the Fermi level for (001), (011) and (111)
relaxed Si surfaces. Spin degeneracy is lifted away from the center of the zone, so
that the density of states given subband depends on spin variables (Results from
Fischetti et al. [65]). ...................................................................... ............................ 56
Figure 2.10: Schematic of electron repopulation in the conduction band equienergy valleys of (a)
(100) Si under <110> uniaxial or biaxial tension, (b) (110) Si under biaxial tension
and (c) (110) Si under <110> uniaxial tension. The current direction for all cases is
along <110>, which is favorable for all cases except case (b) where its mobilityenhanced direction is shown. ........................................................ ............................ 58
Figure 2.11: (a) Relative change in the Si effective mass in the direction parallel and
perpendicular to a [110] uniaxial tension (open symbols: tight binding [82], filled
symbols empirical pseudopotential [82], solid lines: empirical pseudopotential
[83]); (b) Relative change in Si electron ballistic velocity vs. relative change in
mobility for different strains (Results from Khakifirooz et al. [82]). ....................... 59
Figure 2.12: Simulated hole and electron mobility for (100) and (110) silicon substrates as a
function of uniaxial stress along <110> (Results from Packan et al. [74]). ............. 61
Figure 2.13: Schematic of the nano-patterning induced lateral relaxation mechanism. Arrows
with solid border show the direction of the strain and arrows with dashed line
14
shows the lateral relaxation direction. Biaxial stress is preferentially relaxed in the
transverse (lateral) direction. ........................................................ ............................ 63
Figure 2.14: (a) Effective hole mobility vs. inversion charge density (Ninv) for various voltage
shift between capacitance and current measurements (ΔV) due to several
mechanisms such as measurement stress effects; (b) Relative mobility error (with
respect to the case with no shift) as a function of ΔV, for Ninv=1012, 4×1012 and
7×1012 cm-2. While large error is observed for low Ninv, the error is less than 2% at
high inversion charge densities. .................................................... ............................ 66
Figure 2.15: (a) Measured capacitance of planar SOI MOSFETs with Al2O3/WN gate using split
C-V method for devices with mask gate length, Lmask = 0.4, 0.6, 0.8, 1, 1.2, 1.6 and
2 μm. For Lmask = 0.4 μm, the parasitic component (Cpar) contributes to about a
quarter of the total measured capacitance. (b) Plot of maximum capacitance (Cmax)
and the minimum parasitic capacitance (Cpar, min) vs. Lmask. Symbols are measured
data and solid lines are the best fits to the measured data. The difference of the
mask length and the effective gate length (ΔL) was extracted by intersecting the
two fitted lines. ............................................................................. ............................ 68
Figure 2.16: (a) Schematic of the gate-all-around nanowire test structures for effective mobility
extraction, utilizing two FETs with the same number of nanowire (N) and similar
cross-section (central schematic), similar parasitic resistance (i.e. similar contact
design rules and S/D materials) and capacitance (i.e. similar fringing, gate-to-pad
and gate-to-source/drain overlaps)................................................ ............................ 69
Figure 3.1:
Schematic process flow of modified bond and etch-back technique to fabricate
biaxial tensile SSDOI or compressive Ge HOI, after Gomez, et al. [129]............... 74
Figure 3.2:
Schematic diagram of fabrication of highly asymmetric, virtually uniaxial, strainedSi and strained-Ge nano-structures by unilateral relaxation of SSDOI and Ge HOI
substrates. ...................................................................................... ............................ 74
Figure 3.3:
(a) Cross-sectional TEM image of strained-Ge HOI substrate. Tilted SEM images
of (b) 100 nm and (c) 30 nm wide patterned strained-Ge HOI nano-bars prepared
for stress metrology by UV micro-Raman spectroscopy (TEM Courtesy of M.D.
Robertson). .................................................................................... ............................ 76
Figure 3.4:
(a) Raman spectra (325nm excitation) of the Ge LO phonon with overlaid
Lorentzian fit for Ge HOI sample patterned into 30 nm, 50 nm, 100 nm and 300
nm-wide stripes. Dashed line is the signal from the relaxed Ge reference sample.
For clarity, the Raman spectra and corresponding analytical fit are shifted vertically
15
relative to one another (Raman courtesy of M. Canonico (Freescale)); (b) Extracted
biaxial relaxation (solid lines) and Raman peak position (dashed lines) vs. bar width
in strained-Ge layer. ..................................................................... ............................ 77
Figure 3.5:
Schematic process flow of suspended strained-Si nanowires: (a) after spinning ebeam resist, (b) after resist development and strained-Si reactive-ion etching, (c)
after nanowire suspension in dilute HF, and (d) top-down view. (e) Tilted SEM
image of the 20 nm wide strained-Si nanowires in a 100 nm pitch; (f) Tilted SEM
image of the 18 nm wide ultra-dense strained-Si nanowires in a 40 nm pitch (inset:
top view SEM)............................................................................... ............................ 80
Figure 3.6:
(a) Raman spectra (courtesy of M. Canonico (Freescale)) of the Si LO phonon from
unstrained bulk Si (dashed line) and the 40 μm square box (solid line). The
measured Si peak shift is consistent with the strain expected in Si grown on a
relaxed SiGe donor substrate with 30% Ge concentration. (b) Raman spectra at the
center of suspended strained-Si nanowires (30 nm wide), displaying two peaks
corresponding to bulk Si substrate (right) and nanowires (left) with a ~2.1 GPa
uniaxial tension along the nanowires............................................ ............................ 81
Figure 3.7:
(a) Raman spectra (courtesy of M. Canonico (Freescale)) of the Si-Si LO phonon
mode for 30 nm wide suspended strained-Si nanowires with pads attached to the
oxide, as the laser is scanned from pad to pad in a direction parallel to the nanowire
length , as shown in the schematic (b). ......................................... ............................ 82
Figure 3.8:
Total in-plane stress (circles, left axis) and corresponding signal-to-noise ratio
(squares, right axis) for spectra collected from the 2 μm long nanowires midway
between the two pads. ................................................................... ............................ 84
Figure 3.9:
(a)-(c) Schematic of the process flow utilized to realize vertically stacked strainedSi nanowires; (d) top view of the stacked-Si nanowires highlighting the region
where Raman signal was collected; (e) SEM images of N = 1 to 5 level verticallystacked strained-Si nanowires. ...................................................... ............................ 86
Figure 3.10: (a) Raman spectra (courtesy of C. D. Poweleit, ASU) of at the center of array of
suspended strained-Si nanowires with (WNW = 30 and 35 nm, and N = 1 and 5
number of stacked layers); (b) Biaxial strain relaxation (with starting substrates as
reference) vs. number of nanowires as a function of nanowire width, indicating
stress preservation after 5 layer stacking of nanowires. ............... ............................ 87
Figure 4.1:
(a) Fabrication process flow of gate-all-around uniaxial strained-Si nanowire nMOSFETs. (b) Top-view and (c) side-view schematic of suspended uniaxially
16
tensile strained-Si channel fabricated by lateral relaxation and undercutting the
nanowires. Inset shows the nanowire dimensions and stress direction. ................... 90
Figure 4.2:
(a) Sample tilted SEM image of suspended strained-Si nanowires. (b) Top-view
colored SEM image of gate-all-around strained-Si nanowire n-MOSFET with 10
parallel nanowires. The poly-Si/LTO gate stringers at the edge of ion-implanted
source/drain pads were etched using a separate protection mask. ............................ 92
Figure 4.3:
Cross-sectional TEM of gate-all-around n-MOSFETs with (a) elliptical and (b)
circular cross-section strained-Si nanowires. The focused-ion-beam cut is
perpendicular to the nanowire direction (electron transport direction). Heavilydoped poly-Si gate and low-temperature oxide wraps all around the Si
nanowires…................................................................................... ............................ 93
Figure 4.4:
Typical (a) transfer (ID - VGS) and (b) output characteristics (ID - VDS) for a circular
cross-section gate-all-around strained-Si nanowire n-MOSFET with N = 10
nanowires, average nanowire diameter of ~ 8 nm, and LNW ~ 0.65 μm. For (a), the
left axis shows the current in logarithmic scale while the right axis shows it in linear
scale. .............................................................................................. ............................ 94
Figure 4.5:
(a) Plot of subthreshold slope as a function of WNW and LNW for SSOI nanowires
with low-temperature oxide (LTO) and thermal oxide gate dielectrics showing near
ideal subthreshold swing. (b) Variation of threshold voltage (Vth) vs. WNW for SOI
and SSOI nanowires showing Vth shift of -120 ± 30 mV due to uniaxial straininduced conduction band shift. The Vth roll-up for sub 15 nm nanowires is due to
quantum mechanical confinement. ............................................... ............................ 95
Figure 4.6:
Transfer characteristics of gate-all-around Si and strained-Si nanowire n-MOSFETs
(with LTO gate dielectric) showing near ideal subthreshold slope of 65 mV/dec.
and ~2X current enhancement and ~ 0.1 V strain-induced Vth shift. ....................... 96
Figure 4.7:
(a) Extrinsic transconductance (gm) of SOI and SSOI Gate-all-around nanowires vs.
overdrive voltage (VGS-Vth) for nanowires with WNW  20 nm, tNW = 8 nm. SSOI
NW exhibits a 1.95X enhancement in gm, max relative to SOI nanowire devices. The
enhancement at higher overdrives is degraded by increased contribution of the
external resistance. ........................................................................ ............................ 97
Figure 4.8:
(a) Plot of total channel resistance vs. 1/(VGS-Vth-VDS/2) to extract external series
resistance (Rext) for SOI and SSOI nanowires vs. VGS-Vth (WNW  20nm, tNW =
8nm, N = 10). Rext (shown in the figure) is extracted from the intersect of the
extrapolated curve with the vertical axis. (b) Intrinsic transconductance of these
17
devices after correction for Rext. Enhancement factors of 2.1X at maximum gm and
1.86X at VGS-Vth = 0.7 V are due to the uniaxial strain. .............. ............................ 98
Figure 4.9:
Intrinsic gm, max (VDS = 50 mV) vs. WNW for SOI and SSOI gate-all-around devices
with LNW = 0.8 μm, tNW ~ 8 ± 1 nm and N = 10, displaying an average enhancement
in gm, max of ~2X down to sub-10 nm nanowire dimensions. ....... ............................ 99
Figure 4.10: Split capacitance-voltage characteristics of an SSOI nanowire n-MOSFETs (N =
10, WNW ~ 49 nm, tNW ~ 8 nm, LNW = 10 µm) measured at f = 40 kHz and 40X
point averaging to minimize the noise. The gate-channel capacitance (Cgc) was
extracted by subtracting the parasitic capacitance, Cpar, (background and overlap
capacitance, measured from devices without nanowires but with gate overlap on the
S/D regions) was subtracted from the total capacitance (Ctot). (b) Cgc vs. VGS for
SSOI nanowire n-MOSFETs (N = 10, WNW ~ 39 nm, tNW ~ 8 nm, LNW = 10 µm)
extracted at f = 40 kHz and f = 1 MHz. ....................................... .......................... 100
Figure 4.11: Intrinsic gate-channel capacitance-voltage of gate-all-around SSOI nanowires with
WNW = 25, 39, 49 nm. The background and overlap capacitances were subtracted
from the original split-CV. 40 point averaging was used to reduce the noise........ 101
Figure 4.12: (a) Gate-channel capacitance and (b) total channel resistance of SSOI nanowire nMOSFETs (N = 10, WNW ~ 49 nm, tNW ~ 8 nm) with LNW = 10 µm (C1) and LNW = 4
µm (C2) used to extract the mobility using 2-FET method. The extracted Rext is also
shown in (b) ................................................................................... .......................... 102
Figure 4.13: Low-field electron mobility (μeff) vs. charge density (Ninv) of SSOI NW (WNW = 49
nm, tNW = 8.7 nm) measured by split-CV and 2-FET method. μeff for the widest SOI
NW (W = 44nm), planar SOI and SSDOI (tSi = 8.7 nm) (11), and universal are
shown for comparison. .................................................................. .......................... 103
Figure 4.14: Low-field electron mobility (μeff) vs. charge density (Ninv) with WNW ~ 15, 20, 25,
39, 49 nm. The electron mobility plot of fully-depleted ultra-thin-body (8 nm) SOI
is shown for comparison [67]. Mobility is reduced as WNW is decreased, mostly due
to an increase in the contribution of the sidewalls. ...................... .......................... 104
Figure 4.15: (a) Electron mobility for SSOI NWs vs. (a) WNW and (b) the ratio of sidewall to
surface (Wsidewall/Wsurarface , as schematically shown in the inset) at Ninv = 1013 cm-2.
Overlaid are the mobilities of unstrained-Si nanowires (empty triangles: Ref. [23],
empty squares: Ref. [121]). ........................................................... .......................... 105
Figure 4.16: Electron mobility of for SSOI NWs (solid symbols) and SOI NWs (open symbols,
[121]) vs. WNW at Ninv = 1013 cm-2. Lines are the empirical model with rμ = 0.34,
18
0.2 and 0.15 (with rμ decreasing in the direction of the arrow) for SSOI NWs and rμ
= 0.35 and 0.2 for SOI NWs ......................................................... .......................... 107
Figure 5.1:
Process flow utilized to fabricate gate-all-around nanowire p-MOSFETs with highK/metal gate and hydrogen annealing process. ............................ .......................... 113
Figure 5.2:
(a) Schematic of the protection mask to locally release the Si nanowires. (b)
Schematic of the suspended Si nanowires after local release in buffered-oxide-etch,
demonstrating no space available for gate-stringer at source/drain edges. (c)
Schematic of design layout of the Si nanowire MOSFETs, displaying the contact
vias, gate-to-pad overlap (< 100 nm), distance between contact via and the gate
edge (dvia-gate< 400 nm), and between contact via and metal edge (dvia-metal< 400
nm). ................................................................................................ .......................... 114
Figure 5.3:
Schematic device structure of the gate-all-around nanowire MOSFETs designed for
mobility extraction. A-A’ and B-B’ cut-lines represent the device cross-sections
perpendicular and along the nanowire direction, respectively. Device dimensions
(WNW, Wtot, tNW, LNW, Lov and N), channel resistance (RNW and Rov) and capacitive
(Cpar) and resistive (Rext) parasitics are shown on the B-B’ cross-section.............. 115
Figure 5.4:
(a) Tilted and (b) cross-sectional SEM images of the final gate-all-around nanowire
p-MOSFETs with high-κ/metal-gate, with a FIB cut along the suspended nanowire
direction. ........................................................................................ .......................... 116
Figure 5.5:
(a) Schematic and (b) top-view SEM of suspended Si nanowires before and after
high-temperature hydrogen annealing. The right SEM images were enhanced for
brightness, contrast and shadows to magnify the line edge roughness of the Si
nanowires. Reduced sidewall roughness is observed after hydrogen annealing. ... 118
Figure 5.6:
(a) Plan-view SEM images of suspended Si nanowires subjected to hydrogen
anneal at 850°C, with WNW = 14-73 nm; (b) XTEM of on-wafer nanowire test
structure (as-patterned WNW = 20 to 60 nm; step 4 nm) subjected to hydrogen
anneal at 850°C, after device completion. Nanowires are surrounded by conformal
~1 nm ALD O3-SiO2 / 5.5 nm Al2O3 / 30 nm WN gate stack (stack κ = 7.4). For
wide nanowires, tNW = 16 nm; dropping to 13 nm for the circular nanowire. (110),
(111) and (311) sidewall facets are discernible from the XTEM images............... 119
Figure 5.7:
SEM image of array of nanowire test structure (a) as-patterned, (b) after hydrogen
annealing at 875°C and (c) after hydrogen annealing at 900°C. Anisotropic
hydrogen etching and nanowire pinch-off at the pad/nanowire boundaries are
observed for annealing at temperatures higher than 875°C. ........ .......................... 121
19
Figure 5.8:
High-resolution Focused-Ion-Beam (FIB) cross-sectional SEM image of a
nanowire test structure (with as patterned WNW = 20 to 60 nm; step 4 nm) subjected
to hydrogen anneal at 850°C followed by 875°C, after device completion.
Nanowire diameters (dNW, as defined in the SEM image) are scaled from 22 nm
down to sub-10 nm, mostly with circular cross sections. ............ .......................... 122
Figure 5.9:
(a) Split capacitance-voltage characteristics of SOI p-MOSFETs with 7 cycles of
ALD O3, 60 cycles of Al2O3 and WN metal gate, measured at f = 1, 10 and 100 kHz
; The Al2O3 dielectric was deposited using Tri-Methyl-Aluminum (TMA) source at
200°C. (b) Corresponding forward and backward sweeps at f = 100 kHz, showing
80 mV hysteresis ........................................................................... .......................... 124
Figure 5.10: (a) Split capacitance-voltage characteristics of SOI p-MOSFETs with 7 cycles of
ALD O3, 55 cycles of Al2O3 and WN metal gate, showing negligible frequency
dependence at f = 1, 10 and 100 kHz; The Al2O3 dielectric was deposited using TriMethyl-Aluminum (TMA) source at 250°C. (b) Corresponding forward and
backward sweeps at f = 100 kHz, showing no hysteresis. ........... .......................... 125
Figure 5.11: Effective hole mobility vs. inversion charge density (Ninv) for planar SOI devices
with ALD O3-SiO2 / Al2O3 / WN process. Al2O3 was deposited using Tri-MethylAluminum (TMA) at 200°C and 250°C and Tris-Di-Methyl-Amido-Aluminum
(TDMAA) at 200°C. ..................................................................... .......................... 126
Figure 5.12: (a) Schematic of the test structure used to extract the WN workfunction; (b) Plot of
flatband voltage (VFB) vs. capacitance effective thickness (CET) for
WN/Al2O3/SiO2/Si stack as the thickness of the SiO2 is varied. . .......................... 127
Figure 6.1:
(a) Transfer and output characteristics of gate-all-around ~15 nm-diameter
nanowire (LNW = 0.6 µm, N = 500) p-MOSFETs with high-K/metal gate and
hydrogen anneal process, showing ideal sub-threshold slope of 61 mV/dec and very
high on-to-off ratio. ....................................................................... .......................... 131
Figure 6.2:
(a) Subthreshold slope (SS) and (b) threshold voltage (Vth) as a function of WNW for
gate-all-around p-MOSFETs with Al2O3/WN gate stack. All devices show ideal
swing (with a minimum of 60.5 mV/dec for 15 nm circular NW), indicating very
low Dit. ........................................................................................... .......................... 132
Figure 6.3:
Transfer characteristics of 22×15.6 nm gate-all-around nanowire p-MOSFETs (with
N = 500 nanowires) treated with hydrogen anneal at 850°C (condition B) and
without hydrogen anneal (condition A), indicating ideal SS = 61 mV/dec and very
20
high on-to-off ratio (~1010). No hysteresis was observed in the transfer
characteristics. ............................................................................... .......................... 133
Figure 6.4:
Plots of (a) ID vs. gate over-drive voltage (VGS-Vth) and (b) ID vs. VDS for VGS-Vth =
-2 V to 0 V step -0.25 V, for 22×15.6 nm gate-all-around nanowire p-MOSFETs
with hydrogen anneal at 850°C (condition B) and without hydrogen anneal
(condition A), indicating ~1.6X enhancement for linear and saturation current due
to the hydrogen anneal process (condition B). ............................. .......................... 134
Figure 6.5:
Typical split-CV and ID-VGS measurements of 15 nm-diameter circular nanowire
(with LNW= 0.6 and 1.2 µm) for mobility extraction using the 2-FET method. Drain
current was measured at VDS = -50 mV. Current and capacitances are normalized
by the number of nanowires (N = 500). ....................................... .......................... 135
Figure 6.6:
Simulated (nextnano3) hole charge density in nanowires with (a) circular (15.6×14
nm, dNW~15 nm) and (b) elliptical (22×15.7 nm) and cross-sections for VGS-VFB = 1.3 V. Inversion centroid is displaced from nanowire surface by the distance
δQM(VGS). Simulation courtesy of J. Teherani.. ............................ .......................... 136
Figure 6.7:
Measured and nextnano3 simulated inversion capacitance of 15 nm-diameter
circular and 22 nm×15.6 nm elliptical nanowires, demonstrating very good
agreement between measured and simulated results, verifying mobility extraction
method. Only physical dimensions (derived from TEM), κ (extracted from planar
CV measurements) and Qf were input into the simulations. The upper and lower
simulated curves correspond to a metal with high and low density of states,
respectively. Simulation courtesy of J. Teherani. ........................ .......................... 137
Figure 6.8:
Measured (symbols) and simulated (lines) intrinsic capacitances for nanowires
annealed at 875°C (condition C) with nanowire diameter, dNW = 8-17 nm. dNW was
measured by high-resolution cross-sectional SEM and was input into the
simulations for 12 and 17 nm nanowires. For sub-10 nm nanowires, the effective
circular diameter (dNW,eq) was extracted by fitting simulations to the CV
measurements. Simulation courtesy of J. Teherani. ..................... .......................... 138
Figure 6.9:
Effective hole mobility vs. inversion charge density (Ninv, normalized by nanowire
circumference) for nanowires with WNW = 22-72 nm, without hydrogen anneal.
Similar mobilities are observed at high Ninv for various WNW, with a ~20 % drop
compared to planar (100) SOI device. .......................................... .......................... 139
Figure 6.10: (a) Effective hole mobility vs. Ninv (normalized by nanowire circumference) for
nanowires with WNW = 15-72 nm subjected to hydrogen anneal at 850°C (condition
21
B). Monotonic mobility enhancement with decreasing nanowire width is observed,
due to increased contribution of high-mobility sidewalls and reduced sidewall
roughness scattering. Mobility is enhanced by 47% relative to the widest nanowire
and 33% over planar (100) SOI device at Ninv=1.1×1013cm-2. (b) Hole mobility vs.
Ninv for 15 nm circular nanowires demonstrating mobility enhancement over planar
SOI and the highest mobility of nanowires without hydrogen anneal. Significant
enhancement is seen relative to published data for sub-15 nm thickness
nanowires…................................................................................... .......................... 140
Figure 6.11: Hole mobility vs. Ninv, normalized by nanowire physical perimeter (dashed line)
and with quantum-mechanical (QM) correction (symbols) for circular (15.6×14 nm,
dNW ~ 15 nm) and elliptical (22×15.7 nm) nanowires. The QM correction to the
perimeter was calculated using simulations at each gate bias. .... .......................... 141
Figure 6.12: (a) Transfer characteristics of gate-all-around nanowire p-MOSFETs (with dNW ~ 8,
10, 12, 17, 22 nm and LNW = 0.6 µm subjected to non-optimized hydrogen anneal
(condition C). Non ideal swings (>80 mV/dec) suggest that nanowires have high
density of interface traps due to non-optimized condition C. ...... .......................... 142
Figure 6.13: Plots of effective hole mobility vs. inversion charge density, for nanowires with (a)
WNW = 12-32 nm and (b) WNW < 12 nm subjected to non-optimized hydrogen
anneal (condition C). Mobilities are generally reduced due to high density of
interface traps of condition C. ....................................................... .......................... 143
Figure 6.14: Width-dependence of hole mobility for nanowires with and without hydrogen
anneal, at Ninv= 5×1012 and 1013 cm-2. Flat mobility behavior is observed without
hydrogen anneal due to a balance between high-mobility non-(100) planes and
sidewall roughness scattering. The latter mechanism is significantly diminished
with hydrogen anneal (condition B), and more than 57% enhancement is observed
for WNW < 22 nm. .......................................................................... .......................... 144
Figure 6.15: Hole mobility of Si nanowires vs. WNW at Ninv = 1013 cm-2. Symbols correspond to
the experimental results. Lines are the empirical model with μs = 70 cm2/V.s and rμ
= 1.95 (dot-dashed line), μs = 50 cm2/V.s and rμ = 1.95 (solid line), and μs = 70
cm2/V.s and rμ = 0.9-1.42 (dot-dashed line) to fit the experimental data. .............. 145
Figure 6.16: Hole mobility in Si nanowires subjected to hydrogen anneal at 875°C (condition C)
vs. nanowire diameter (width) for Ninv = 5×1012 and 1013 cm-2. Increased mobility is
observed by reducing dNW to 12 nm diameter (elliptical to circular shape transition),
while the mobility of sub-12 nm circular nanowires is reduced as dNW is
decreased... .................................................................................... .......................... 147
22
Figure 6.17: Comparison of the normalized hole mobility (at Ninv = 1013 cm-2) vs. nanowire
width, for various post-suspension treatments. Mobilities are normalized by the
mobility of on-chip planar SOI p-MOSFET, extracted for each process condition.
Similar normalized mobilities are observed for hydrogen annealed nanowires
processed at conditions B and C, in the common range of WNW. .......................... 148
Figure A.1: Plot of relative remaining Hydrogen Silsesquioxane (HSQ) thickness vs. exposure
dose for HSQ on HOI samples exposed at 10 keV and 30 keV. Both samples were
prebaked at 90°C for 4 minutes and developed with 25 wt. % TMAH for 1 minute.
While similar contrast is observed, higher dose is required to expose HSQ at energy
of 30 keV. ...................................................................................... .......................... 158
Figure A.2: Contrast curve for 4% XR-1541 Hydrogen Silsesquioxane (HSQ) exposed at 30 keV
and developed in 0.26N TMAH and 25 wt. % TMAH at the room temperature. The
contrast is significantly enhanced using 25 wt. % TMAH. ......... .......................... 160
Figure A.3: Contrast curve for 4% XR-1541 Hydrogen Silsesquioxane (HSQ) prebaked at 200°C
and 90°C for 2 minutes, exposed at 30 keV and developed in 25 wt. % TMAH for 1
minute. While similar contrast is observed, prebaking at 90°C has a wider exposure
window. ......................................................................................... .......................... 160
Figure A.4: (a) Typical plan-view SEM image of 20 nm-wide 4% XR-1541 Hydrogen
Silsesquioxane (HSQ) line and (b) corresponding line edge profile. HSQ was
developed in 25 wt % TMAH for 60 seconds. (c) Tilted SEM image of HSQ lines
(various width) on Si wafer after Si etch and (d) magnified cross-sectional SEM of
17.3 nm HSQ line (with an aspect ratio of ~5) on a Si fin........... .......................... 161
Figure A.5: SEM images of the e-beam alignment marks with various sizes in the range of ~0.2
µm to ~ 6 µm created by photolithography and over-exposure... .......................... 162
Figure A.6: SEM image of nanowire/pad structure created using hybrid lithography process (a)
before Si reactive-ion etching and (b) after Si reactive-ion etching and photoresist
ashing. ............................................................................................ .......................... 163
Figure A.7: SEM images of ultra-dense 10 nm 6% XR-1541 Hydrogen Silsesquioxane (HSQ)
lines in 30 nm pitch achieved by a salty developed. .................... .......................... 164
Figure B.1: Raman spectra of the Si-Si LO phonon mode as the laser is scanned from pad to pad
in a direction parallel to the nanowire length for (a) 40 nm, (b) 25 nm and (c) 20
nm-wide nanowires. The nanowires are ~25 nm thick and 2 μm long................... 168
23
Figure B.2: Total in-plane stress extracted from the data assuming biaxial isotropic strain for each
spectrum along the Raman line scan for nanowires with widths of (a) 40, (b) 30, (c)
25, and (d) 20 nm. ......................................................................... .......................... 169
Figure B.3: (a) Low (b) and high laser power spectra of the Si LO phonons from the nanowires
and substrate. Thermal expansion contributes to an apparent ~0.18 GPa total inplane stress shift in the high power case....................................... .......................... 170
Figure B.4: (a) Raman spectra of the Si-Si LO phonon mode and (b) total in-plane stress as the
laser is scanned from pad to pad in a direction parallel to the nanowire length, for
ultra-dense 18 nm-wide nanowires. The nanowire pitch size was reduced to 40 nm
to improve the Raman signal-to-noise ratio. ................................ .......................... 170
Figure C.1: Schematic of starting as-grown epitaxial substrates with (a) single and (b) N = 5
period superlattice of strained-Si/Si0.7Ge0.3; (c) Raman spectra of the Si LO phonon
from the as grown substrate with N = 5 periods using 4 different excitation
wavelengths which vary the penetration depth into the layers. No change in Raman
peak position was observed using different laser lines with different penetration
depths, indicating similar stress in all layers; (d) Raman spectra of starting
substrates with N=1 to 5 periods using 458 nm laser and (e) relative Raman shift
from a Si reference corresponding to strained-Si and relaxed SiGe peaks. For all
samples (up to 5 periods), the starting substrates show fully strained Si. The bulk Si
signal is successfully eliminated for an excitation wavelength of 458 nm via the
intervening thick relaxed SiGe layer. ........................................... .......................... 174
Figure D.1: (a) SEM image of the gate photoresist on the S/D anchors after successive alignment
corrections, demonstrating excellent alignment(< 30 nm accuracy). (b) SEM image
of the photoresist masking layer to etch poly-Si stringers from the S/D anchor
edges. Note this is a test structure with no poly-Si gate (not a real device) to
demonstrate the position of the stringer-etch mask. ..................... .......................... 180
Figure E.1:
(a) Optical photograph of in-situ N+ doped poly-Si wafer pieces deposited at 560°C
and annealed at temperatures between 600°C and 700°C, demonstrating color
change from green to magenta as the temperature is increased; (b) Plot of sheet
resistance as a function annealing temperature, for in-situ N+ doped poly-Si
deposited at 560°C.. ...................................................................... .......................... 187
Figure F.1: (a) Top-view schematic of Si/Ge nanowire PMOS device with N parallel nanowires
and a cutline indicating where the TEM cross-section was obtained; (b) crosssection TEM image of Si-core/Ge-shell NW with Al2O3/WN gate stack. ............. 190
24
Figure F.2: (a) Transfer characteristics of Si-core/Ge-shell nanowire p-MOSFET for various core
Si nanowire widths in the range of 20–50 nm; (b) Output characteristics of Sicore/Ge-shell nanowire p-MOSFET with WSi-NW = 20 nm; (c) Measured inversion
capacitance of each wire normalized per wire length as a function of WSi-NW. ..... 191
Figure F.3: (a) Hole mobility of Si-core/Ge-shell multi-nanowire p-MOSFETs with Al2O3/WN
gate stack, as a function of inversion charge density; (b) Hole mobility and
enhancement factor over the widest wire with WSi-NW = 70 nm, as a function of
core-Si NW width, indicating enhanced hole transport with decreasing wire
width… .......................................................................................... .......................... 192
Figure F.4:
Finite element (a) transverse and (b) longitudinal stress simulations of wide (WSi-NW
= 55 nm) and narrow (WSi-NW = 20 nm) Si-core/Ge-shell nanowires based on 1.4
GPa intrinsic stress of the gate stack. Both nanowires show similar longitudinal
compressive stress. The wide nanowire shows transverse compression while narrow
nanowire shows transverse tension in the top Ge surface. ........... .......................... 194
List of Tables
Table 6.1:
Process splits for post-suspension nanowire treatment, indicating pre-dielectric
cleaning and hydrogen annealing conditions. .............................. .......................... 129
Table A.1:
Optimized process flow for e-beam lithography using HSQ negative-tone
resist........ ....................................................................................... .......................... 158
Table C.1:
Process flow utilized to realize vertically stacked strained-Si nanowires. ............. 176
Table D.1:
Process flow to fabricate gate-all-around nanowire n-MOSFETs.......................... 177
Table E.1:
Process flow to fabricate gate-all-around nanowire p-MOSFETs.......................... 183
25
26
Chapter 1
Introduction
1.1 Thesis Introduction and Motivation
Complementary Metal-Oxide-Semiconductor (CMOS) technology has been scaled during the
past 30 years with a drive to continuously increase the density of devices on a chip and increase
the switching performance of transistors, the major components of electronic circuits. Towards
the end of the ITRS roadmap [1], in which the channel length is predicted to be aggressively
scaled, careful device design consideration is required due to the trade-offs between device
current drive, short channel effects and power consumption. The on-state current (Ion) of a
MOSFET is represented by
/
(1.1)
where W is the device’s width, VDD is the power-supply voltage, Vth is threshold voltage, Qs is
the inversion charge density and v is the velocity near the source region (injection velocity). The
power consumption, Pdiss, can be approximated by [2]
27
10
(1.2)
where PD, PS, α, f, CL, and S are dynamic power dissipation, static power dissipation, activity
factor, operating frequency, load capacitance, and sub-threshold slope, respectively and Ileak
represents the total leakage current from gate and junction sources, and Ith is the drain current at
Vth. In order to maintain low power consumption, lower VDD and leakage current, higher Vth and
steeper S is required according to equation (1.2). On the other hand large gate capacitance, low
Vth and high velocity are required to achieve a high performance in terms of Ion. In addition to
the trade-offs for Vth and VDD, the choice of high CG requires thinner dielectric which can
increase direct tunneling which enhances the leakage and increases the power consumption.
From the electrostatics point of view, high substrate doping is required for aggressively-scaled
planar devices to control the short channel effects. The high doping results in increased junction
and gate-induced-drain leakage (GIDL) [3], degraded on current due to the increased Coulombic
scattering [4] and increased variation in threshold voltage [5]. In addition, extension and halo
implants needed to control short channel effects increase source/drain parasitic series resistance
which degrade the current drive [6]. Considering the trade-off between the current drive, short
channel effects and power consumption [7], conventional Si MOSFETs fail to satisfy the device
requirements and new materials and device architectures are required for future CMOS
generations.
To enhance the current drive, new channel materials such as strained-Si, SiC, SiGe, Ge, III-V
have been extensively investigated over the past 20 years, by many academic and industrial
researchers with some representative papers given in references [8-13]. Uniaxially strained-Si
technology with tensile liner and embedded SiGe stressors was incorporated into main-stream
28
CMOS production starting at the 90 nm technology node [14]. To further continue scaling and
improve the current drive high-permittivity-dielectric (high-κ)/metal gate technology has also
been commercialized by Intel in the 45 nm technology node.
This has been shown to
dramatically improve the gate leakage and power consumption for both NMOS and PMOS
devices [15]. Ultra-thin-body and multi-gate SOI devices have been shown to provide excellent
scalability and immunity to short-channel effects [16, 17]. The geometry enables excellent
electrostatic control by the gate and the lightly-doped Si channel dramatically reduces the
random dopant fluctuation and Vth variation [16]. In addition, these device architectures benefit
from lower capacitive parasitics and junction leakage due to the presence of a thick buried oxide.
Among various options for a multi-gate device architecture, such as double-gate, tri-gate,
etc., the nanowire (NW) channel with a wrap-around gate, so called Gate-All-Around (GAA),
has the largest advantage in terms of electrostatic integrity as will be discussed in Chapter 2.
Two approaches are generally used to fabricate Si NWs as well as other semiconductor NWs:
bottom-up and top-down. In the first method, NWs are usually grown using a metallic catalyst on
a separate substrate, usually through a Vapor-Liquid-Solid (VLS) growth mechanism. After a
chemical or mechanical separation step, the NWs are harvested and transferred to another
substrate [18-20]. In the top down-approach, the NWs are fabricated using a CMOS compatible
technology, such as lithography-based patterning and etching [21]. Unlike the bottom-up
approach where the NWs are randomly distributed, the top-down method enables accurate
positioning of the NWs across the wafer and facilitates the ultra-large-scale-integration for highperformance nano-electronic circuits. Moreover, due to process difficulties related to the length
of grown NWs, NW release and gate-etch process, most of the VLS grown NW transistors have
an omega-shaped gate (Ω-gate) geometry and are thus not full gate-all-around [18].
29
In a long channel MOSFET, carriers encounter various scattering mechanisms on their path
toward the drain terminal. Carrier mobility is a well known benchmark to judge the intrinsic
performance of a long channel MOSFET. Equation (1.1) indicates that the injection velocity near
the source determines the on-state current of a short channel device. As will be discussed in
Chapter 2, state-of-the art short channel devices do not operate in the fully ballistic regime (they
are at roughly 60% of the ballistic limit) and mobility is related to velocity through effective
mass and ballistic ratio. Therefore, understanding the carrier mobility is beneficial to design and
engineer new devices for future CMOS generations. To date, very few groups have examined the
intrinsic transport in Si NWs [22-25]. The presence of significant resistive and capacitive
parasitics as well as lack of large capacitance due to the small size of the NW channel adds
complexities to the extraction of the intrinsic NW characteristics. In most of the published
reports, either over-simplified calculations or in-complete device charge simulations lead to
inaccurate and unreasonable mobility extraction [25]. While in the other reports with more
careful extraction techniques and design, the lack of a well-behaved top-down process (as
compared to the bottom-up-fabricated NWs with smooth, near ideal sidewalls) results in
significant mobility degradation for smaller NW sizes [23], which is not intrinsic to NWs in
general.
This thesis is about transport enhancement techniques in GAA MOSFETs. As part of this
thesis, the fabrication of Si NWs with uniaxial tensile strain is demonstrated using a novel topdown scheme. The Si NW channel combines the suspended structure required for GAA
architecture as well as built-in uniaxial tension with potential for electron transport enhancement.
The performance of novel GAA Si NW n-MOSFETs with uniaxial strain is analyzed in this
thesis. GAA Si NW p-MOSFETs were also fabricated and analyzed. In order to accurately
30
extract the hole mobility of Si NWs, a process was designed and developed using an optimized
hydrogen anneal process to form smooth, high-quality NW sidewalls. The process also benefits
from utilization of a high-κ /metal gate technology required for future CMOS generations and to
avoid the complexity which occurs when extracting mobility of NWs due to non-uniform nature
of common dielectrics such as crystal orientation-dependent thermally grown or low-temperature
oxide. Mobility enhancement over planar SOI MOSFETs is observed for both engineered nchannel and p-channel NW GAA MOSFETs. The observations provide insights into the physics
of NW MOSFETs which are of interest for future low-power, high-performance CMOS
technologies.
1.2 Thesis Outline
Chapter 2 briefly overviews the background physics and methods incorporated in the next
chapters to facilitate the understanding of the rest of this thesis. The universal scaling and
transport theory of MOSFETs is provided and various scattering mechanism are briefly
discussed. Prospects and possible candidates to enhance the transport of multi-gate devices are
also presented. In addition, mobility extraction methodology used in this thesis is discussed at the
end of this chapter.
Chapter 3 presents the fabrication and stress characterization of novel asymmetrically
strained-Ge and silicon nano-bars/wires with potential transport enhancements for future multi-
31
gate CMOS. Device design, fabrication and characterization of GAA Si NW n-MOSFETs with
and without strain are presented in chapter 4. Detailed intrinsic transconductance and electron
mobility extraction for strained-Si NW n-MOSFETs with various dimensions are provided in this
chapter.
Device design considerations to accurately investigate the hole mobility in Si NW MOSFETs
with a high-κ/metal gate process are presented in chapter 5. An optimized high-κ/ metal gate and
high-temperature hydrogen anneal process is described and the role of hydrogen anneal is
investigated. Chapter 6 investigates the electrical performance of Si NWs with the above process
and detailed hole mobility extraction down to 8 nm NW dimensions is discussed.
Chapter 7 summarizes and concludes the thesis and suggestions for future work to further
enhance the transport in multi-gate NWs are given. In addition, the process and characterization
details are presented in Appendices A-E. Finally, fabrication and hole transport in Si/Ge coreshell NWs is presented in Appendix F.
32
Chapter 2
Thesis Background
This chapter briefly overviews the background physics and methods required to facilitate the
understanding of the rest of this thesis. After an introduction to multi-gate MOSFETs, the
scaling theory of the MOSFET is briefly discussed in section 2.2 of this chapter. Section 2.3
overviews the transport theory and major scattering mechanisms in Si MOSFETs. Possible
transport enhancement solutions for planar and multi-gate MOSFETs are provided in section 2.4,
including discussion of surface orientation and channel direction, strain engineering and new
processes and channel materials. Finally, section 2.5 presents the extraction methodologies to
characterize the carrier mobility in gate-all-around nanowire transistors.
2.1 Introduction to Multi-gate Devices
Conventional bulk Si technology has been the mainstream technology since the beginning of
the CMOS industry. As the channel scales from one generation to the next, increased channel
doping and halo implant are required to control short channel effects. In addition, junction
leakage is a determining factor for the overall off-state leakage. Moreover, the source/drain to
33
bulk capacitive parasitics are more pronounced in aggressively scaled MOSFETs. These parasitic
capacitances are significantly reduced by partially-depleted (PD) Silicon-On-Insulator (SOI)
technology which has been in production by a few groups for low-power applications [26]. On
the other hand, utilizing fully-depleted (FD) SOI technology where the entire channel is depleted
due to the thin Si body, the gate control is significantly enhanced compared to the bulk Si. In
addition to the reduced parasitics and junction leakage, the lightly-doped or undoped Si
minimizes random dopant fluctuations and thus decreases the threshold voltage variation, which
is a concern for nanoscale state-of-the art transistors. Moreover, from the process point of view,
the issues related to halo and implant damage and device isolation are essentially eliminated for
ultra-thin body FD SOI technology compared to the bulk Si process [16].
In order to control short channel effects in planar SOI MOSFETs and maintain reasonable
electrostatics at a given gate length, LG, a critical Si thickness, tSi on the order of LG/3 is required
[27, 28]. As an example, for the 15 nm node technology, a gate length of 15 nm is indicated by
the International Technology Roadmap for Semiconductors (ITRS), which demands a FD-SOI
technology with a Si body thickness of around 5 nm. In addition to manufacturing issues
regarding the control of Si critical thickness dimension, the confinement of carriers results in
degradation of carrier transport (as discussed in section 2.3) and large external resistance.
Therefore, multi-gate devices have been suggested to further relax the critical Si dimension as
well as benefit from the aforementioned FD-SOI device and process technology. For this
purpose, planar double-gate [29], fully DEpleted Lean-channel TrAnsistor (DELTA) [30],
vertical double-gate (FinFET) [31-34], triple-gate (Tri-gate) [35], omega-shaped gate (Ω-gate)
[36], penta-gate [37], Inverted T-channel FET [38], Φ-FET [24], and Gate-All-Around (GAA)
nanowire [21-24], [39-42] have been suggested by various researchers over the past decade.
34
While most of these multi-gate technologies have been experimentally shown to benefit from
excellent electrostatics and short-channel effects, they commonly suffer from a complicated
fabrication process technology compared to planar bulk or SOI technology. Figure 2.1 shows the
device schematic of (a) ultra-thin body planar FD SOI, (b) double-gate FinFET (c) tri-gate and
(d) GAA NW MOSFETs. The critical Si dimensions to sustain acceptable electrostatics [36] are
also presented. It can be seen that the criterion of Si film thickness is successfully relaxed for the
nanowire MOSFET, which is naturally evolved from double-gate FinFET technology.
Figure 2.1: Schematic diagram of the device cross-section, viewed in the direction of the current
transport for (a) planar ultra-thin-body SOI, (b) double-gate FinFET, (c) Tri-gate FET and (d) gate-allaround nanowire FET, representing the evolution of nanowire FET from an ultra-thin-body SOI FET. The
required criterion on the Si thickness (tSi) for a given gate length (LG) to have acceptable electrostatics is
also shown, indicating more relaxed channel dimension available for nanowire FET (compared to other
architectures) to be considered as a candidate for a given technology node.
35
2.2 Scaling Theory of MOSFETs and Advantages of
Nanowires
The scaling behavior and electrostatics of thin-body SOI (single or multi-gate) and gate-allaround nanowire MOSFETs is determined by the surface potential in the channel which results
in the injection of carriers from the source to the drain terminal. The electrostatic potential, Φ, in
the channel can be solved using Poisson’s equation, with a parabolic solution in the form of
equation (2.1) as suggested by Young [27]:
Φ ,
(2.1)
where z and r are directions along and perpendicular to the current direction, respectively. The
1D Poisson’s equation for the surface potential (Φs), for various channel geometries, can be
simplified to:
Φ
Φ
Φ
Φ
(2.2)
where Φg , Φbi, ρ, N and εs are gate and built in potentials, mobile and channel doping densities
and channel permittivity, respectively. The solution to the second-order differential equation
(2.2) has an exponential form given by
Φ
exp (2.3)
where λ is the so called natural length or screening length, representing the length scaled for
channel potential variation. The natural length contains information about the device geometry.
The analytical solutions for double gate and gate-all-around structures are given by equations
(2.4) and (2.5), respectively [43, 44]:
36
εS
2ε
ε tS
4εS t
1
2εS t S ln 1
2
tS t
(2.4)
ε tS
(2.5)
16
where tSi, εSi, tox and εox are the physical thickness and permittivity of Si and dielectric,
respectively. With the scaling parameter, α, defined as
(2.6)
2
there is a universality for scaling of various devices with different architecture or geometries.
Figure 2.2 shows a simulation-based example of the universality of sub-threshold slope and
Drain-Induced-Barrier-Lowering (DIBL) for GAA and double-gate MOSFETs for various oxide
and Si thicknesses [44]. Recent results by Bangsaruntip et al. for short channel GAA Si NWs and
planar FD-SOI MOSFETs also provide experimental evidence for this universality [42].
Figure 2.2: Universal dependence of (a) subthreshold slope and (b) drain-induced-barrier-lowering
(DIBL) on the scaling parameter, for gate-all-around and double-gate MOSFETs with various oxide and
Si thicknesses. Data from Ref. [44].
37
In the off-state operation mode, the solution for maximum potential which determines the
sub-threshold drain current is given by [45]
Φ
2
Φ
Φ
Φ
Φ
Φ
exp
2
Φ
Φ
(2.7)
where Φd = -qVds is the drain potential. For an ideal MOSFET with L >> λ, δ Φs ≈ δ Φg and
∂Φs/∂Φd ≈ 0. In other words, the gate has direct control over the channel surface potential and
short channel effects are diminished when the natural length of a device is much smaller than the
gate length. This leads to an ideal inverse sub-threshold slope, SS, defined as
log
ln 10
,
1
(2.8)
where kB is the Boltzmann constant, T is the operation temperature, CB and CS,D are bulk and
S/D capacitances and Cit is the interface trap capacitance. For an electrostatically well-behaved
device (Cox >> CB and CS,D) with an ideal dielectric interface (Cit = 0), the right term is negligible
and the sub-threshold slope approaches ~60 mV/dec. at room temperature. For GAA nanowires
with a thickness similar to single-gate or double-gate SOI MOSFETs, the natural length is larger
which results in lower sub-threshold slope and DIBL at a given gate length. This clearly
indicates why nanowires are attractive for future CMOS generations. Figure 2.3 (a) illustrates a
capacitance circuit model of a MOSFET, where Cs and Cd are the source and drain capacitances
and Cox = εox / tox is the physical oxide capacitance [46, 47]. The inversion-layer capacitance or
quantum capacitance is defined as
(2.9)
Φ
38
which is the variation of channel charge, Qch, due to a change in the surface potential. The origin
of the quantum capacitance is the finite band bending required to increase Qch due to the finite
density of states. Figure 2.3 (b) shows a schematic of the gate capacitance components including
quantum capacitance [46-48]. Using the circuit model shown in Figure 2.3 (a) and equation (2.8)
the variation of surface-channel potential is given by
Φ
Φ
Φ
(2.10)
Figure 2.3: (a) Capacitance circuit model and conduction band profile of a MOSFET, introducing the
capacitances of source (Cs), drain (Cd) and oxide (Cox) as well as surface channel charge (Qch) [46, 47];
(b) Simplified capacitance model of the gate of a MOSFET (CG), displaying the physical oxide thickness
(Cox) and the quantum capacitance (CQ).
As described earlier, for an electrostatically well-behaved device in the sub-threshold regime,
δ Φs ≈ δ Φg and ∂Φs/∂Φd ≈ 0. As a result, Cox >> Cd, CQ. However, in the on-state the quantum
capacitance is proportional to the density of states,
Φ , where Ef source is
the source Fermi level [49, 50]. For a 3-D system like a bulk Si MOSFET, with a density of
states proportional to
Φ , the quantum capacitance is continuously increased by increasing
gate voltage and according to (2.10), ∂Φs/∂Φg approaches zero. For a nanowire MOSFET with
39
very small channel dimensions, quantization results in sub-band separation. When the sub-band
separation exceeds the thermal energy, one-dimensional (1-D) transport results with a density of
states proportional to 1/
Φ . As a result, quantum capacitance becomes smaller than the
physical oxide capacitance and the device operates in the quantum capacitance limit, i.e. the gate
capacitance is governed by the quantum capacitance rather than oxide thickness [47]. In addition,
according to equation (2.10), ∂Φs/∂Φg no longer approaches zero and approaches unity in the
limit of extremely scaled dielectric thickness. It is worth mentioning that for realistic oxide
thicknesses, the quantum capacitance limit happens in materials with very low density-of-states
effective mass such as InAs [51].
2.3 Carrier Transport and Scattering Mechanisms
2.3.1 Mobility and Velocity
The drain current of a MOSFET is determined by the charge density (Qs) and velocity (vs) of
carriers near the source and can be simply represented by [52]
/
(2.11)
where Qs is the channel charge density given by Qs = Cg (Vgs - Vth). In a long channel
MOSFET, the source velocity vs is proportional to the electric field and low field effective
mobility, µeff, near the source edge. The low field effective mobility of a MOSFET is affected by
various scattering mechanism that carriers encounter when moving in the channel towards the
drain end and is inversely proportional to the effective mass of carriers and is given by
40
(2.12)
where τ is the scattering relaxation time and m* is the carrier’s effective mass [53]. Various
sources of scattering will be discussed later in this section, where in most of them the scattering
relaxation time in the two-dimensional inversion layer is inversely proportional to the density of
state effective mass, mD [54]:
(2.13)
In this equation, mc is the carrier conductivity effective mass. On the other hand, according to
Lundstrom’s theory, carriers obey quasi-ballistic transport in short channel devices in which nonstationary transport becomes dominant [52]. Here, the injection velocity of carriers over the
potential barrier near the source, vinj, determines the drain current. The drain current in this case
is given by:
1
1
(2.14)
where Qssource is the inversion charge density near the source, r is the backscattering rate towards
the source. The backscattering rate is determined by the mean free path of the carriers, λ, and the
distance, l, over which the channel potential drops by the thermal voltage:
(2.15)
The l factor is also called the critical length for scattering and is empirically estimated as a
fraction of the effective channel length. The second term of (2.14), B = (1-r)/(1+r) is often called
ballistic efficiency, which indicates how close the transport is to the ballistic thermal limit [55,
56]. The injection velocity for non-degenerate and degenerate limits is given by [56, 57]:
41
12
, for the non-degenerate limit
/
4
3
/
/
/
/
/
, for the degenerate limit
(2.16)
(2.17)
where vth and vF are thermal and Fermi velocities and mx and my are in-plane effective masses
along and perpendicular to the transport direction, respectively. In order to increase the source
injection velocity, lighter in-plane masses are required. Comparing equation 2.13 for mobility
and 2.17 for injection velocity and considering the fact that mobility change is only a
consequence of the effective mass, vinj
µeff½. In general, considering various scattering mechanisms leads to [58]: , where 0 ≤ α ≤ 0.5
(2.18)
Khakifirooz showed that the critical length of scattering is proportional to the low field
mobility by a power law [58]:
, where β ≈ 0.45
(2.19)
Using equations (2.15), (2.18) and (2.19), the relation between the change in mobility and
injection velocity is given by:
1
1
(2.20)
As a result of the correlation between vinj and µeff, and the fact that state-of-the-art devices
are not working in fully-ballistic regime, understanding of mobility for new channel materials
and systems such as strained-Si and nanowires is important and can provide new insights for
42
design of short channel devices. In the following sections, various mechanisms that affect the
scattering in modern CMOS devices are overviewed.
2.3.2 Scattering Mechanisms
In a real device where transport is not fully ballistic, carriers can be scattered via interaction
with ionized impurities, other carriers, lattice vibrations, imperfect dielectric interface or
remotely from the dipoles in the high-κ dielectric. These collisions leads to a change of the
carrier’s crystal momentum, p = ħk, to another state with a crystal momentum of p'. Knowing
the scattering potential, the scattering rates can be approximated using Fermi’s Golden Rule
using
1
Ω
exp
. /
(2.21)
where ħ, Ω, Hp'p and Us and are reduced Planck constant, scattering volume, matrix element and
perturbing potential, respectively. The transition rate from state p to p', S(p, p'), can be then
calculated by
S
,
2π
′
(2.22)
where ΔE is any possible change in the carrier’s energy caused by the scattering event [53].
Depending on the nature of scattering, the relaxation time can then be calculated using:
1
,
, for isotropic scattering
43
(2.23)
1
,
1
cos α
, for elastic scattering
(2.24)
where α is the polar angle between the incident and scattered carrier. The total relaxation time, τ,
can be approximated using Mattheissen’s rule assuming individual scattering rates, τi, are
independent [53]:
1
1
(2.25)
2.3.2.1 Coulombic Scattering
Carriers in the inversion layer can be affected by the electric field of ionized impurities
present in the channel through Coulombic scattering. Screening results in a decaying exponential
perturbation potential
exp(-r/LD)/r [53]. The screening length, LD, is also known as the Debye
length which is inversely proportional to the square root of channel doping. In general, this type
of scattering tends to deflect carriers at very small angles. When the carrier density is very high,
LD is very small and the potential is strongly screened and the scattering is isotropic. Using the
screened potential, Brooks and Herring showed that the momentum relaxation time is
proportional to E3/2, where E is the carrier’s kinetic energy [59]. In other word, carriers with
higher kinetic energy (at higher gate overdrive or higher operation temperature) are less
influenced by the ionized impurities. Theoretical and experimental results suggest that the
Coulombic scattering limited mobility is proportional to the inversion carrier density and
inversely related to the background doping concentration [4, 60]. Carriers can also be scattered
by interface traps at the dielectric/semiconductor interface. In FD-SOI, multi-gate and nanowire
44
MOSFETs, as the channel is lightly-doped or undoped, the coulombic scattering due to the
ionized impurities is significantly suppressed. However, the mobility can be degraded by the
scattering of the carriers from the interface states at the Silicon/dielectric or Si/buried oxide
interface.
2.3.2.2 Surface Roughness Scattering
In MOSFETs with thermally grown oxide were oxidation leaves a relatively rough surface on
an atomic scale, carriers can be scattered by the fluctuations of the confining potential along the
channel direction. This leads to sub-band fluctuation and is often called surface roughness
scattering. For multi-gate and nanowire devices where the channel is defined by non-ideal
lithography and reactive ion-etching, this type of scattering becomes very important and can
severely degrade the carrier transport. While this effect is negligible at lower overdrives, its
effects are more pronounced at higher overdrive voltages where the confined carriers are very
close to the dielectric-channel interface. The related perturbing potential, USR, is usually modeled
by a random fluctuation function, Δ(r), and the average vertical electric field, Eav:
∆
(2.26)
Δ(r) is the autocorrelation function of interface roughness and is usually approximated by
a Gaussian function in the form of:
∆
(2.27)
∆ exp 45
where Δ and L are the height and correlation length of surface roughness, respectively [61].
Under the assumption of single sub-band occupation, the relaxation time of surface roughness
scattering, τSR (p), is given by:
1
Δ
1
exp
2
1
(2.28)
In the extreme limit where the electron wavefunction is much larger than the correlation length,
µSR
(∆.L.Eav)-2. It has been experimentally observed that for electrons on (100) Si, the mobility
has stronger Eeff dependency, i.e. Eeff-2.6 [62]. Here, the average electric field is interpreted
similar to the effective vertical field, Eeff, which is proportional to the inversion charge density.
Moreover, the experimental results provided in Ref. [62] indicate that surface roughness limited
mobility for (110) and (111) electrons and (100) holes have Eeff-1.5, Eeff-1.0 and Eeff-1.3 dependence,
respectively. This non-parabolic relationship can be attributed to the large correlation length
comparable to the carrier’s workfunction which leads to the Eav dependence of the integral of
equation (2.28). However, the above hypothesis was shown to fail by low temperature
measurements. In summary, the inversion charge density or Eeff dependence of surface roughness
limited mobility for carriers on non-(100) planes is complicated and can not simply be modeled
by the height and correlation length of the Gaussian’s fluctuation function.
2.3.2.3 Phonon Scattering and Confinement
A major source of scattering in semiconductors originates from interaction of the electron
wavefunction with crystal lattice vibrations which are quantum mechanically described by
46
phonons. Due to periodic nature of lattice, vibrational lattice waves have similar properties to
electronic Bloch function. Acoustic phonons have relatively low energies and approximately
linear relationship to the lattice wave vector, β, while the optical phonon have energies in the
order of a few tens of electron volts and are almost independent of β. For acoustic phonons
which displace neighbor atoms in the same direction, the interaction potential, UAP, is
proportional the strain, or ∂u/∂x (u is the displacement). On the other hand, for optical phonons
which displace neighbor atoms in the opposite direction, the interaction potential, UOP, is
proportional to the displacement [53]. When a carrier interacts with a phonon, both its energy
and momentum are conserved. For intra-valley scattering where the carriers remain in the same
valley after scattering, the phonons involved are only those with wave vectors near the center of
the Brillouin zone. Since the change in the carrier energy is often negligible compared to the
carrier’s energy, kBT, acoustic phonon scattering is considered to be an elastic process. However,
optical phonon scattering involves a phonon with energy comparable or larger than the carrier’s
energy and can not be considered an elastic process, unless the carriers have very high energies.
Using phonon deformation potentials and considering the conservation of energy and
momentum, Fermi’s Golden Rule can be invoked to calculate the phonon scattering rate:
S
,
C
1
2
1
2
(2.29)
2
where Nβ is the number phonons, ω is the phonon angular frequency and v is the carrier velocity.
The prefactor Cβ is given by:
Ω
for acoustic phonons and
Ω
47
for optical phonons
(2.30)
where DA and DO are acoustic and optical phonon deformation potentials, vs is the sound
velocity, and ωO is the optical phonon frequency. The acoustic and optical phonon relaxation
times are then given by equations (2.31) and (2.32), respectively.
1
(2.31)
1
1
2
2
1
2
(2.32)
where cl is the elastic constant and gc is the density of states. It can be seen that for both cases,
scattering rates are proportional to the density of states. For electrons in the conduction band of
semiconductors such as Si or Ge where the conduction band consists of multiple energetically
equivalent valleys, both types of scattering, acoustic and optical, are important. Similar equations
and arguments can be used for such inter-valley phonon scatterings. For Si, carriers with higher
energies have shorter relaxation time.
Carriers can be quantum mechanically confined in infinite quantum wells or quasi-triangular
wells associated with the MOSFET inversion layer. For MOS inversion layer, the shape of the
quantum well can be numerically calculated using self-consistent Schrödinger-Poisson’s
equation. For such two-dimensional carriers, momentum conservation only applies in the plane
and the phonon scattering rate is given by
S
,
|If β |
(2.33)
,
where Ifi is called form factor, and z and denote the confinement and in-plane directions,
respectively [53]. The inter-sub-band acoustic phonon scattering rate is given by
48
1
1
1
(2.34)
|
|
(2.35)
where F(z) is the envelope function of the confined factor and Wfi describes the effective extent
of the interaction in the confinement direction. In addition, the scattering rate is proportional to
the two-dimensional density of states. Similar relation can be derived for inter-valley scattering
rates. The resulting acoustic phonon-limited mobility is:
(2.36)
with W, width of inversion layer defined as [60, 61]:
16
3 12
/
11
32
/
/
(2.37)
Here, mz is the effective mass along the confinement direction, Ndpl is the background doping
and Ns is the inversion charge density. As a result, phonon limited mobility is proportional to Ns1/3
. Figure 2.4 illustrates the schematic of sub-band structure of 2D electrons for (a) a bulk
MOSFET and (b) thin-body SOI [63]. Unlike bulk MOSFET, the tail of electron or hole
wavefunction is confined by the physical thickness of the Si layer which leads to phonon limited
mobility reduction as the thickness of SOI is decreased. As a result, monotonic hole mobility
reduction is observed with decreasing Si thickness [64, 65]. However, a different trend is
observed for electron mobility of ultra-thin-body SOI with body thickness in the range of ~ 3 to
5 nm. For SOI thickness around 5 nm, further decrease of Si thickness down to ~3 nm is shown
49
to enhance the electron mobility, due to increased separation of the subbands and reduced intersubband phonon scattering [64].
Figure 2.4: Schematic sub-band structures of two-dimensional electrons for bulk and ultra-thin-body SOI
MOSFETs. Structural confinement of the inversion layer in ultra-thin-body SOI MOSFETs decreases the
average thickness of the inversion layer (Zav) as well as phonon-limited mobility and increases the
inversion layer capacitance and threshold voltage (After Uchida et al. [63]).
2.3.2.4 Thickness Fluctuation Scattering
In ultra-thin body SOI MOSFETs, III-V quantum wells or nanowires, the energy level of
confined subbands is a strong function of the channel thickness. As a result, any atomic scale
change in the thickness of channel can significantly affect the subband levels and lead to
scattering of the carriers. This type of scattering is called thickness fluctuation scattering [64]
and is schematically shown in Figure 2.5. The related scattering potential, UTF, is given by:
(2.38)
∆
where t is the channel thickness, E is the subband energy level, and ∆ is the fluctuation function,
as described in section 2.3.2.2. For a one-dimensional quantum well, similar to a particle in box
50
problem, the energy levels are proportional to t-2. This results in a thickness fluctuation limited
mobility, μTF, of the form:
(2.39)
which has been experimentally observed for ultra-thin-body SOI, SiGe or III-V MOSFETs [64],
[66-69]. In the case of top-down fabricated Si nanowires with relatively rougher surface
compared to planar SOI, this scattering may be a determining factor of the overall mobility
behavior.
Figure 2.5: Schematic of (left) interface-roughness induced thickness fluctuation scattering and (right)
variation of conduction band due to thickness fluctuation scattering in ultra-thin-body SOI channels
(After Ref. [64]).
2.3.2.5 Remote Phonon Scattering
As transistors are scaled, thermally grown SiO2 can no longer meet the off-state and leakage
requirements. High-κ dielectrics have been studied as a replacement for SiO2 and have been in
production since the 45 nm technology node [15]. In general, the dielectric constant of a material
originates from the contribution of the ionic and electronic polarization. The electronic
polarization is inversely proportional to the direct bandgap of the material. The electronic effect
51
is negligible for dielectrics, where their bandgaps are naturally much larger than semiconductors.
Therefore the ionic polarization dominates the high-κ behavior of dielectrics. The large dielectric
behavior of high-κ materials is due to the highly polarizable metal-oxide bonds. Unlike “hard”
Si-O bonds in SiO2, polarization of these “soft” metal-O (or N) bonds can screen the external
field and increase the dielectric permittivity [70]. Wang and Mahan showed that electrons at the
interface between semiconductor and dielectric can couple with the surface optical (SO) modes,
arising from the longitudinal-optical (LO) modes on the insulator at the Si/insulator interface
[71]. The coupling potential is given by:
1
1
(2.40)
where εs∞ is the optical permittivity of the semiconductor, εox0 and εox∞ are static and optical
permittivities of insulator, respectively. Equation (2.40) is similar to the Polarized Optical
Phonon (POP) scattering where the deformation of the lattice by phonons perturbs the dipole
moment between atoms which results in an electric field that scatters carriers [53]. However, in
this type of scattering, inversion layer electrons are scattered by “image-charge effects” at the
semiconductor/dielectric interface which affects the decay of the dipole field of the insulator
phonons away from the bulk of the insulator. This scattering is called remote phonon scattering
factor is relatively
and has a large impact on the carrier’s mobility. For SiO2, the
small. In addition, for SiO2 ωSO ≈150 mV, and it is very unlikely for thermal electrons to emit
such a large energy. For the high-κ dielectrics, ions can only respond at lower frequencies and
therefore the high-frequency response is purely electronic. This large ionic response at lowfrequencies results in a large static dielectric constant (large
becomes large which degrades the carrier’s mobility.
52
), but the
factor
Figure 2.6: (a) Calculated effective electron mobility of Si inversion layers of MOS system with
insulators indicated. Remote scattering with surface optical phonons, anisotropic scattering with acoustic
phonons and empirical scattering with surface roughness have been considered (b) Calculated total
electron mobility in the inversion layer of a HfO2 /SiO2 /Si system as a function of thickness of the
interfacial SiO2 layer for the three indicated values of the electron concentration in the inversion layer.
The horizontal lines at the far right are the asymptotic limits of infinite oxide thickness (Results from
Fischetti et al. [70]).
Figure 2.6 (a) shows the theoretical electron effective mobility from Fischetti et al. for
various dielectrics with ideal interface (i.e. no defect, fixed charge or interface trap) [70].
Mobility degradation due to the remote phonon scattering can be seen for various dielectrics.
Moving the High-κ dielectric farther away from the Si substrate using and interfacial SiO2 is
expected to significantly improve the electron mobility. The thin SiO2 interfacial layer reduces
the scattering strength of the High-κ SO modes by a factor ~exp ( -2KF tox), where KF is the
Fermi wavevector which is proportional to Ns1/2 for 2D electron gas. As a result, as shown in
Figure 2.6 (b), for small Ns, unreasonably thick oxides are required to boost electron mobility.
However, at large Ns, even a thin 0.5-1.0 nm of interfacial oxide is sufficient to reduce remote
phonon scattering. As another solution, Chau et al. experimentally demonstrated that the use of
midgap metal-gate electrodes (such as TiN) with higher electron density than depleted poly-Si
53
can effectively screen and reduce the remote phonons and significantly improve the electron
mobility [72].
2.4 Transport Enhancement Options for Multi-Gate
MOSFETs
This section overviews the impact of various design and process options such as surface and
channel direction, strain engineering and utilizing new channel materials and process
technologies on the transport in planar and multi-gate and provides guidelines to boost their
carrier transport.
2.4.1 Surface Crystallographic Orientation and Channel Direction
In multi-gate and nanowire transistors, inversion carriers are in close proximity to various
surface crystallographic orientations due to the three-dimensional geometry of the channel. As a
result, carrier transport in different surface orientations and directions can be significantly
different due to distinct scattering mechanisms and conductivity effective masses for various
planes. Figure 2.7 shows the experimental results for electron and hole effective mobilities as a
function of inversion charge density for (100), (111) and (110) surfaces and for <110> and
<100> channel directions [73]. While the (100) surface has the highest electron mobility, it
54
shows the lowest hole mobility. The opposite trend is observed for (110) surfaces which have
recently been considered as a transport booster for p-MOSFETs [74-77].
Figure 2.7: Effective electron and hole mobility of Si as a function of inversion charge density for (100),
(111) and (110) surfaces. Mobility is isotropic (direction independent) for (100) and (111) surfaces.
Among all surface/directions, (100) and (110)/<110> have the highest electron and hole mobility,
respectively (Results from Irie et al. [73]).
To further elucidate this, the equi-energy conduction band valleys for (100) and (110) are
plotted in Figure 2.8. For (100) surfaces, transport is isotropic (independent of the channel
direction) and the conductivity effective mass is determined from 4 valleys with effective mass
of mt = 0.19 m0 and two valleys with effective mass of ml = 0.98 m0, where mt, ml, and m0 are
the transverse, longitudinal and free electron masses. For (110) surface with the current along
<110> direction, 4 valleys with ml and 2 valleys with mt contribute to the total conductivity
effective mass, which qualitatively describes why electron (110) mobility is less than on the
(100) surface.
55
Figure 2.8: (a) Schematic of Si conduction band’s equienergy ellipsoids, displaying Δ2 and Δ4 valleys; (b)
Equienergy valleys of Si on (110) surface. Four valleys with heavy ml and two valleys with light mt
contribute to the conduction along <110> direction; (c) Equienergy valleys of Si on (100) surface. Two
valleys with heavy ml and four valleys with light mt contribute to the conduction along <100> or <110>
direction, offering lower conductivity mass compared to (110) surface.
Figure 2.9: (Top) energy and (bottom) equienergy lines of the lowest-lying subbands (HH, LH and SO)
along with the position of the Fermi level for (001), (011) and (111) relaxed Si surfaces. Spin degeneracy
is lifted away from the center of the zone, so that the density of states given subband depends on spin
variables (Results from Fischetti et al. [65]).
56
The understating of hole transport is generally more complicated due to the strong anisotropy
and non-parabolicity of the heavy-hole (HH) and light-hole (LH) bands and small value of the
spin-orbit (SO) splitting in the valence band. Figure 2.9 shows the k.p calculated hole subband
energy as a function of surface field, Fs, and the equi-energy lines in the lowest-lying HH, LH
and SO subbands for (100), (111) and (110) surfaces [65]. For the (110) surface, the largest
energy splitting between the lowest two subbands among various surface orientations and the
light effective mass along <110> direction under strong quantum confinement effects are
suggested mechanisms for enhanced hole mobility. In addition, for (110) surfaces, the observed
enhanced hole mobility of the <110> over <100> can be justified by the lighter effective mass
along <110> direction.
Based on the above discussion and the fact that gate-all-around nanowire channels may
involve transport along various surface orientations, it is expected that GAA nanowire pMOSFETs will show transport enhancement over planar (100) MOSFETs. Chapter 6 provides
some experimental evidence for this mobility enhancement. However, as can be experimentally
seen in chapter 4, GAA nanowire n-MOSFETs suffer from lower mobility than (100) planar
devices. Strain engineering is indeed needed to recover the electron mobility degradation by the
non-(100) planes.
2.4.2 Strain Engineering
It is well known that biaxial tension can improve the electron mobility of planar (100)
MOSFETs [8, 78, 79]. Figure 2.10 shows the schematic of the conduction band for electrons on
57
the (100) and (110) surfaces. For (100) surface, biaxial and <110> oriented uniaxial strains shift
the Δ2 valleys to lower energies and Δ4 valleys to higher energy, and repopulate electrons in the
Δ2 valleys, with lower effective mass. As a consequence, inter-valley phonon scattering is
significantly reduced and the mobility is enhanced by ~2X [54]. For (110) surface, as shown in
Figure 2.10, biaxial tension repopulates the electron in the Δ4 valleys whose energy is lowered by
strain. The effective mass of these four valleys along <110> is ml which doesn’t provide the
desired enhancement. However, the optimum mobility enhancement for biaxially strained (110)
surface is along <100> direction where lighter mt dominates the conductivity effective mass.
Utilizing uniaxial tension along <110> direction, electrons repopulate to the two valleys with
lower energy reduced by strain and lower effective mass (mt) [80, 81].
Figure 2.10: Schematic of electron repopulation in the conduction band equienergy valleys of (a) (100) Si
under <110> uniaxial or biaxial tension, (b) (110) Si under biaxial tension and (c) (110) Si under <110>
uniaxial tension. The current direction for all cases is along <110>, which is favorable for all cases except
case (b) where its mobility-enhanced direction is shown.
In addition to electron repopulation, unlike biaxial strain, uniaxial strain benefits from
continuous reduction of effective mass by applying strain. This is shown in Figure 2.11 (a) where
the calculated relative change in the effective mass in the direction parallel and perpendicular to
58
the channel is plotted as a function of uniaxial strain in the [110] direction (open symbols: tightbinding, solid lines and filled symbols: pseudopotential method) [58, 82, 83]. As a consequence
of continuous reduction in the effective mass, for sufficiently high level of strain, uniaxial strain
is expected to display a larger mobility enhancement factor than biaxial strain [84].
Figure 2.11 (b) shows the plot of relative change in ballistic velocity as a function of relative
change in mobility for biaxial and <100> and <110> uniaxial strained Si [58, 82]. For uniaxial
tension along <110> direction, a direct correlation between relative change in ballistic velocity
and mobility is observed. For biaxial strained-Si, since the mobility enhancement is governed by
reduction in phonon scattering rather than effective mass (recall equations (2.16) and (2.17)), the
ballistic velocity is slightly enhanced and the α parameter, as define in equation (2.18), is around
0.3.
Figure 2.11: (a) Relative change in the Si effective mass in the direction parallel and perpendicular to a
[110] uniaxial tension (open symbols: tight binding [82], filled symbols empirical pseudopotential [82],
solid lines: empirical pseudopotential [83]); (b) Relative change in Si electron ballistic velocity vs.
relative change in mobility for different strains (Results from Khakifirooz et al. [82]).
59
Based on the above discussion, for GAA nanowire n-MOSFETs, uniaxial tension along
<110> direction is expected to improve the electron mobility of these MOSFETs, which is
degraded by the low-mobility non-(100) sidewall surfaces. In chapter 4, this effect is
experimentally investigated for GAA nanowire n-MOSFETs.
For hole transport on the (100) surface, theoretical results show that compressive strain (up to
~3 GPa) can enhance the hole mobility ~5.5X over unstrained devices [74]. Uniaxial strain (even
small levels) along <110> is shown to significantly reduce the effective mass [82]. For (110)
surface, uniaxial strain along <110> direction is shown to improve the hole mobility of both
<110> and <111>-oriented channels [74, 85]. The reported mobility enhancement was larger
along <110> direction with an unusual Ns dependency, hypothesized by modulation of effective
mass only along <110> direction and only at low Ns [85].
For bulk (100) surface, biaxial strain lifts the LH and HH degeneracy and results in reduction
of phonon scattering. In addition, it is expected to repopulate the holes to the LH band which
benefits from effective mass reduction. However, in a quantized MOSFET, LH subbands move
to higher levels which is in the opposite direction of the band splitting by biaxial strain. While
there is some mobility enhancement due to reduced phonon scattering at lower Ns, the
enhancement disappears at higher Ns.
Application of biaxial strain to suspended nanowires is not technologically feasible. While Si
nanowires with high-hole-mobility non-(100) surface are considered as the transport booster over
bulk (100) devices, uniaxial compression along (110) is expected to further boost their hole
transport. Recent results by Li et al. shows +85% enhancement in short channel drain current of
GAA nanowire p-MOSFETs by uniaxial compression [88]. Figure 2.12 summarizes the
60
simulated hole and electron mobilities for (100) and (110) silicon substrates as a function of
stress [74]. A uniaxial strain of 3 GPa along <110> direction can continuously increase the
electron mobility up to 2.3X for (100) and up to 4.5X for (110) surface. Moreover, a uniaxial
compression of 3 GPa along <110> can enhance the hole mobility by 5.7X for (100) and 1.9X
for (110) surface. In addition, it can be seen that the orientation dependence of both electron and
hole mobilities is significantly reduced at very high-levels of uniaxial stress.
Figure 2.12: Simulated hole and electron mobility for (100) and (110) silicon substrates as a function of
uniaxial stress along <110> (Results from Packan et al. [74]).
2.4.3 Technological Implementation: New Materials and Processes
Strain-engineering methods are generally categorized into global and local strain
technologies. In the former, substrates are globally strained to another physical or virtual
substrate. Using this technique, biaxially strained-Si on bulk [8] or insulator [89, 90, 91] or
compressively strained-Si1-xGex (0 < x ≤ 1) on bulk [62, 92, 93, 94] or insulator [6, 95, 96, 97]
61
are created. The bulk process involves growth of strained-Si or SiGe using heteroepitaxy [98].
The “on-insulator” or “SOI-like” process can be realized using a bond and etch back technique
[90], smart-cut [99], Ge condensation by oxidation [97] or direct growth on thin-body SOI
substrates [95]. As the lattice size of SiGe is larger than Si, biaxial compressively strained-Si can
not be fabricated using this technique.
In the local or process-induced stress engineering, the strain is locally applied to the device.
SiGe-embedded source/drain [9, 14, 15], SiC- embedded source/drain [11, 101], contact etch
stop liners with tensile [102] or compressive strain [103, 104], Shallow-Trench-Isolation [105]
and stress memorization [106] are proposed by various groups for planar devices. However,
there are few reports on the application of strain to multi-gate and particularly GAA structures.
Verheyen et al. showed that SiGe-embedded source/drain improves the current of 50 nm-long pMOS FinFETs by 25% [107]. Liow et al. demonstrated 80% current enhancement for Geembedded tri-gate (W = 30 nm) short channel p-FETs [108]. Li et al. applied this method to 25
nm-long GAA NW and +85% p-MOS current enhancement was observed [88]. In some other
techniques, strain was applied by bending the suspended channel. Using thermal oxidation of
suspended long Si beams, Moselund et al. demonstrated “bended GAA” n-MOSFETs with
enhanced mobility over non-suspended structures [109, 110]. In other work, Si nanowires were
bent by metal gate stressor process [111].
The local strain engineering effectiveness in planar technology is reduced as the device pitch
size is aggressively scaled, mostly due to the limited physical space available for the local
stressors. Therefore, new schemes and approaches for strain engineering become more vital. A
biaxially strained substrate can be etched preferentially in one direction to asymmetrically relax
62
the strain in the lateral direction. Figure 2.13 schematically illustrates this concept. The
relaxation is believed to be elastic and free of any defect. Using Raman spectroscopy and stress
TCAD simulations, Lei et al. showed that uniaxial strained-Si can be achieved by patterning 30
nm thick strained-Si directly-on-insulator (SSDOI) substrates into 90 nm wide fins [112]. Using
nano-beam diffraction (NBD) technique, Usuda et al. mapped the strain in the Si fin and
confirmed that stress is uniaxial [113, 114]. FinFETs and and tri-gate [18,19, 115-118] have been
fabricated using this technique with enhanced long channel mobility and short channel current
drive due to uniaxial tension along the fin. Using a similar technique, uniaxially strained-Si1-xGex
(x ≤ 0.7) p-MOSFETs are reported with more than 3X mobility enhancement over planar devices
[119, 120]. Recently, Tachi et al. have demonstrated fabrication of gate-all-around nanowire pMOSFETs with relaxed and bent SiGe nanowire channels [121]. However, they observed low
enhancement factor for bent strained-SiGe channels and no enhancement (degradation) for
relaxed SiGe nanowires.
Figure 2.13: Schematic of the nano-patterning induced lateral relaxation mechanism. Arrows with solid
border show the direction of the strain and arrows with dashed line shows the lateral relaxation direction.
Biaxial stress is preferentially relaxed in the transverse (lateral) direction.
63
In chapter 4, the performance of the GAA n-MOSFETs with uniaxial tensile strain are
investigated. On the other hand, germanium channels have higher hole mobility compared to
bulk Si and can be considered as promising candidates for multi-gate GAA NW transistors.
However, there is no reliable top-down fabrication process to realize defect free Ge nanowires
and most of the reported data are based on bottom-up fabrication which has little interest for
CMOS applications [122-124]. A reasonable CMOS compatible approach is the Si/Ge core-shell
nanowire growth which can be achieved by selective epitaxy of Ge on Si fins or nanowire [125].
However, this method requires a mature defect-free germanium growth. Moreover, this method
is technologically limited by the very low critical-thickness of epitaxial Ge on Si and strongly
depends on the shape of core-Si nanowire. The preliminary results of fabrication and transport
characterization of top-down fabricated Si/Ge core-shell nanowire p-MOSFETs are presented in
Appendix F.
2.5 Mobility Extraction for Gate-All-Around
Nanowires MOSFETs
This section describes the effective mobility extraction methodology that is used in this thesis
for planar and nanowire MOSFETs. The low-field electron mobility of a MOSFET is given by
(2.41)
where Leff and Weff are the effective gate length and width of device, gd = ∂ID/∂VDS is the drain
conductance, Qinv and Q'inv is the total and density of inversion charge, in units of C and C/cm2,
64
respectively [4]. For bulk and planar devices, effective mobility is often expressed as a function
of inversion charge density (cm-2) or effective electric field, Eeff (MV/cm) defined as:
1
(2.42)
where Q'dep is the depletion charge density and εs is the dielectric constant of the channel. The η
factor is a key parameter in determining Eeff and was initially assumed to be a constant factor,
1/2 for electrons and 1/3 for holes [4, 62]. To maintain universality of mobility, Irie et al. showed
that η is indeed a function of Eeff , surface orientation and channel direction [73]. For nanowire
MOSFETs with various surface orientation and geometry-dependent field, the expression of
mobility in terms of Eeff is extremely complicated and the mobility is usually expressed as a
function of inversion charge density. In derivation of equation (2.41), the diffusion current ( ∂Qinv/∂x) was assumed to be negligible which is satisfied in practice for VDS in the range of 10 to
50 mV [126]. To extract the mobility of planar devices, typically a very long device (Leff ~ 50200 µm) is used to vanish the effects of external parasitic resistance and gd can be simply
presented by ID / VDS. Test structures have been proposed to cancel the series resistance of the
ultra-thin-body SOI devices, by means of addition of external tabs [127]. In addition, recessed
channel has also been proposed to locally thin the SOI device and leave the channel thick enough
in the vicinity of source/drain, to minimize the effects of the series resistance [63]. However,
knowing the external series resistance, Rext, corrected gd can be written as:
(2.43)
The inversion charge is given by:
65
(2.44)
where Ninv is the inversion charge density (in cm-2 units) and CGC is the intrinsic gate-to-channel
capacitance and can be directly extracted using split-CV method of a long cannel device. The
split C-V of devices can be measured at frequencies in the range of 1 kHz to 1 MHz, using a
semiconductor parameter analyzer. At lower frequencies, which are closer to the quasi-static
device operation, dielectric interface traps can respond leading to overestimation of the inversion
charge. Measurements at higher frequencies overcome this problem and also benefit from less
measurement noise. However, the measured capacitance can be misinterpreted due to the
external resistance dependence of the measured impedance. As a result, the measurements in this
thesis were performed in the range of 40-100 kHz where the aforementioned problems were
minimized.
Figure 2.14: (a) Effective hole mobility vs. inversion charge density (Ninv) for various hypothetical
voltage shift between capacitance and current measurements (ΔV) due to several mechanisms such as
measurement stress effects; (b) Relative mobility error (with respect to the case with no shift) as a
function of ΔV, for Ninv=1012, 4×1012 and 7×1012 cm-2. While large error is observed for low Ninv, the
error is less than 2% at high inversion charge densities.
66
It is very important to measure the I-V and C-V on the same device. For devices with nonideal high-κ dielectric the I-V and C-V characteristics show a finite hysteresis, similar
measurement sweep direction should be chosen. In other words, any shift in the threshold shift
due to hysteresis or unstable dielectric condition as a result of measurement stress leads to
inaccurate mobility extraction. To better understand this, Figure 2.14(a) shows a plot of hole
mobility in a thin-body planar SOI p-MOSFET, for various voltage shifts, ΔV, between the C-V
and I-V measurements. The relative mobility error for various inversion charge densities is
plotted in Figure 2.14 (b). While negligible error (less than 2%) is observed at high inversion
charge density, relatively large error (~15%) is observed for low inversion charge density
(Ninv=1×1012 cm-2) for ΔV = ±40 mV.
Nanowire MOSFETs have generally small capacitance originating from the nano-scale size
of the channel. In addition, due to the process issues such as limited e-beam write field size and
long exposure time for e-beam lithography as well as stiction issues, fabrication of very longchannel nanowires (in the scale used to characterize the mobility of planar devices) is not
practical. Medium channel lengths in the order of a micron are feasible. The importance of the
parasitic capacitances (Cpar) and Rext becomes more serious as Cpar is comparable to CGC in
medium channel-length devices. Fig. 2.15 (a) shows the measured split C-V characteristics of
medium-size planar devices with targeted gate length or mask length (LG) in the range of 0.4 to 2
µm. The plot of maximum capacitance (Cmax) and minimum capacitance (Cpar) as a function of
LG is shown in Figure 2.15 (b). It can be seen that Cpar is independent of the gate length. For the
device with LG = 0.4 µm, it is observed that Cpar is about 25% of the total capacitance which
leads to overestimation of the inversion charge by 25% and therefore underestimation of
mobility by ~20%. The difference between LG and the Leff, ΔL, can be extracted by intersecting
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the extrapolated plots of Cmax and Cpar of the planar devices, as shown in Figure 2.15 (b). For
nanowire MOSFETs, to acquire measurable capacitance signal, multi-nanowire device can be
fabricated. However, the parasitics also scaled similar to intrinsic nanowire capacitance which
adds more difficulty to the mobility extraction. As discussed in chapter 4 and 6, nanowire
devices have higher capacitive parasitics compared to planar devices due to the overlap of the
gate on the source/drain anchors.
Figure 2.15: (a) Measured capacitance of planar SOI MOSFETs with Al2O3/WN gate using split C-V
method for devices with mask gate length, Lmask = 0.4, 0.6, 0.8, 1, 1.2, 1.6 and 2 μm. For Lmask = 0.4 μm,
the parasitic component (Cpar) contributes about one fourth of the total measured capacitance. (b) Plot of
maximum capacitance (Cmax) and the minimum parasitic capacitance (Cpar, min) vs. Lmask. Symbols are
measured data and solid lines are the best fits to the measured data. The difference between the mask
length and the effective gate length (ΔL) was extracted by intersecting the two fitted lines.
Based on the above discussion, the effective mobility extraction of nanowire MOSFETs
requires careful considerations on the device design and parasitics. Consider a design where two
nanowire MOSFETs with the same number of nanowire (N) and similar cross-section, have
similar parasitic resistance (i.e. similar contact design rules and S/D materials) and capacitance
(i.e. similar fringing, gate-to-pad and gate-to-source/drain overlaps), similar threshold voltage
and mobility but two different nanowire or mask gate lengths (Li), as schematically shown in
68
Figure 2.16. The total channel resistance, Ri and total capacitance, Ci, of the ith device can be
written as:
,
,
,
(2.45)
(2.46)
,
Figure 2.16: (a) Schematic of the gate-all-around nanowire test structures for effective mobility
extraction, utilizing two FETs with the same number of nanowires (N) and similar cross-section (central
schematic), similar parasitic resistance (i.e. similar contact design rules and S/D materials) and
capacitance (i.e. similar fringing, gate-to-pad and gate-to-source/drain overlaps).
By taking two MOSFETs with various Li, and subtracting the total resistance capacitance, it
is possible to cancel the parasitics and extract the intrinsic mobility of a device with differential
L = L1 –L2. Using this technique (so called 2FET or double Lm method [128]), the effective
mobility can be calculated using equation (2.47) and fully written in terms of experimentally
measurable parameters:
69
μ
.
.
(2.47)
.
(2.48)
. .
Equations (2.47) and (2.48) can be corrected for any small shift in the threshold voltage of
two devices under test, simply via shifting both current and capacitances by the difference in
their threshold voltages.
Inversion charge density evaluation is a subject of controversy in nanowire MOSFETs.
Uniform dielectric is required to nearly equally invert the carriers over the entire nanowire
perimeter, which is not often achieved using thermally-grown or low-temperature oxides. The
effective nanowire width, Weff, used in equation (2.41) can be considered as the perimeter of
nanowire (Figure 2.16) to the first order estimation, and can be measured by Transmission
Electron Microscopy (TEM) analysis.
2.6 Chapter Summary
Basic theory and physics of the MOSFETs that are used in this thesis were overviewed in this
chapter. Following the discussion on the scaling theory of the MOSFETs, undoped Si nanowires
with relaxed channel thickness and excellent immunity to short channel effects are very
promising candidates for future low-power CMOS generations. In addition, the importance of
transport and mobility investigation for Si nanowires was discussed. Common scattering
mechanisms that affect the mobility of MOSFETs were reviewed. As multigate and nanowire
70
channels consist of several crystallographic planes, the role of surface orientation and channel
direction on the electron and hole transport was briefly reviewed. After a brief introduction to the
physics of strain engineering for various orientations, technological methods to apply strain on
planar, multi-gate and nanowire devices were reviewed. Based on the discussion of the surface
orientation and the few experimental results reported on multi-gate devices, sidewalls (even
ideally processed) degrade the performance of Si nanowire n-MOSFETs, while they can exhibit
the opposite trend for Si nanowire p-MOSFETs. As a result, uniaxial strain engineering along
<110> direction, particularly for n-MOSFETs, is expected to recover some of the mobility
degradation. Finally, the methodology used in this thesis to extract the mobility of Si nanowires
was extensively discussed in section 2.5.
71
72
Chapter 3
Asymmetrically Strained-Si and Ge
channels
The asymmetric strain engineering of globally-strained substrates is investigated in this
chapter. Two types of stress-engineered channels are introduced: asymmetric compressively
strained Ge and tensile suspended strained Si nanowires. Fabrication and detailed strain
characterization of these channels are discussed in section 3.2 and 3.3. Finally, a method to
vertically stack the suspended strained Si nanowires is demonstrated.
3.1 Biaxial to Uniaxial Strain Transformation
Globally biaxial-strained substrates, such as tensile Strained-Si-Directly-On-Insulator
(SSDOI) or strained-Si/strained-SiGe (Ge)/strained-Si Heterostructure-On-Insulator (SiGe (Ge)
HOI), can be fabricated by epitaxial growth of multiple SiGe and strained-Si layers on bulk Si,
followed by layer transfer to an oxidized wafer by bonding and either hydrogen-induced
delamination or etch back of the undesired materials. The so called bond and etch-back
73
technique was previously demonstrated for SSDOI [90] and SiGe [6] or Ge HOI substrates
[129], as schematically shown in Figure 3.1.
Figure 3.1: Schematic process flow of modified bond and etch-back technique to fabricate biaxial tensile
SSDOI or compressive Ge HOI, after Gomez, et al. [129].
Figure 3.2: Schematic diagram of fabrication of highly asymmetric, virtually uniaxial, strained-Si and
strained-Ge nano-structures by unilateral relaxation of SSDOI and Ge HOI substrates.
Although the in-plane strain in these as-fabricated substrates is biaxial, patterning induced
lateral relaxation can be utilized to transform the strain to uniaxial tension or uniaxial
74
compression, for SSDOI or Ge-HOI, respectively. Figure 3.2 schematically illustrates this
concept. It is worth mentioning that this type of strain relaxation is elastic and free of any
crystalline defects. This transformation is important as uniaxial strain lowers the conductivity
effective mass, reducing all scattering mechanisms and increasing the thermal velocity which
improves the ballisticity and hence the current drive in short channel devices.
3.2 Asymmetrically Strained-Ge Nano-Bars
3.2.1 Fabrication and Metrology
Starting substrates were strained-Si/strained-Ge/strained-Si HOI substrates which were
fabricated utilizing a bond and etch-back technique as described in Ref. [129]. Raman
measurements on these unpatterned HOI substrates indicate very high levels of strain in the ultrathin Si and Ge films (~1.8% biaxial tension and 1.8% compression, respectively). All epitaxial
layers were grown to be pseudomorphic to a relaxed SiGe virtual substrate with 50% Ge content.
The strained-Si cap layer was thinned down to ~4 nm using SC1 (5:1:1 H2O:NH4OH:H2O2)
solution at 80°C followed by 1 minute in 50:1 H2O:HF solution. Figure 3.3 (a) shows a crosssectional Transmission Electron Microscopy (XTEM) image of the initial substrate after thinning
the strained-Si cap layer. The measured thickness of the strained-Si cap layer is approximately 4
nm and the thickness of the strained-Ge varies from 5 to 7 nm. These values are in good
agreement with the results of spectroscopic ellipsometry. After standard cleaning, scanning
electron-beam lithography with XR-1541 Hydrogen SilsesQuioxane (HSQ) negative-tone resist
(from Dow Corning™) was utilized to pattern the samples into gratings with various bar widths
75
ranging from 300 nm down to 30 nm. The material characterization, optimization and process
development of HSQ is presented in Appendix A.
Figure 3.3: (a) Cross-sectional TEM image of strained-Ge HOI substrate. Tilted SEM images of (b) 100
nm and (c) 30 nm wide patterned strained-Ge HOI nano-bars prepared for stress metrology by UV microRaman spectroscopy (TEM Courtesy of M.D. Robertson).
To obtain a measurable Raman signal with acceptable signal to noise ratio (utilized for stress
characterization), dense patterns must be created. The pattern transfer was achieved by Reactive
Ion Etching (RIE) using Cl2/Ar precursors. Figure 3.3 (b) and (c) show sample Scanning
Electron Microscopy (SEM) images of the patterned HOI with different stripe widths of 30 and
100 nm.
3.2.2 Strain Characterization
UV Micro-Raman courtesy of Michael Canonico (Freescale) spectroscopy was used to
analyze the level of stress in the nano-scale strained-Si and strained-Ge layers [130, 131]. The
76
364 nm Ar-Ion and 325 nm He-Cd lines, both attenuated to minimize laser induced heating, were
used to measure the Si LO phonon from the strained-Si layer and the Ge LO phonon from the
strained-Ge layer, respectively. The 325 nm line is chosen for Ge scattering because in bulk
crystals, the Raman cross-section is resonantly enhanced by ~1.8X compared to 364 nm
excitation. Each Ge band was collected using a relatively long acquisition time of 30 minutes in
order to enhance the signal-to-noise ratio, and fitted with either Lorentzian or Exponentially
Modified Gaussian (EMG) line shapes. Since the HOI line widths are smaller than the laser spot
size (~0.4 μm diameter), spatially resolving the strain distribution is not possible. In addition,
resolving individual stress components using a micro-Raman geometry is difficult and often
impractical. Therefore, the analysis of the Raman data in this thesis is based on a planar stress
model, and we assumed phonon deformation coefficients consistent with uniform biaxial stress.
Figure 3.4: (a) Raman spectra (325 nm excitation) of the Ge LO phonon with overlaid Lorentzian fit for
Ge HOI sample patterned into 30 nm, 50 nm, 100 nm and 300 nm-wide stripes. Dashed line is the signal
from the relaxed Ge reference sample. For clarity, the Raman spectra and corresponding analytical fit are
shifted vertically relative to one another (Raman courtesy of M. Canonico (Freescale)); (b) Extracted
biaxial relaxation (solid lines) and Raman peak position (dashed lines) vs. bar width in strained-Ge layer.
77
Figure 3.4 (a) shows a series of Raman spectra of the Ge LO phonon in the strained-Ge
channel for the patterned long bars with widths ranging from 30 to 300 nm. The signal from a
bulk germanium substrate is also plotted as a reference. In this case, the average thickness of
strained-Ge is ~6 nm and the thickness of the strained-Si cap layer varies from 4 to 5 nm. From
this data, the shift in Raman peak position as a function of bar width can be extracted. The peak
position of the Ge mode and the calculated relaxation as a function of bar width is shown in Fig.
3.4 (b). The error bars are estimated from various sources such as XRD composition and
relaxation measurements for the 50% SiGe as-grown donor wafer, XRD composition of
nominally pure Ge HOI layer (courtesy M. Canonico, Freescale), phonon frequencies for
unstrained bulk Si, Ge, strained-Si and strained-Ge layers and uncertainties in phonon
deformation coefficients for Ge-Ge/SiGe and Si-Si/SiGe. As can be seen from Fig. 3.4 (b), the
relaxation in strained-Ge is increased by reducing the bar width and a relaxation of
approximately 45% (assuming biaxial compressive strain) is extracted for 30 nm-wide stripes.
Here, the relaxation values are calculated assuming the strained-Ge is fully strained, taking into
account the reduced Ge fraction due to inter-diffusion. A general trend of enhanced relaxation by
reducing the bar width is observed for all Si cap thicknesses, with more relaxation as the
thickness of strained-Si cap is increased [131]. The measured results are consistent with FiniteElement (FE) simulations [131] and atomistic model of strain relaxation [132]. In addition,
simulation by Park et al. indicates that increasing Ge thickness assists lateral relaxation at
relatively wider bar widths. For example, for a Ge HOI substrate with 10 nm Ge layer and no Si
cap, pure uniaxial strain is predicted for 30 nm bar widths. However, increasing the Ge thickness
is practically limited by the low critical thickness of strained-Ge on Si [12, 68]. In addition,
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processing Ge HOI without a Si cap is challenging due to process sensitivity of ultra-thin Ge
layer.
3.3 Suspended uniaxially strained-Si nanowires
3.3.1 Fabrication of Strained-Si Nanowires
Starting material was 150 mm SSDOI wafers (with buried oxide thickness of ~400 nm),
strained to a virtual Si0.70Ge0.3 substrate. A modified bond and etch-back technique was used to
create 30% SSDOI substrates [133]. A final strained-Si thickness of ~18-20 nm was measured by
a UV laser interferometer calibrated by SIMS/TEM measurements. The fabrication process of
strained-Si nanowires is schematically shown in Figure 3.5. After spinning ~90 nm HSQ e-beam
resist, e-beam exposure was performed in a Raith150™ scanning e-beam lithography system
with process details given in appendix A. Multiple parallel nanowires ending on two pads were
exposed. The width of the wires was varied in the range of 20 to 80 nm. The nanowires were 2
μm long and the pads were 2 μm × 1 μm rectangles. The pitch size (distance between nanowire
centerlines) was 100 nm for 20, 25, 30, and 35 nm-wide nanowires and 120, 150, 180, and 200
nm for 40, 50, 60 and 80 nm-wide nanowires, respectively. The dose and pitch were optimized to
minimize proximity effects. The resist was developed in 25% Tetra-Methyl-AmmoniumHydroxide (TMAH) solution for 1 minute. High nanowire density is an important parameter to
obtain a measurable Raman signal. In order to improve the Raman signal-to-noise ratio for
nanowires with dimensions around 20 nm or less, ultra dense suspended strained-Si NWs were
fabricated utilizing a modified thin HSQ and a salty developer [134], with details provided in
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Appendix A. The strained-Si layer was then dry etched using Cl2/Ar in a reactive ion etcher
(Figure 3.5(b)). The nanowires were suspended by time-controlled partial etching of the buried
oxide (80 to 100 nm removed) in 100:1 HF solution. A schematic cross section and top view of
the suspended strained-Si nanowire fabrication process is shown in Figure 3.5 (c) and (d),
respectively. The tilted SEM micrographs of 25 nm-wide suspended nanowires in a 100 nm pitch
and ultra-dense 18 nm-wide suspended nanowires in a 40 nm pitch are shown in Figure 3.5 (e)
and (f), respectively.
Figure 3.5: Schematic process flow of suspended strained-Si nanowires: (a) after spinning e-beam resist,
(b) after resist development and strained-Si reactive-ion etching, (c) after nanowire suspension in dilute
HF, and (d) top-down view. (e) Tilted SEM image of the 20 nm wide strained-Si nanowires in a 100 nm
pitch; (f) Tilted SEM image of the 18 nm wide ultra-dense strained-Si nanowires in a 40 nm pitch (inset:
top view SEM).
3.3.2 Raman Characterization and Stress Mapping
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UV Micro-Raman spectroscopy courtesy of M. Canonico (Freescale) was used to analyze the
level of stress in the suspended strained-Si nanowire and pad regions. The UV spectrometer was
operated in additive mode using 325 nm He-Cd laser line. The UV laser power density was ~300
kW/cm2 and the beam diameter was ~ 0.4 μm. Figure 3.6 (a) shows the Raman spectra of the Si
LO phonon from a 40 μm × 40 μm patterned square region, which approximates the original
blanket SSDOI layer strain. The Raman spectrum of a bulk Si wafer is also shown for
comparison. The Si LO phonon frequency is observed to be red-shifted by -8.9 cm-1, equivalent
to 2.16 GPa biaxial stress [112, 133]. The measured stress is consistent with the nominal value
of 30% Ge (+ 1 at. % Ge) in the relaxed SiGe donor substrate.
Figure 3.6: (a) Raman spectra (courtesy of M. Canonico (Freescale)) of the Si LO phonon from
unstrained bulk Si (dashed line) and the 40 μm square box (solid line). The measured Si peak shift is
consistent with the strain expected in Si grown on a relaxed SiGe donor substrate with 30% Ge
concentration. (b) Raman spectra at the center of suspended strained-Si nanowires (30 nm wide),
displaying two peaks corresponding to bulk Si substrate (right) and nanowires (left) with a ~2.1 GPa
uniaxial tension along the nanowires.
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Figure 3.6 (b) shows a typical Raman spectrum of the Si-Si LO phonon mode of suspended
30 nm-wide, 2 μm long strained-Si nanowires, at a location close to the center of Si nanowire. To
obtain such spectra, the laser was scanned from pad to pad in a direction parallel to the nanowire
length, as schematically shown in Figure 3.7 (b). The relevant Raman spectra for 30 nm wide
wires are shown in Figure 3.7 (a). Similar Raman spectra and total in-plane stress for the 18, 20,
25 and 40 nm wide nanowires are shown in Appendix B.
Figure 3.7: (a) Raman spectra (courtesy of M. Canonico (Freescale)) of the Si-Si LO phonon mode
for 30 nm wide suspended strained-Si nanowires with pads attached to the oxide, as the laser is scanned
from pad to pad in a direction parallel to the nanowire length , as shown in the schematic (b).
For 30 nm-wide nanowires with the spectra shown in Figure 3.7 (a), spectra #15 and #16
correspond to the Si substrate and spectrum #17-19 begins to show an asymmetry on the low
energy side. The broadening arises due to simultaneous illumination of the SSOI pad and
substrate. In spectra #20 and #21, the Si LO frequency further redshifts to ~515 cm-1 and the Si
substrate intensity diminishes as the laser beam scans across the pad. Beginning with spectrum
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#21, the peak frequency blueshifts slightly to ~516 cm-1 and the substrate signal reappears as the
laser beam transitions onto the wires and off of the pad. The increasing substrate intensity at
~520 cm-1 results from the laser beam passing between the wires. Spectra 22-27 correspond to
signal from the Si nanowires. Starting with spectrum #28, the strained Si signal intensity
increases and the substrate intensity decreases as the laser beam begins transitioning from the
wires back onto the second pad. Spectra #30 and #31 are representative of the pad alone. At
spectrum #32 and #33 the laser beam is beginning to move from the pad back onto the substrate,
and thus the overall signal is a convolution of both strained Si and substrate frequencies. Finally,
spectra #34 and #35 represent a signal collected solely from the substrate. All strain calculations
are based on a manual software fit to the spectral data using one or two Lorentzian functions
depending on the overall signal line shape and position of the laser beam, after canceling the
linear background signal (examples are given in Appendix B). Stress errors were calculated
based on various sources such as unstrained Si reference frequency, SSOI frequency, phonon
deformation potentials, and elastic constants. These measurements were performed at the limit of
both the spatial and spectral resolution of convention UV micro-Raman and the data and analysis
should be viewed within that context.
Additionally, micro-Raman configurations are not
conducive to observing the TO phonon band and thus a planar stress model with biaxial strain is
generally assumed. Therefore, to calculate stress in nanowire and pad regions from the observed
peak shifts, isotropic biaxial relaxation was assumed.
Micro-Raman measurements are not able to resolve the individual in-plane stress
components. Typically for large features or blanket films which are strained due to lattice
mismatched epitaxial growth, the planar stress model is used. However, for small patterned
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features with relatively high aspect ratios, uniaxial relaxation can occur [113, 135]. It is believed
that the biaxial to highly asymmetric strain (close to uniaxial) transition occurred upon patterning
the SSDOI films. After suspension, since the wires are free standing, elastic in-plane relaxation
in the direction perpendicular to the nanowires is highly likely, and we can assume that the strain
is mainly uniaxial with only a longitudinal component remaining.
Figure 3.8: Total in-plane stress (circles, left axis) and corresponding signal-to-noise ratio (squares, right
axis) for spectra collected from the 2 μm long nanowires midway between the two pads.
The total in-plane stress, σxx + σyy, at the center of the nanowire region as a function of
nanowire width is plotted in Figure 3.8 (left axis). As can be seen from this plot, the nanowires
are strained to a total in-plane stress of ~2.1 GPa with minimal width dependence. The righthand axis corresponds to the associated Raman signal to noise ratio (SNR). Note that the signal
to noise ratio falls significantly as the nanowire width is decreased. This is mainly due to fact
that the nanowire fill factor is decreased below widths of 40 nm. Nanowires with widths of less
than 40 nm were fabricated at a constant pitch size of 100 nm. As the gap size is increased by
reducing the nanowire width, the signal obtained from the substrate increases. Therefore, it is
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more difficult to deconvolve the signals from the substrate and wires and SNR is reduced. The
results for 18 nm wide, ultra dense nanowire (shown in Appendix B) indicate better signal to
noise ratio with total in-plane stress of ~1.7 GPa at the center of these nanowires.
3.3.3 Vertically-Stacked Strained-Si Nanowires
Si nanowires usually have lower integration density compared to planar devices, due to the
physical space requirement for the surround-gate architecture. As a result, nanowires usually
offer less current density for a given chip area. One practical approach to overcome this problem
is to increase the current density by vertically stacking the Si nanowires. Although this method is
capable of increasing the current drive of a device, since the capacitance is also scaled, is doesn’t
improve the circuit gate delay. Combining the uniaxial strain engineering technique with vertical
stacking is beneficial for both current drive enhancement and circuit delay improvement,
simultaneously. Figure 3.9 (a)-(c) shows a schematic process flow to fabricate suspended
vertically stacked Si nanowires. Starting wafers can either be relaxed Si1-xGex on bulk Si, relaxed
Si1-xGex on insulator, or strained-Si directly on insulator (SSDOI) with biaxial tension in the
strained Si. As shown in Figure 3.9 (a), a super-lattice consisting of strained-Si / relaxed Si1-xGex
is then epitaxially grown on the substrates. After a nanolithography step, the material is patterned
and vertically etched to create strained-Si/Si1-xGex pillars (Figure 3.9 (b)). The strained-Si
nanowires are then suspended by selective removal of the relaxed Si1-xGex sacrificial layers
sandwiched between the strained-Si nanowires, as schematically shown in Figure 3.9 (c). The
detailed process flow is provided in Appendix C. The proposed method is in principle
compatible with a CMOS structure where with the same stack, Si can be selectively removed so
that SiGe nanowires can be used as the channel for p-MOSFETs. Figure 3.9 (d) shows the top-
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view schematic of the Raman laser analysis areas used to characterize stress in the nanowires.
Test structures with N = 1 to 5 levels of vertical stack were fabricated on bulk relaxed Si0.7Ge0.3
substrates. Figure 3.9 (e) shows sample tilted SEM images of 1.4 µm long vertically stacked
suspended strained-Si nanowires with N = 1 to 5 stacked levels.
Figure 3.9: (a)-(c) Schematic of the process flow utilized to realize vertically stacked strained-Si
nanowires; (d) top view of the stacked-Si nanowires highlighting the region where Raman signal was
collected; (e) SEM images of N = 1 to 5 level vertically-stacked strained-Si nanowires.
Micro–Raman spectroscopy was used to measure the amount of strain in the as-grown
substrates as well as the nanowires. The micro-Raman measurements were performed at 458 nm
laser line and average power of 1 mW, in a backscatter configuration (no sample tilt) with an
Olympus™ 0.8 NA objective, allowing for sub-micron spatial resolution [136]. The stress
measurememts on starting substrates (shown in Appendix C) indicate that the Si is fully strained
even after 5 periods, with an average biaxial tensile strain 1.17% (2.1 GPa) [137].
Figure 3.10 (a) shows Raman spectra of the Si-Si LO phonon mode at the center of an array
of suspended strained-Si nanowires with WNW = 30 and 35 nm and N = 1 and 5 vertical stacked
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layers. WNW is defined as the plan-view SEM width of Si nanowires. The inset shows a top-view
schematic of nanowires where the approximate position of the laser beam is highlighted. As the
laser spot size is much larger than the nanowire diameter, each scan averages the signal taken
from many parallel wires. Again, two peaks are noticeable in the Raman spectra. The left peak
corresponds to the signal penetrated through the spacing between nanowires to the bulk Si0.7Ge0.3
region. The right peak corresponds to strained-Si nanowires. Compared to experiments
performed on SSDOI substrates (section 3.2), the use of a thick, relaxed SiGe substrate in the
present structures blocks the signal from the bulk Si substrate, reducing interference between the
bulk and strained-Si peaks. As a result, enhanced signal-to-noise ratio is expected when scanning
the strained-Si nanowires.
Figure 3.10: (a) Raman spectra (courtesy of C. D. Poweleit, ASU) of at the center of array of suspended
strained-Si nanowires with (WNW = 30 and 35 nm, and N = 1 and 5 number of stacked layers); (b) Biaxial
strain relaxation (with starting substrates as reference) vs. number of nanowires as a function of nanowire
width, indicating stress preservation after 5 layer stacking of nanowires.
Isotropic biaxial relaxation was assumed to quantify stress with a biaxial average defined as
(εxx + εyy) / 2, where εxx and εyy are the longitudinal and transverse components of the stress,
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respectively. To investigate how much relaxation results from the stacking process, biaxial strain
relaxation in nanowires as a function of stack number for WNW = 30 nm and 35 nm is plotted in
Figure 3.10 (b). Here the biaxial relaxation is defined as the difference in average biaxial strain
in the starting substrate and the center of the nanowires. No significant change in nanowire
strain, within the error bar of Raman spectroscopy, was observed due to the stacking process.
3.4 Chapter Summary
In summary, this chapter introduces two novel channel systems with asymmetric strain
configurations suitable for future CMOS generations. Compressively strained-Ge channels with
virtually uniaxial strain were demonstrated by elastic lateral relaxation of Ge HOI substrates
using a nano-patterning technique. UV-micro-Raman measurements indicate that approximately
45% of initial biaxial compression is relaxed for 30 nm wide Ge HOI nanowires, with a Ge
thickness up to 7 nm. In addition, a novel uniaxial suspended strained-Si nanowire technology
was successfully developed by lateral relaxation and release of SSDOI substrate, forming
suspended strained-Si nanowires with pitch sizes as small as 40 nm. The UV-micro-Raman
metrology on arrays of dense nanowires indicate that suspended nanowires were strained to total
in-plane stress (mainly uniaxial) of ~2 GPa with a minimal width dependency. Moreover, a
process was developed to realize vertical stacking of these suspended strained channels in the
third dimension. Stress measurements confirm that the strain is maintained even after five levels
of vertical stacking. Combined with the benefits of uniaxial strain technology, this technique has
potential to increase the current drive of gate-all-around MOSFETs at a given pitch size.
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Chapter 4
Gate-All-Around Uniaxially StrainedSi Nanowire n-MOSFETs
4.1 Introduction
This chapter describes the experimental results on the fabrication and electrical
characterization of Si and strained-Si nanowire n-MOSFETs. Section 4.2 briefly discusses about
fabrication and metrology of gate-all-around nanowire n-MOSFETs. The electrostatics and subthreshold characteristics of these devices is investigated in section 4.3. Section 4.4 evaluates the
performance of gate-all-around strained Si nanowires over unstrained Si nanowires in terms of
current drive, extrinsic and intrinsic transconductance. Finally, the electron effective mobility of
these devices is investigated in section 4.5.
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Figure 4.1: (a) Fabrication process flow of gate-all-around uniaxial strained-Si nanowire n-MOSFETs.
(b) Top-view and (c) side-view schematic of suspended uniaxially tensile strained-Si channel fabricated
by lateral relaxation and undercutting the nanowires. Inset shows the nanowire dimensions and stress
direction.
4.2 Device Fabrication and Metrology
The fabrication process flow for gate-all-around strained-Si nanowires is shown in Figure 4.1
(a). 150 mm-diameter Strained-Silicon-Directly-On-Insulator (SSDOI) wafers, strained to
Si0.7Ge0.3 virtual substrates, fabricated using a bond and etch-back method, were used as the
starting substrate. The Si layer was thinned to 21 nm by wet chemical oxidation and oxide
removal. For comparison, unstrained SOI wafers (thinned down to similar thickness by multiple
steps of dry-oxidation and oxide removal) were used as control devices. After defining e-beam
alignment marks by photolithography and reactive ion etching deep into the bulk Si, active layers
were patterned by hybrid lithography, where <110>-oriented multiple NWs (with widths of 20 –
60 nm) were defined by e-beam lithography and the source/drain pads were defined by
photolithography. Figure 4.1 (b) and (c) schematically illustrates the orientation and geometry of
the nanowires and the direction of the engineered stress by lateral relaxation. The <110>
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nanowire orientation was chosen to gain the maximum uniaxial strain-induced performance, as
discussed in section 2.4.2. The active layers were mesa-etched by reactive ion etching and
nanowires were then suspended by time-controlled wet etching of the buried oxide in a
hydrofluoric acid bath. Figure 4.2 (a) shows a sample SEM micrograph of 20 nm-wide
suspended strained-Si nanowires. As shown in chapter 3, the nanowires are uniaxially strained to
a high stress level of ~2 GPa, with little dependence on nanowire width. After RCA cleaning, the
nanowires were wrapped with Low-Temperature-Oxide (LTO) and in-situ n+-doped poly-Si. The
gate was aligned to the nanowires using a non-self aligned process. A misalignment accuracy of
less than 50 nm was achieved using a multiple exposure and correction process by i-line stepper
and SEM, respectively. The gate overlaps the S/D by approximately 100 nm or 400 nm,
depending on the design. Devices with nanowire lengths in the range of 0.4 to 10 μm were
fabricated. Source/drain regions were then implanted with phosphorus at energy of 19 keV to a
dose of 3×1015 cm-2.
During the nanowire release process, the S/D pad edges were also undercut (see Figure 4.2
(a)) and the gap was then filled with gate oxide and poly-Si stringers. The ion-implanted oxide
and poly-Si can provide a leaky oxide which can increase the sub-threshold leakage of the
device. As a result, a photolithography mask was designed to protect the gate and S/D pads
except the S/D edges, where the stringers were formed, as shown in Appendix D. The poly-Si
stringers were then reactive-ion etched using a sequential Si/oxide/Si/oxide/Si etch recipe. After
poly-Si stringer etch and inter-layer-dielectric deposition, S/D regions were activated by rapid
thermal annealing at 625˚C for 2 minutes followed by 800˚C for 10 seconds. Ti/Al metallization
and N2/H2 annealing finalized device fabrication. Control SOI samples with similar body
thickness went through the same process steps to compare the performance of strained-Si
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nanowire (SSOI NW) with the unstrained-Si nanowires (SOI NW). The fabrication yield was
improved for the strained devices relative to the unstrained ones, as the uniform tensile strain
prevents bending during processing. The device dimensions were calibrated by SEM and crosssectional TEM. Based on these calibrations, nanowires were laterally thinned to various widths
in the range of 50 to 8 nm, vertically thinned to thicknesses of ~8 nm, and the corners were
rounded during processing. Figure 4.2 (b) shows SEM micrograph of 0.8 µm long nanowire nMOSFET with 10 parallel nanowires after complete device fabrication. It can be seen that a
perfect gate to nanowire alignment is achieved. Evidence of the S/D stringer etch on the buried
oxide is also discernible, as the unprotected buried oxide is also exposed to the successive
stringer etch steps.
Figure 4.2: (a) Sample tilted SEM image of suspended strained-Si nanowires. (b) Top-view colored SEM
image of gate-all-around strained-Si nanowire n-MOSFET with 10 parallel nanowires. The poly-Si/LTO
gate stringers at the edge of ion-implanted source/drain pads were etched using a separate protection
mask.
Cross-sectional Transmission-Electron-Microscopy (XTEM) was used to calibrate the
dimension of the nanowires. Figure 4.3 illustrates sample XTEM images of strained-Si nanowire
n-MOSFETs with (a) 24.4×8 nm elliptical and (b) 8 nm diameter circular cross sections. The
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nanowires are fully wrapped with non-uniform LTO and poly-Si. The lattice images in the insets
indicate perfect crystalline structure in the nanowire channel. In addition, the nanowires show
rounded corners.
Figure 4.3: Cross-sectional TEM of gate-all-around n-MOSFETs with (a) elliptical and (b) circular crosssection strained-Si nanowires. The focused-ion-beam cut is perpendicular to the nanowire direction
(electron transport direction). Heavily-doped poly-Si gate and low-temperature oxide wraps all around the
Si nanowires. TEM performed at Evans Analytical Group.
4.3 Electrostatics and Threshold Voltage
Figure 4.4 shows the transfer (ID - VGS, in both linear and logarithmic scales) and output (ID VDS, in linear scale) characteristics of gate-all-around strained-Si nanowires with ~4 nm-radius
circular cross-section as shown in TEM image of Figure 4.3 (b). The device consists of 10
parallel nanowires with a length of ~0.65 µm. Normal MOSFET output and transfer
characteristics are observed for these sub-10 nm nanowires. Excellent cut-off characteristics
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(very low-level off current) with a sub-threshold slope (defined in equation 2.8) of 67 mV/dec
were achieved even with medium quality LTO.
Figure 4.4: Typical (a) transfer (ID - VGS) and (b) output characteristics (ID - VDS) for a circular crosssection gate-all-around strained-Si nanowire n-MOSFET with N = 10 nanowires, average nanowire
diameter of ~ 8 nm, and LNW ~ 0.65 μm. For (a), the left axis shows the current in logarithmic scale while
the right axis shows it in linear scale.
Figure 4.5(a) shows the plot of sub-threshold slope vs. nanowire width for various nanowire
lengths in the range of ~0.4 to ~1 µm. Sub-threshold slopes were calculated over a range of four
orders of magnitude from the off-state operation tail. The sub-threshold slope varies between 64
to 67 mV/dec, indicating a relatively low interface state density at the nanowire/LTO interface.
For comparison, the sub-threshold slope of devices with thermally grown oxide is also shown in
this figure, exhibiting near ideal swing of 60-63 mV/dec due to the better quality of the thermal
oxide compared to LTO. The small roll-up of the sub-threshold slope at smaller nanowire widths
can be attributed to the increased density of the interface traps at the nanowire sidewalls
compared to (100) horizontal surfaces. Figure 4.5 (b) shows the variation of the threshold voltage
as a function of nanowire width for strained Si nanowires and unstrained Si nanowires. The
threshold voltage was extracted by the linear extrapolation method [126]. Both types of devices
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are “normally on” (except sub-10 nm SOI nanowires) due to the interface and fixed charges of
LTO as well as fully-depleted nature of SOI and SSOI planar and non-planar devices. However,
in practical applications the threshold of these devices can be adjusted by gate workfunction
engineering. SSOI NW devices show a negative threshold voltage shift of 120 ± 30 mV relative
to unstrained devices confirming the presence of uniaxial tension, which lowers the conduction
band edge compared that in to unstrained nanowires. The shift is consistent with the results on
uniaxially-strained Tri-gate n-MOSFETs [80] and as expected is less than the shift for planar
biaxial devices (~340 mV). It can be seen that the threshold voltage increases with decreasing
nanowire width. This is attributed to both the lateral confinement of the electrons which
increases the conduction band (Δ2) energy (as discussed in section 2.3.2.3), as well as the
mobility degradation due to decrease in the nanowire width [63].
Figure 4.5: (a) Plot of subthreshold slope as a function of WNW and LNW for SSOI nanowires with lowtemperature oxide (LTO) and thermal oxide gate dielectrics showing near ideal subthreshold swing. (b)
Variation of threshold voltage (Vth) vs. WNW for SOI and SSOI nanowires showing Vth shift of -120 ± 30
mV due to uniaxial strain-induced conduction band shift. The Vth roll-up for sub 15 nm nanowires is due
to quantum mechanical confinement.
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Figure 4.6: Transfer characteristics of gate-all-around Si and strained-Si nanowire n-MOSFETs (with
LTO gate dielectric) showing near ideal subthreshold slope of 65 mV/dec. and ~2X current enhancement
and ~ 0.1 V strain-induced Vth shift.
4.4 Performance Evaluation
Figure 4.6 shows the transfer (ID - VGS) characteristics of gate-all-around SSOI and SOI
nanowire MOSFETs (LNW = 1 µm, tNW = 8 nm, WNW = 20 nm and N = 10), plotted on linear and
logarithmic scales. Both devices display excellent near-ideal swing of 65 mV/dec. In addition,
the threshold voltage of SSOI NWs are ~ -0.1 V shifted with respect to SOI NWs due to the
modulation of the conduction band by uniaxial strain. Strained nanowires also show more than
2X enhancement in current drive over unstrained nanowires at VGS = 1 V. In order to evaluate
the performance of these devices, the extrinsic low-field (VDS = 0.05 V) transconductance of
both devices are plotted as a function of the overdrive voltage (VGS-Vth) in Figure 4.7. Such a
plot can reduce the effects of the different turn-on voltage of strained and unstrained nanowires,
leading to a fair comparison of the extrinsic performance. An enhancement of 1.95X is achieved
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for peak transconductance of SSOI NWs over SOI NWs. It can be seen that the enhancement is
degraded at higher over drive voltages due to increased contribution of the external resistance as
a result of the high resistivity of the ultra-thin-body S/D regions.
Figure 4.7: (a) Extrinsic transconductance (gm) of SOI and SSOI Gate-all-around nanowires vs. overdrive
voltage (VGS-Vth) for nanowires with WNW  20 nm, tNW = 8 nm. SSOI NW exhibits a 1.95X enhancement
in gm, max relative to SOI nanowire devices. The enhancement at higher overdrives is degraded by
increased contribution of the external resistance.
To determine the intrinsic transconductance (gm,
int)
of these devices, the series resistance
(Rext) was extracted by plotting the linear total resistance (Rtot = VDS/ID) versus 1/(VGS-VthVDS/2), as shown in Figure 4.8 (a) [126, 138]. The extracted total Rext was ~7.3 kΩ for SSOI NW
and ~9.5 kΩ for SOI NW devices. These values are in reasonable agreement with results
obtained by the L array method [139]. Figure 4.8 (b) shows the gm, int of gate-all-around strained
and unstrained Si devices versus over-drive voltage, at VDS = 50 mV after correction for series
resistance using the above values and a method described in Ref. [140]. The strained-Si nanowire
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device shows an enhancement of ~2.1X in peak intrinsic gm and 1.86X at higher over-drive
voltages, compared to the unstrained Si nanowire device.
Figure 4.8: (a) Plot of total channel resistance vs. 1/(VGS-Vth-VDS/2) to extract external series resistance
(Rext) for SOI and SSOI nanowires vs. VGS-Vth (WNW  20 nm, tNW = 8 nm, N = 10). Rext (shown in the
figure) is extracted from the intercept of the extrapolated curve with the vertical axis. (b) Intrinsic
transconductance of these devices after correction for Rext. Enhancement factors of 2.1X at maximum gm
and 1.86X at VGS-Vth = 0.7 V are due to the uniaxial strain.
Fig. 4.9 compares maximum intrinsic transconductance, gm, max (measured at VDS = 50 mV
and after correction for Rext) versus WNW for unstrained and strained GAA devices (LNW = 0.8
µm, N = 10), illustrating enhancement in gm,
max
over the entire range of nanowire widths
investigated. It should be noted that even a 2 kΩ (~25%) change in Rext impacts gm, max by less
than 5% in these devices. This is because the current is dominated by the intrinsic nanowire
resistance. An average enhancement of ~2X extends to lateral dimensions in the sub-10 nm
regime, indicating the significant effect of uniaxial strain in deeply scaled Si nanowires.
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Figure 4.9: Intrinsic gm, max (VDS = 50 mV) vs. WNW for SOI and SSOI gate-all-around devices with LNW =
0.8 μm, tNW ~ 8 ± 1 nm and N = 10, displaying an average enhancement in gm, max of ~2X down to sub-10
nm nanowire dimensions.
4.5 Mobility Characterization
4.5.1 Split C-V Measurements
As discussed earlier in section 2.5, nanowires possess very small capacitance due to their
smaller area compared to planar devices. As a result, parasitics and background capacitance are
more pronounced. The capacitance of the fabricated devices was measured using an Agilent
4294A precision impedance analyzer which is nominally capable of measuring ~1 fF capacitance
at common frequency range used for split C-V measurements [141]. Capacitance signals
measured at regular frequencies used for planar devices, i.e. around 40 kHz, are very noisy with
approximately ±15-20 fF noise amplitude. The measurement noise is comparable or larger than
the intrinsic capacitance of the long nanowires (~10 µm long). Measuring capacitances at high-
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frequencies, i.e. 1 MHz, can noticeably lower the noise. It is well known from probability and
statistics that the standard variation of a random variable, σ, with N observations (measurements)
is reduced to σN given by:
(4.1)
/√
In other words, N times point averaging of the capacitance can lower the noise by the square
root of N. As a result, averaging of 40 measurements at 40 kHz can lower the noise to ~2.3-3.1
fF which is acceptable for capacitances on the order of 20 fF or more. The drawback of this
technique is the required long measurement time for every device (order of several minutes to an
hour).
Figure 4.10: Split capacitance-voltage characteristics of an SSOI nanowire n-MOSFETs (N = 10, WNW ~
49 nm, tNW ~ 8 nm, LNW = 10 µm) measured at f = 40 kHz and 40X point averaging to minimize the
noise. The gate-channel capacitance (Cgc) was extracted by subtracting the parasitic capacitance, Cpar,
(background and overlap capacitance, measured from devices without nanowires but with gate overlap on
the S/D regions) was subtracted from the total capacitance (Ctot). (b) Cgc vs. VGS for SSOI nanowire nMOSFETs (N = 10, WNW ~ 39 nm, tNW ~ 8 nm, LNW = 10 µm) extracted at f = 40 kHz and f = 1 MHz.
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Figure 4.10 (a) shows split C-V measurements of SSOI NW n-MOSFETs (N = 10, WNW ~ 49
nm, tNW ~ 8 nm, LNW = 10 µm) measured at f = 40 kHz with 40X point averaging (Ctot). The split
C-V of devices without Si nanowires but similar design structure, where gate poly-Si overlaps
the S/D pads, is also overlaid (Cpar). As devices are much longer than the gate-to-source/drain
overlap regions, Cpar can represent the background and parasitics capacitances with reasonable
accuracy. Thus, the intrinsic gate to nanowire channel capacitance, Cgc, can be approximated by:
(4.2)
Figure 4.10 (b) shows Cgc vs. VGS for SSOI NW n-MOSFETs (N = 10, WNW ~ 39 nm, tNW ~ 8
nm, LNW = 10 µm) extracted at f = 40 kHz and f = 1 MHz. The measured capacitances are in
good agreement (within less than 8%). The extracted Cgc for SSOI NW n-MOSFETs with WNW
= ~25, 39, and 49 nm are shown in Figure 4.11. These C-V characteristics are used for mobility
estimation in the following section.
Figure 4.11: Intrinsic gate-channel capacitance-voltage of gate-all-around SSOI nanowires with WNW =
25, 39, 49 nm. The background and overlap capacitances were subtracted from the original split-CV. 40
point averaging was used to reduce the noise.
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Figure 4.12: (a) Gate-channel capacitance and (b) total channel resistance of SSOI nanowire n-MOSFETs
(N = 10, WNW ~ 49 nm, tNW ~ 8 nm) with LNW = 10 µm (C1 and R1) and LNW = 4 µm (C2 and R2) used to
extract the mobility using the 2-FET method. The extracted Rext is also shown in (b).
4.5.2 Electron Mobility
Figure 4.12 shows the capacitance and the low-field channel resistance (equation 2.45) of the
SSOI nanowire n-MOSFETs (N = 10, WNW ~ 49 nm, tNW ~ 8.7 nm) with LNW = 10 µm (C1 and
R1) and LNW = 4 µm (C2 and R2), utilized for mobility extraction using the two FET method as
described in section 2.5. The ratio of maximum capacitances is 0.43 which scales quite well with
the ratio of the nanowire lengths (~6 % error). The error can originate from the variation and
length dependence of non-uniformly deposited LTO dielectric, as well as small differences in the
nanowire diameter of two devices due to lithography issues. The external resistance (Rext),
consists of the contact resistance, sheet resistance of the ion-implanted S/D and the resistance of
the overlap regions, and is calculated using:
(4.3)
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Extracted Rext has an average value of ~7 kΩ and approaches 6.1 kΩ at high gate overdrives.
These results are in very good agreement with the result extracted using the method described in
section 4.4, Figure 4.8 (a). The extracted low-field effective mobility, μeff, of the SSOI NW nMOSFETs (N = 10, WNW ~ 49 nm, tNW ~ 8.7 nm) using the split C-V (after correction for the
parasitics) and two FET methods are shown in Figure 4.13, demonstrating excellent agreement
between the two mobility extraction techniques. The average inversion charge density (Ninv) was
calculated by integrating the measured C-V data and normalizing to the surface area of the wires
given by 2L x (WNW + tNW). Universal (100) mobility [73] and the mobility of planar SOI and
SSDOI (tSi = 8.7 nm, close to the average thickness of SSOI NW) [67] and SOI NWs (WNW = 44
nm) are also overlaid for comparison. The SSOI NW device with WNW = 49 nm shows
enhancements of 1.22X, 1.69X, and ~ 2.57X over universal, thin-body planar SOI and SOI NW
devices (with slightly smaller width of ~ 44 nm), at Ninv = 1013 cm-2, respectively.
Figure 4.13: Low-field electron mobility (μeff) vs. charge density (Ninv) of SSOI NW (WNW = 49 nm, tNW
= 8.7 nm) measured by split-CV and 2-FET method. μeff for the widest SOI NW (W = 44nm), planar SOI
and SSDOI (tSi = 8.7 nm) (11), and universal are shown for comparison.
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4.5.3 Width Dependence of Electron Mobility
Figure 4.14 shows the effective electron mobility vs. average inversion charge density for
SSOI NWs with WNW in the range of 15-49 nm. For comparison, the electron mobility of an
ultra-thin body fully-depleted SOI MOSFET with body thickness of 8 nm is also shown [67].
SSOI NWs with WNW ≥ 20 show electron mobility enhancement over planar SOI MOSFET at
mid and high inversion charge densities. In addition, the mobility of 15 nm SSOI NW
approaches the planar SOI mobility at high inversion charge density, i.e. 1013 cm-2. It can be seen
that the nanowire mobility is reduced as WNW is decreased.
Figure 4.14: Low-field electron mobility (μeff) vs. charge density (Ninv) with WNW ~ 15, 20, 25, 39, 49 nm.
The electron mobility plot of fully-depleted ultra-thin-body (8 nm) SOI is shown for comparison [67].
Mobility is reduced as WNW is decreased, mostly due to an increase in the contribution of the sidewalls.
To further investigate the width dependence of the electron mobility of SSOI nanowires, the
variation of electron mobility as a function of WNW, for Ninv = 1013 cm-2 (filled triangles) is
shown in Figure 4.15 (a). For comparison, the mobilities of unstrained-Si nanowires from the
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literature are also overlaid (empty symbols with solid margin: Ref. [23], empty symbols with
dashed margin: Ref. [121]). A general trend of electron mobility reduction with decreasing
nanowire widths can be seen for all the three reports. It should be noted that the thickness of
nanowires is different in these three cases: 8-8.7 nm for SSOI NWs, 15 nm for SOI NWs of Ref.
[121] and 18 nm for SOI NWs of Ref. [23]. As a result, a better demonstration can be achieved
by plotting the electron mobility vs. the ratio of the low mobility sidewall width to the surface
width (Wsidewall / Wsurface), as shown in Figure 4.15 (b). The arrow in the figure points out that as
WNW is reduced, the ratio Wsidewall / Wsurface increases. Figure 4.15 clearly shows ~2X mobility
enhancement is achieved over the entire range of Wsidewall / Wsurface for SSOI NWs compared to
the highest electron mobility reported for SOI NWs (Ref. [121]). In addition, the mobility of SOI
NWs of Ref. [23] (fabricated using a similar approach to this work) are ~ 2.5 - 3.5X lower than
the mobility of SSOI NWs in this work.
Figure 4.15: (a) Electron mobility for SSOI NWs vs. (a) WNW and (b) the ratio of sidewall to surface
(Wsidewall / Wsurarface , as schematically shown in the inset) at Ninv = 1013 cm-2. Overlaid are the mobilities
of unstrained-Si nanowires (empty triangles: Ref. [23], empty squares: Ref. [121]).
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To better understand the width dependence of the electron mobility in Si nanowires, a simple
model is introduced in this section. The total conductance of the nanowire channel made on
(100) SOI, GNW, can be written as:
(4.4)
where GS and GSW are the conductance of two regions: the (100) surface and non-(100)
sidewalls, respectively. Equation (4.4) can be expressed in terms of the width (W), mobility (μ)
and charge density (n) associated with a given region by:
(4.5)
The S and SW indices refer to (100) surface and sidewall regions, respectively. The nS and nSW
are related to nNW as follows:
(4.6)
Equations 4.5 and 4.6 can be merged into the following equation:
1
1
1
(4.7)
1
where kW = WSW/ WS, rn = nSW/ nS, and rμ = μSW/ μS. kW is a geometric constant which is the ratio
of the sidewall width to the horizontal surface width and rn is the ratio of the inversion charge
density near the sidewall to that on the horizontal surface. The kW constant can be directly
extracted by metrology techniques such as TEM, or SEM and elipsometry and can be corrected
for quantum mechanical separation of the inversion charge from the nanowire/dielectric
interface. The rn ratio can be extracted by Schrödinger-Poisson charge simulations and is a
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function of device geometry. The ratio rμ is an empirical fit to the experimental data and includes
both intrinsic orientation effects as well as line-edge roughness scattering. In addition, as the
inversion charge density is different on the sidewalls and (100) surfaces, the rμ is not simply the
ratio of the mobility at given inversion charge density. For example, in an elliptical cross-section
nanowire at an inversion charge density of 1013 cm-2 at the top surface, if the average sidewall
charge density is 1.5X larger than the surface, the sidewalls have a lower mobility (compared to
the mobility at Ninv = 1013) due to the electric field dependence of the mobility. Thus, rμ is less
than what is expected by simply dividing the mobilities at Ninv=1013 cm-2. This adds some
complexity to the model described.
Figure 4.16: Electron mobility for SSOI NWs (solid symbols) and SOI NWs (open symbols, [121]) vs.
WNW at Ninv = 1013 cm-2. Lines are the empirical model with rμ = 0.34, 0.2 and 0.15 (with rμ decreasing in
the direction of the arrow) for SSOI NWs and rμ = 0.35 and 0.2 for SOI NWs.
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Figure 4.16 shows the mobility of SSOI NWs and SOI NWs (Ref. [121]) as a function of
WNW at Ninv = 1013 cm-2. Symbols and lines represent the results obtained by measurements and
using the simple model, respectively. For SSOI NWs, rn = 1.23 was extracted using SchrödingerPoisson charge simulations. For simplicity, the mobility of biaxially strained-Si was assumed for
μs [67]. In addition, the effective width of the device was defined geometrically as the perimeter
taken at the location of the charge centroid peak. As a result, only one fitting parameter, i.e. rµ,
was used for this model. Using data shown in Figure 2.7 from Ref. [73], and considering the
simulated rn = 1.23, rµ = 0.34 is extracted for the worst case. The results of this simple model for
rµ = 0.34, 0.2, and 0.15 are shown in Figure 4.16. The best mobility fits were achieved for rµ =
0.15-0.2, with small sensitivity to rµ. For SOI NWs from Ref. [121], the inversion charge density
was simulated using a Schrödinger-Poisson solver and the published geometry of the device
cross-section, and rn.kw = 0.51, 0.65, 0.74, 0.78 was extracted for WNW = 30, 20, 15 and 10 nm,
respectively (simulations courtesy of J. T. Teherani). Figure 4.16 shows the modeling results for
SOI NWs with rµ = 0.35 and 0.2, corresponding to the nominal ratio and the best fit, respectively.
For both types of nanowires, at least 42%-56% reduction in rµ is observed from its nominal value
(where the nominal value is estimated from the orientation dependence of the mobility, i.e. the
electron mobility ratio for the (110) and (100) surfaces, accounting for the local difference in
inversion charge density). Assuming this simple model is valid, this deviation of the mobility
ratio is attributed to the sidewall roughness scattering.
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4.6 Chapter Summary
In summary, this chapter was focused on the fabrication and electrical characterization of
gate-all-around nanowire n-MOSFETs with novel uniaxial tensile strained-Si channels. Longchannel nanowire devices with nanowire widths in the range of 49 nm down to 8 nm exhibit
excellent electrostatics with near ideal sub-threshold slope and very high on-to-off ratio. The
threshold voltage of strained-Si nanowire n-MOSFETs was increased compared to unstrained-Si
devices as a result of uniaxial strain in the channel. The performance of these devices was also
investigated in terms of drain current, extrinsic and intrinsic transconductance and low-field
electron mobility, all revealing noticeable enhancement over planar fully depleted SOI nMOSFETs and ~2X enhancement over unstrained-Si nanowires fabricated in this work as well as
those reported in the literature. The width dependence of the mobility was also investigated and
it was observed that the mobility decreases as the nanowire width is decreased. This mobility
reduction is attributed to the increased contribution of the sidewalls with lower mobility due to
their naturally larger effective mass as well as sidewall roughness scattering. Finally, a simple
analytical model was developed to investigate the width dependence of electron mobility in
strained-Si and unstrained-Si nanowires. This model uses only a single fitting parameter, i.e. the
sidewall to surface mobility ratio, and verifies that the electron mobility reduction with
decreasing nanowire width can be described by increased contribution of the low-electronmobility sidewalls. In addition, the mobility ratio is deviated from the nominal theoretical value
by more than 42%, which is believed to be due to the sidewall roughness scattering, resulting
from the non-ideal lithography and RIE process.
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110
Chapter 5
Device Design and Process Technology
for Gate-All-Around Si Nanowire pMOSFETs
5.1 Introduction
As discussed earlier in chapter 2, gate-all-around nanowire p-MOSFETs have potential to
offer enhanced hole transport properties compared to planar devices, because of the highmobility (110) sidewall planes. Careful design and fabrication process are critical in order to
accurately investigate transport in such structures. Towards this end, this chapter provides key
design and process fundamentals to facilitate the analysis of carrier mobility in Si nanowires.
The new design utilized in this thesis to fabricate gate-all-around nanowire p-MOSFETs is
introduced in section 5.2. The role of maskless high-temperature hydrogen anneal on the shape
of suspended Si nanowires is given in section 5.3. Finally, this chapter ends with the
characterization of the atomic-layer deposited (ALD) high-κ and metal gate process technology
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utilized for fabrication of gate-all-around nanowire transistors, and the effect of various ALD
deposition conditions on the hole mobility of planar SOI MOSFETs is investigated.
5.2 Device Design for Accurate Mobility Extraction
The fabrication flow of gate-all-around Si nanowire p-MOSFETs is shown in Figure 5.1.
Starting wafers were 150 mm, (100)-oriented SOI wafers (100 nm Si / 200 nm buried-oxide).
The Si thickness was thinned to ~20 nm by multiple cleaning, oxidation and oxide removal steps.
After definition of e-beam lithography alignment marks, Si nanowires along <110> direction and
S/D pads were defined by hybrid lithography. The new design features 100 µm-wide S/D pads
which allows accommodation of N = 500 parallel nanowires in a 200 nm pitch and sub-1.2 µm
S/D spacing Keeping the nanowire length, LNW, below 1.2 um helps to avoid stiction problems
between the nanowire and substrate. The increased number of nanowires leads to a significant
enhancement of the capacitance signal. After reactive-ion etching of Si and stripping the resist,
nanowires were locally released using a protective photoresist mask and a buffered-oxide etch
bath. Figure 5.2 shows the schematic of Si nanowires with S/D edges protected by the “local
release mask” (a) before suspension and (b) after local release and resist strip. These process
steps eliminate the formation of gate stringers, minimizing the parasitic capacitance and leakage
current.
The suspended nanowires were then RCA cleaned and subjected to a hydrogen anneal
process in an Applied Materials Epi Centura™ reactor. The process details of the maskless
hydrogen anneal are given in section 5.3. After hydrogen annealing, each wafer was immediately
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transferred to an atomic-layer deposition system were an interfacial SiO2 / Al2O3 dielectric and
tungsten-nitride (WN) metal gate was deposited on top of planar mesas and all around suspended
Si nanowires. ALD high-κ/metal gate was chosen for several reasons. Although thermally grown
oxide benefits from excellent interface with Si nanowires, the facet dependence of the growth
usually results in a non-uniform oxide thickness for various crystallographic planes which
complicates the electrical analysis [141]. In addition, thermally grown oxide can induce a
significant amount of stress in the nanowires which can alter their intrinsic carrier transport
properties [109, 110, 141, 142]. Low-temperature chemically-deposited oxide is also nonconformal and difficult to scale below thicknesses of about 4 nm due to the high gate-leakage.
However, the ALD dielectric benefits from scalability to thinner effective-oxide-thicknesses
(EOT) and its excellent conformality ensures that the entire perimeter of the Si nanowire is
uniformly gated. The details of the high-κ/ metal-gate process used for this experiment are
provided in section 5.4.
Figure 5.1: Process flow utilized to fabricate gate-all-around nanowire p-MOSFETs with high-K/metal
gate and hydrogen annealing process.
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After gate stack deposition, the gate was patterned via a non-self-aligned photolithography
step with less than 100 nm overlap on the source/drain. Any misalignment was diagnosed by
SEM imaging and lithography was repeated until the desired accuracy was achieved. The
overlapped gate structure was designed for two reasons. First, it helps to minimize the S/D
external resistance as the ion-implanted nanowires may exhibit very large series resistance.
Second, it is technologically difficult to remove the metal gate stringers under the nanowires if
the gate is underlapped. Moreover, any gate-first process to be used after vertical etching of the
gate, requires an isotropic etch of the gate metal stringers under the nanowires which also
laterally etches the bottom gate and results in high extension resistance.
Figure 5.2: (a) Schematic of the protection mask to locally release the Si nanowires. (b) Schematic of the
suspended Si nanowires after local release in buffered-oxide-etch, demonstrating no space available for
gate-stringer at source/drain edges. (c) Schematic of design layout of the Si nanowire MOSFETs,
displaying the contact vias, gate-to-pad overlap (< 100 nm), distance between contact via and the gate
edge (dvia-gate< 400 nm), and between contact via and metal edge (dvia-metal< 400 nm).
After WN gate etching in an SF6 plasma, source/drain regions were ion-implanted with boron
at a dose of 2×1015 cm-2 and energy of 5 keV. LTO inter-layer-dielectric was then deposited
while exposing the high-κ/metal gate to a temperature of 400°C for a few hours, source/drain
regions were activated at 640°C for 10 minutes, followed by annealing in forming gas at 500°C
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for 30 minutes. Compared to the previous design described in chapter 4, the new design also
features a tighter contact pitch design with the i-line stepper to minimize the series resistance.
Figure 5.2 (c) illustrates the schematic of design layout for the Si nanowire MOSFETs,
displaying the contact vias, gate-to-pad overlap (< 100 nm), distance between contact via and the
gate edge (dvia-gate< 400 nm), and between contact via and metal edge (dvia-metal< 400 nm). After
contact via opening and Ti/Al deposition and patterning, the fabrication was completed by a
forming gas annealing at 450°C for 30 minutes. The process details and recipes are given in
Appendix E.
Figure 5.3: Schematic device structure of the gate-all-around nanowire MOSFETs designed for mobility
extraction. A-A’ and B-B’ cut-lines represent the device cross-sections perpendicular and along the
nanowire direction, respectively. Device dimensions (WNW, Wtot, tNW, LNW, Lov and N), channel resistance
(RNW and Rov), and capacitive (Cpar) and resistive (Rext) parasitics are shown on the B-B’ cross-section.
Figure 5.3 schematically illustrates the device structure of the gate-all-around nanowire
MOSFETs designed for accurate mobility extraction. A-A’ and B-B’ cut-lines represent the
device cross-sections perpendicular and along the nanowire direction, respectively. Device
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physical dimensions such as nanowire width (WNW), nanowire height (tNW), total nanowire
perimeter, (Wtot), nanowire length (LNW), number of parallel nanowires (N), and gate-to-pad
overlap length (Lov) are indicated. The total source to drain resistance includes external
resistance, Rext, and channel resistance, Rch. The former consists of the contact resistance (Rc)
and resistance of the ion-implanted source/drain (Rs). The latter mainly consists of the nanowire
intrinsic resistance as well as gate-to-pad overlap resistance, which has a minor contribution for
long-channel devices. In addition, Figure 5.3 illustrates some major components of the parasitic
capacitances (Cpar, other than gate-to-nanowire capacitance) such as gate-to-S/D pad, gate-to-S/D
metal, and gate-to-S/D capacitances.
Figure 5.4: (a) Tilted and (b) cross-sectional SEM images of the final gate-all-around nanowire pMOSFETs with high-κ/metal-gate, with a FIB cut along the suspended nanowire direction.
Figure 5.4 (a) shows a tilted SEM image of the gate-all-around nanowire (N = 500 nanowires
and LNW = 1 µm) p-MOSFET with high-κ/metal gate process after complete device fabrication.
In order to prepare the sample for cross-sectional SEM analysis, the devices were cut using an
FEI Helios Nanolab™ 600 Dual-Beam™ Focused-Ion-Beam (FIB) milling system. Figure 5.4
(b) shows a cross-sectional SEM micrograph of a gate-all-around nanowire p-MOSFET cutting
along the direction of the Si nanowires. The Si nanowires and the S/D pads under the gate are
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clearly discernible in this picture due to excellent contrast between the gate-stack and Si, as
opposed to the poor contrast between SiO2 and Si. The area under the end of the Si nanowire
shows a quarter-circle like profile, due to the isotropic nature of the oxide wet etching, which is
fully covered with the WN gate.
5.3 Hydrogen Anneal Process
The effects of hydrogen thermal annealing on the morphology of Si trenches, corners, and
fins have been investigated by various groups, over the past decade [144-151]. Hydrogen thermal
annealing at very high temperatures (800-1100°C) was initially found to transform the shape of
rectangular Si trenches, etched on bulk Si substrates, to circular cross-sections [144]. Using
molecular dynamic simulations, Sato et al. suggested that Si migration around the corners to
minimize the number of dangling bonds and the surface potential energy is the dominant
mechanism. Kuribayashi et al. showed that increasing the hydrogen pressure can reduce the
reshaping of Si trenches [145]. At higher pressure, the increased density of H2 molecules
adsorbed on the Si surface enhances the energy barrier for diffusion of Si atoms which can
reduce the chance of surface migration and reshaping of the trench corners. Lee et al. showed
that hydrogen annealing of Si fins at 900°C with a thick nitride hard mask results in an increased
saturation current with a lowered threshold voltage and a decreased low-frequency noise level
[146]. On the similar structures, Xiong et al. showed that hydrogen anneal improves gate leakage
and reduces the width of the fins resulting in a lower threshold voltage and improved DIBL
characteristics [147]. Zaman et al. demonstrated that maskless hydrogen annealing of the Si fins
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suffers from reduction of the fin size and therefore reduction of the effective width of Si in Trigate MOSFETs [148]. Recently, Tezuka et al. showed that annealing of the Si fins (~67 nm
wide) with oxide hard mask at temperatures above 925°C results in the etching of Si fins and
formation of narrower fins (~34 nm wide) with smooth (110) sidewall [149]. The etching
reaction was attributed to the formation of volatile Si-hydride in reactions such as Si+H2→SiH2
or Si+2H2→SiH4 [150]. In a recent report, Dornel et al. revealed that three-dimensional arrays of
top-down fabricated Si nanowires with 45×20 nm rectangular cross-section were reshaped to
circular cross-section with 35 nm diameter, after hydrogen annealing at 850°C and 20 torr [151].
They also showed that annealing at temperatures higher than 850°C leads to nanowire pinch-off
at the pad/nanowire ends and can result in nanowire breakage due to surface diffusion of Si
atoms. In this section, the effects of maskless hydrogen anneal at various temperatures are
investigated.
Figure 5.5: (a) Schematic and (b) top-view SEM of suspended Si nanowires before and after hightemperature hydrogen annealing. The right SEM images were enhanced for brightness, contrast and
shadows to magnify the line edge roughness of the Si nanowires. Reduced sidewall roughness is observed
after hydrogen annealing.
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Suspended Si nanowire test structures were fabricated using a top-down approach, as
discussed in section 5.2. After a modified RCA clean with an HF last step and rinsing in DI
water, hydrogen annealing was performed at a temperature of 850°C and a pressure of 100 torr
for 2 minutes, in an Applied Materials Epi Centura™ reactor. Figure 5.5 shows the schematic
and top-view SEM images of 20 nm-wide suspended Si nanowires before and after hightemperature hydrogen annealing. The right SEM images were enhanced for brightness, contrast
and shadows to magnify the line edge roughness of the Si nanowires. Reduced sidewall
roughness after hydrogen annealing is apparent from these images.
Figure 5.6: (a) Plan-view SEM images of suspended Si nanowires subjected to hydrogen anneal at
850°C, with WNW = 14-73 nm; (b) XTEM of on-wafer nanowire test structure (as-patterned WNW = 20 to
60 nm; step 4 nm) subjected to hydrogen anneal at 850°C, after device completion. Nanowires are
surrounded by conformal ~1 nm ALD O3-SiO2 / 5.5 nm Al2O3 / 30 nm WN gate stack (stack κ = 7.4). For
wide nanowires, tNW = 16 nm; dropping to 13 nm for the circular nanowire. (110), (111) and (311)
sidewall facets are discernible from the XTEM images.
Figure 5.6 (a) illustrates plan-view SEM images of suspended Si nanowires subjected to
hydrogen annealing at 850°C, with WNW =14-73 nm, demonstrating extremely smooth sidewalls
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with roughness below the detection limit of SEM. In order to investigate the cross-sectional
shape of the Si nanowires after hydrogen annealing, suspended nanowire test structures were
fabricated with as-patterned WNW = 20 to 60 nm with an incremental step size of 4 nm, in
vicinity of the devices on the die. This test structure allows on-wafer calibration of the nanowire
dimensions, without need for costly TEM imaging of every single device. Figure 5.6 (b) shows
XTEM images of such a test structure subjected to hydrogen anneal at 850°C, after device
completion. The nanowires are labeled #1 to #11. High-magnification XTEM images of
nanowire #1 to #8 are shown at the bottom row. Nanowires are surrounded by conformal 1 nm
ALD O3-SiO2/ 5.5 nm Al2O3/30 nm WN gate stack (stack κ = 7.4 as determined from planar
capacitors). For wide nanowires, tNW = 16 nm, dropping to 13 nm for the smallest nanowire,
which is has a circular cross-section.
It can be seen that the sidewalls are faceted to
crystallographic planes after hydrogen annealing. The angles between the (001) plane and the
facets are ~25°, 54°, and 90° which correspond to {311}, {111} and {110} crystallographic
planes, respectively. The results are very close to the facets reported by Vescan et al. for the
selective epitaxy of Si on (001) Si surface [152]. In addition, unlike the results of Ref. [151], no
nanowire pinch-off or breakage at the S/D anchors was observed.
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Figure 5.7: SEM image of array of nanowire test structure (a) as-patterned, (b) after hydrogen annealing
at 875°C and (c) after hydrogen annealing at 900°C. Anisotropic hydrogen etching and nanowire pinchoff at the pad/nanowire boundaries are observed for annealing at temperatures higher than 875°C.
For hydrogen annealing above 850°C, significant reduction of the nanowire dimensions was
observed. This is attributed to either migration of the Si atoms to the S/D anchors or thermal
etching of the Si nanowires. Figure 5.7 shows SEM micrographs of a test structure with an array
of nanowires (a) as-patterned and before hydrogen annealing, (b) after hydrogen annealing at
875°C and (c) after hydrogen annealing at 900°C. Again, very smooth sidewalls are achieved.
Moreover, rough Si nano-beams at the boundary of Si nanowires and S/D pads (formed as a
consequence of hybrid-lithography) are completely flattened. In addition, Si nanowires
dimensions are significantly reduced at these elevated temperatures and nanowire pinch-off and
breakage at the pad/nanowire boundaries are observed for narrower nanowires annealed at
temperatures higher than 875°C.
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Figure 5.8: High-resolution Focused-Ion-Beam (FIB) cross-sectional SEM image of a nanowire test
structure (with as patterned WNW = 20 to 60 nm; step 4 nm) subjected to hydrogen anneal at 850°C
followed by 875°C, after device completion. Nanowire diameters (dNW, as defined in the SEM image) are
scaled from 22 nm down to sub-10 nm, mostly with circular cross sections.
Figure 5.8 shows a high-resolution (HR) Focused-Ion-Beam (FIB) cross-sectional SEM
image of a nanowire test structure (with as patterned WNW = 20 to 60 nm; step 4 nm) subjected to
hydrogen annealing at 850°C followed by 875°C, after device completion. The nanowires are
labeled #1 to #11. The bottom row shows higher magnification HR-SEM images of nanowires
with #1, #6 and #11 index numbers. It can be seen that nanowire diameters (dNW, as defined in
the bottom-right SEM image) are scaled from 22 nm down to sub-10 nm, mostly with circular
cross sections. The electrical characteristics of the nanowires subjected to hydrogen anneals with
conditions similar to that shown in Figure 5.6 and 5.8, where the nanowires are mildly smoothed
or reshaped by hydrogen annealing, are investigated in chapter 6.
5.4 High-κ/Metal Gate Process
In order to develop a high-κ/metal gate process it is necessary to perform experiments on
planar SOI wafers for basic material and electrical characterization, which is the subject of this
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section. As discussed in section 5.2, thermally grown oxide or low-temperature oxide suffer from
various issues such as scalability, conformality, undesired stress induction or bending the Si
nanowires. On the other hand, ALD dielectrics benefit from scalability to thinner effectiveoxide-thicknesses (EOT) and their excellent conformality ensures that the entire perimeter of the
Si nanowire is uniformly gated. High-κ/metal gate deposition used for this thesis was performed
in a Cambridge Nanotech™ ALD system. Between two possible dielectric options, HfO2 and
Al2O3, Al2O3 was chosen due to its lower interface trap density and hysteresis behavior
compared to HfO2. HfO2 benefits from better scalability and less gate leakage at sub-1 nm
effective oxide thickness (EOT). However, the EOT achieved using Al2O3 is low enough for
long channel devices fabricated in thesis to accurately extract mobility in gate-all-around
nanowire MOSFETs. In addition, Al2O3 benefits from better thermal stability at hightemperatures required to activate the S/D, i.e. 640°C, in a gate-first process approach.
Furthermore, processing Al2O3 is much easier to etch than HfO2, particularly for contact via
opening as HfO2 crystallizes after S/D activation anneal, turning into an extremely difficult
material to etch [153]. The electrical characterization of Al2O3 and WN, as well as hole mobility
of planar SOI devices with Al2O3 and WN are investigated in this section.
5.4.1 ALD Al2O3/WN Stack with O3 Surface Passivation
Prior to Al2O3 deposition, planar thin-body SOI wafers were subjected to 7 cycles of in-situ
ALD O3 treatment. The ALD systems was fed through an O3 generator operated at 80% cell
power with 560 sccm O2 flow and ~0.04-0.05 sccm N2 flow. Al2O3 was deposited using a Tri-
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Methyl-Aluminum (TMA) source at temperatures of 200°C and 250°C. Figure 5.9 (a) shows the
split capacitance-voltage (C-V) characteristics of SOI p-MOSFETs with 7 cycles of ALD O3, 60
cycles of Al2O3 and 1200 cycles of WN metal gate, measured at f = 1, 10 and 100 kHz. The
Al2O3 was deposited using a TMA source at 200°C, with a deposition rate of 1.0 Å per cycle.
The WN was deposited at 340°C with a deposition rate of ~0.3-0.4 Å per cycle. Figure 5.9 (b)
shows the corresponding forward and reverse sweeps at f = 100 kHz. Figure 5.10 shows the same
set of split C-V curves for 7 cycles of ALD O3, 55 cycles of Al2O3 and 1200 cycles of WN metal
gate, where the Al2O3 was deposited using a TMA source at 250°C. While the former deposition
condition (at 200°C) shows ~80 mV hysteresis and some frequency dependence, the frequency
dependence is significantly reduced in the latter condition (at 250°C) and hysteresis is
completely eliminated. These results indicate excellent interface properties for SiO2/Al2O3/WN
stack with Al2O3 deposited at 250°C and similar process conditions are used to fabricate gate-allaround nanowire p-MOSFETs.
Figure 5.9: (a) Split capacitance-voltage characteristics of SOI p-MOSFETs with 7 cycles of ALD O3, 60
cycles of Al2O3 and WN metal gate, measured at f = 1, 10 and 100 kHz ; The Al2O3 dielectric was
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deposited using Tri-Methyl-Aluminum (TMA) source at 200°C. (b) Corresponding forward and backward
sweeps at f = 100 kHz, showing 80 mV hysteresis.
Figure 5.10: (a) Split capacitance-voltage characteristics of SOI p-MOSFETs with 7 cycles of ALD O3,
55 cycles of Al2O3 and WN metal gate, showing negligible frequency dependence at f = 1, 10 and 100
kHz; The Al2O3 dielectric was deposited using Tri-Methyl-Aluminum (TMA) source at 250°C. (b)
Corresponding forward and backward sweeps at f = 100 kHz, showing no hysteresis.
5.4.2 Planar SOI Mobility
The mobility characteristics of planar SOI p-MOSFETs with SiO2/Al2O3/WN stack, where
Al2O3 was deposited at 200°C and 250°C, are shown in Figure 5.11. Effective hole mobility of
similar stack with Al2O3 deposited using a Tris-Di-Methyl-Amido-Aluminum (TDMAA) source
at 200°C is also shown for comparison. Similar mobility behavior is observed by deposition of
Al2O3 at 200°C using TMA and TDMAA sources. It can be seen that the hole mobility is about
30% degraded compared to universal at high inversion charge densities. However, the hole
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mobility of SOI p-MOSFET with Al2O3 deposited using a TMA source at 250°C tracks the
universal curve, consistent with the excellent C-V characteristics shown in section 5.4.1.
Figure 5.11: Effective hole mobility vs. inversion charge density (Ninv) for planar SOI devices with ALD
O3-SiO2 / Al2O3 / WN process. Al2O3 was deposited using Tri-Methyl-Aluminum (TMA) at 200°C and
250°C and Tris-Di-Methyl-Amido-Aluminum (TDMAA) at 200°C.
5.4.3 Tungsten Nitride (WN) Workfunction
Tungsten-nitride deposited by sputtering has recently been shown to have a work function
near the valence band of Si [154]. In order to extract the work function of ALD WN, p-Si wafers
with a doping density of ~1.3×1015 cm-3 were thermally oxidized to an oxide thickness of 40 nm.
Using multiple photolithography steps to protect some quarters of the wafer, the SiO2 layer was
partially etched by a time controlled wet etch. After cleaning the wafer in Piranha solution, the
wafer was exposed to 7 cycles of O3, 55 cycles of the optimized Al2O3 and 1000 cycles of WN in
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the ALD system. Using this approach, capacitors with four oxide thicknesses were fabricated
using a single ALD run. Figure 5.12 (a) shows the schematic of the structure used to extract the
WN workfunction. The flat band voltage of the capacitors was extracted by plotting 1/(C/Cox)2
vs. VGS and extracting the knee point, as described in Ref. [126]. The variation of VFB as a
function of Capacitance-Equivalent-Thickness (CET) is shown in Figure 5.12 (b). Considering
the doping of the p-Si wafer, a work function of 5.3 eV was extracted for ALD WN. This
indicates that the Fermi level of WN is ~0.25 eV deep into the valence band of the Si. This result
is consistent with the threshold voltage of fully-depleted undoped SOI p-MOSFETs described in
section 6.2.1.
Figure 5.12: (a) Schematic of the test structure used to extract the WN workfunction; (b) Plot of flatband
voltage (VFB) vs. capacitance effective thickness (CET) for WN/Al2O3/SiO2/Si stack as the thickness of
the SiO2 is varied. The value of the metal/semiconductor work function difference extracted from the
plot is 0.51 eV.
5.5 Chapter Summary
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This chapter presented the new design and process steps to fabricate and accurately
investigate the hole mobility of gate-all-around nanowire p-MOSFETs, with potentiallyenhanced electrical characteristics. The process combines a large number of sub-micron long
parallel nanowires at various dimensions with a conformal high-κ / metal gate and hightemperature hydrogen anneal technology, to acquire measurable capacitance signal and
uniformly gate the nanowires that were smoothed by the hydrogen anneal process. Tighter
contact pitch and reduced gate-to-S/D pad overlap were also implemented to reduce the external
resistance and capacitive parasitics, respectively. The hydrogen anneal process was observed to
smooth the sidewalls at 850°C and reshape or anisotropically thin the nanowires at temperatures
above 875°C, as confirmed by plan-view and cross-sectional SEM and TEM analyzes. A high-κ /
metal gate technology using O3 surface passivation, TMA Al2O3, and WN was optimized to
achieve hole universal mobility on planar FD-SOI p-MOSFETs, with moderately-low activation
temperatures, i.e. 640°C. The electrical characteristics of these devices are extensively
investigated in chapter 6.
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Chapter 6
Hole Transport in Gate-All-Around Si
Nanowire p-MOSFETs
6.1 Introduction and Process Splits
The electrical characteristics and the hole mobility of gate-all-around Si nanowire pMOSFETs with a conformal ALD high-κ/metal gate stack and hydrogen anneal process are
investigated in this chapter. Table 6.1 summarizes the process splits utilized after suspension of
the Si nanowires, representing the pre-dielectric cleaning steps and hydrogen annealing
conditions.
Condition
Suspended Nanowire Process
A
No hydrogen annealing, RCA clean, HF last, ALD
B
RCA clean, hydrogen anneal at 850°C, 100 torr for 2 min, ALD
C
Condition B + RCA, hydrogen anneal at 875°C, 100 torr for 2 min, HF dip, ALD
Table 6.1: Process splits for post-suspension nanowire treatment, indicating pre-dielectric cleaning and
hydrogen annealing conditions.
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Typical cross-sectional transmission-electron-microscopy (XTEM) and high-resolution
cross-sectional scanning-electron-microscopy (HR-XSEM) images of devices after complete
fabrication are shown in Figures 5.6 and 5.8. For all three cases, the gate dielectric consists of an
optimized ~1.0 nm in-situ O3-SiO2 and 55 Å of Al2O3, deposited by ALD, with an effective
oxide thickness, EOT, of 3.4 nm. The nanowires were also conformally wrapped with ~27-30 nm
ALD WN. Each device consists of 500 parallel nanowires, and no nanowire breakage was
observed by SEM during processing. The design tips and process details are discussed in section
5.2 and Appendix E, respectively.
6.2 Device Characteristics
6.2.1 Drain Current and Electrostatics
Transfer and output characteristics of gate-all-around nanowire p-MOSFETs (LNW = 0.6 µm,
N = 500, EOT = 3.4 nm) with the optimized hydrogen anneal condition (B) are shown in Figure
6.1 (a) and (b), respectively. The nanowire has as circular cross-section with a radius of ~7.5 nm.
Normal characteristics with no hysteresis or high-κ instability were observed. The device shows
approximately 10 order of magnitude cut-off behavior. The ideal swing of 61 mV/dec. indicates
excellent interface properties. Using equation 2.8 and assuming negligible CS/D compared to Cox,
Dit ~ 2×1011 cm-2 was extracted for the dielectric stack, comparable to thermal SiO2 grown by
high-temperature dry oxidation.
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Figure 6.1: (a) Transfer and output characteristics of gate-all-around ~15 nm-diameter nanowire (LNW =
0.6 µm, N = 500) p-MOSFETs with high-K/metal gate and hydrogen anneal process, showing ideal subthreshold slope of 61 mV/dec and very high on-to-off ratio. The EOT was extracted from C-V
measurements on planar transistors.
The variation of sub-threshold slope (SS) and threshold voltage (Vth) as a function of WNW
for gate-all-around nanowire p-MOSFET with WNW = 15-72 nm and LNW = 0.6-1.2 µm are
shown in Figure 6.2. Slopes were average over 4 to 5 orders of magnitude change in the subthreshold drain current. The threshold voltages were extracted using the “linear extrapolation”
method at VDS = -0.05 V, which have similar values at higher drain voltages due to lack of draininduced-barrier-lowering (DIBL) for these long-channel devices [126]. The SS and Vth of planar
fully-depleted SOI p-MOSFETs (on the same chip) are also shown for comparison. Subthreshold slopes have very small variation between 60.5 and 61.7 mV/dec., with very slight
nanowire width dependence indicating excellent density of interface traps. The higher subthreshold slope of the planar devices (~63 mV/dec.) may be attributed to the higher density of
interface traps at the bottom interface between Si and SiO2.
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Figure 6.2: (a) Subthreshold slope (SS) and (b) threshold voltage (Vth) as a function of WNW for gate-allaround p-MOSFETs with Al2O3/WN gate stack. All devices show ideal swing (with a minimum of 60.5
mV/dec for 15 nm circular NW), indicating very low Dit.
A large Vth roll-off with decreasing WNW is observed in Figure 6.2 (b). The flatband voltage
based upon the workfunction of WN, extracted in section 5.4.3, is also shown as a reference.
Quantum mechanical simulations did not show considerable change in the threshold behavior of
these nanowires for various nanowire widths in the range of study. Such strong Vth roll-off
behavior may be due to the sidewall facet-dependent fixed charge, which is more pronounced at
narrower nanowires due to the increased contribution of the sidewalls.
6.2.2 Performance Enhancement by Hydrogen Anneal
Figure 6.3 compares the transfer characteristics of gate-all-around nanowire p-MOSFETs
(LNW = 0.8 µm, N = 500 and 22×15.6 nm elliptical nanowire) treated with optimized hydrogen
anneal at 850°C (condition B) and without hydrogen anneal (condition A). Both devices exhibit
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excellent cut-off characteristics with SS = 61 mV/dec. A threshold voltage shift can be observed
for these nanowires, where hydrogen annealed nanowires turn on at lower gate voltages (in
absolute value). There are few reports on the earlier turn-on behavior of hydrogen annealed
FinFETs or Tri-gate MOSFETs due to reshaping induced by annealing [146-148]. However,
similar threshold shift was observed for the on-chip planar SOI p-MOSFETs investigated in this
study, and the threshold shift it believed to be due to a variation of the flatband voltage or
random variation of the metal gate workfunction.
Figure 6.3: Transfer characteristics of 22×15.6 nm gate-all-around nanowire p-MOSFETs (with N = 500
nanowires) treated with hydrogen anneal at 850°C (condition B) and without hydrogen anneal (condition
A), indicating ideal SS = 61 mV/dec and very high on-to-off ratio (~1010). No hysteresis was observed in
the transfer characteristics.
In order to directly compare the performance enhancement by hydrogen annealing, the
transfer characteristics of these nanowires (WNW = 22 nm) were plotted vs. overdrive voltage
(VGS - Vth), as shown in Figure 6.4 (a). Moreover, the output characteristics of these devices were
plotted at VGS - Vth = 0 to -2 V, with a step size of -0.25 V. An enhancement of ~1.6X is
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observed for both linear and saturation current due to the optimized hydrogen anneal process at
850°C. This relatively high performance enhancement can not be due to the possible small size
difference of nanowires. For example, a possible 2 nm difference in the width or height of
nanowires can only contribute to 5 % change in the effective width and total current of the
device. The intrinsic performance enhancement by hydrogen annealing, in terms of hole
mobility, is discussed in the following section.
Figure 6.4: Plots of (a) ID vs. gate over-drive voltage (VGS-Vth) and (b) ID vs. VDS for VGS-Vth = -2 V to 0
V step -0.25 V, for 22×15.6 nm gate-all-around nanowire p-MOSFETs with hydrogen anneal at 850°C
(condition B) and without hydrogen anneal (condition A), indicating ~1.6X enhancement for linear and
saturation current due to the hydrogen anneal process (condition B).
6.3 Hole Mobility Characterization
6.3.1 Capacitance Measurements and Mobility Extraction
Low-field effective hole mobility of these devices was extracted using a double Lm or twoFET method, as extensively described in section 2.5. MOSFETs with LNW = 0.6 and 1.2 µm and
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N = 500 nanowires were used for this purpose. Drain current was measured at VDS = -50 mV.
Figure 6.5 shows typical split C-V and ID-VGS measurements of 15 nm-diameter circular
nanowire p-MOSFETs (with LNW = 0.6 and 1.2 µm). The currents and capacitances are
normalized by the number of nanowires. The differential capacitance, ΔCinv, is indeed the
intrinsic capacitance of a nanowire with a differential length 0.6 µm (the difference between 1.2
and 0.6 µm nanowire lengths), where all the overlap and other capacitive parasitics are excluded.
Figure 6.5: Typical split-CV and ID-VGS measurements of 15 nm-diameter circular nanowire (with LNW=
0.6 and 1.2 µm) for mobility extraction using the 2-FET method. Drain current was measured at VDS = 50 mV. Current and capacitances are normalized by the number of nanowires (N = 500).
6.3.2 Charge Distribution and Capacitance Simulations
Two-dimensional quantum mechanical simulations were conducted by James T. Teherani
using the nextnano3 ™ Schrödinger-Poisson solver to simulate the charge and potential
distribution and extract the capacitance of the nanowires. To compensate for the lack of S/D
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terminals in the two-dimensional simulation approach, the flat band voltage was changed to
sweep the gate voltage. Only physical dimensions (derived from XTEM) and permittivity
(extracted from planar CV measurements) were input into the simulations. Due to the unknown
fixed charge and the large roll-off of Vth as seen in section 6.2.1, the C-V characteristics were
laterally shifted to match the experimental results.
Figure 6.6: Simulated (nextnano3) hole charge density in nanowires with (a) circular (15.6×14 nm,
dNW~15 nm) and (b) elliptical (22×15.7 nm) and cross-sections for VGS-VFB = -1.3 V. Inversion centroid is
displaced from nanowire surface by the distance δQM (VGS). Simulation courtesy of J. Teherani.
Figure 6.6 illustrates the simulated hole charge density in nanowires with circular (15.6×14
nm, dNW ~ 15nm) and elliptical (22×15.7 nm) cross-sections, at VGS - VFB = -1.3 V. It can be seen
that the inversion centroid is displaced from the nanowire/dielectric interface by the distance
δQM(VGS). In addition, simulations reveal increased peak charge density at the sidewalls (by a
factor of ~1.9) compared to the horizontal (100) surfaces (due to the radial nature of the electric
field), indicating the importance of the sidewall roughness quality.
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Figure 6.7: Measured and nextnano3 simulated inversion capacitance of 15 nm-diameter circular and 22
nm×15.6 nm elliptical nanowires, demonstrating very good agreement between measured and simulated
results, verifying the experimental mobility extraction method. Only physical dimensions (derived from
TEM), κ (extracted from planar CV measurements) and Qf were input into the simulations. The upper and
lower simulated curves correspond to simulations using a gate metal with high and low density of states,
respectively. Simulation courtesy of J. Teherani.
The measured intrinsic capacitance of ~15 nm-diameter circular and 22 nm × 15.6 nm
elliptical nanowires, normalized to the length of the nanowires, is shown in Figure 6.7. Overlaid
are the nextnano3 simulated nanowire inversion capacitances, demonstrating quite good
agreement between measured and simulated results. To model the WN metal gate, two limits
were considered. The upper simulated curves correspond to a metal with high density of states
and free electron effective mass, showing no gate depletion. The lower simulated curves
correspond to a metal with lower density of states showing small band bending and charge
depletion. The simulations with the reduced gate depletion increased Cmax by ~8% which is
within the experimental uncertainty in any case. The simulations verify the inversion charge
estimation and mobility extraction approach, by direct integration of the measured capacitances.
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Figure 6.8 shows the measured (symbols) and simulated (lines) intrinsic capacitances for
nanowires annealed at 875°C (condition C) with nanowire diameter, dNW = 8-17 nm. The
nanowire was measured by high-resolution cross-sectional SEM (see Figure 5.8) and the
diameter was input into the simulations for the dNW = 12 and 17 nm nanowires. Again, excellent
agreement is observed between the simulated capacitance and the experimental data. For sub-10
nm nanowires, under the resolution of XSEM, the effective circular diameter (dNW,eq) was
extracted by fitting simulations to the CV measurements.
Figure 6.8: Measured (symbols) and simulated (lines) intrinsic capacitances for nanowires annealed at
875°C (condition C) with nanowire diameter, dNW = 8-17 nm. dNW was measured by high-resolution crosssectional SEM and was input into the simulations for 12 and 17 nm nanowires. For sub-10 nm nanowires,
the effective circular diameter (dNW,eq) was extracted by fitting simulations to the CV measurements.
Simulation courtesy of J. Teherani.
6.3.3 Hole Mobility Investigation
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In this section, the low-field effective hole mobility of Si nanowires, with various nanowire
widths, treated without hydrogen anneal, with an optimized hydrogen anneal at 850°C, and with
hydrogen anneals at temperatures as high as 875°C which reshapes the nanowires is investigated.
6.3.3.1 Nanowires without Hydrogen Anneal
Figure 6.9 shows the effective hole mobility vs. inversion charge density (Ninv) for nanowires
with WNW = 22-72 nm, without hydrogen anneal, along with the mobility of on-chip planar SOI
p-MOSFETs. Inversion charge density was normalized by nanowire circumference. It can be
seen that all mobilities are degraded compared to the mobility of the planar SOI p-MOSFET. In
addition, similar hole mobilities are observed at high Ninv for various WNW in the range of 22-72
nm, with an average of ~20% drop compared to planar SOI device.
Figure 6.9: Effective hole mobility vs. inversion charge density (Ninv, normalized by nanowire
circumference) for nanowires with WNW = 22-72 nm, without hydrogen anneal. Similar mobilities are
observed at high Ninv for various WNW, with a ~20 % drop compared to planar (100) SOI device.
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Figure 6.10: (a) Effective hole mobility vs. Ninv (normalized by nanowire circumference) for nanowires
with WNW = 15-72 nm subjected to hydrogen anneal at 850°C (condition B). Monotonic mobility
enhancement with decreasing nanowire width is observed, due to increased contribution of high-mobility
sidewalls and reduced sidewall roughness scattering. Mobility is enhanced by 47% relative to the widest
nanowire and 33% over planar (100) SOI device at Ninv=1.1×1013cm-2. (b) Hole mobility vs. Ninv for 15
nm circular nanowires demonstrating mobility enhancement over planar SOI and the highest mobility of
nanowires without hydrogen anneal. Significant enhancement is seen relative to published data for sub-15
nm thickness nanowires.
6.3.3.2 Nanowires with Optimized Hydrogen Anneal (Condition B)
The effective hole mobility as a function of inversion charge density of Si nanowires, with
WNW = 15 to 72 nm subjected to hydrogen anneal at 850°C (condition B) is shown in Figure 6.10
(a). Hole mobility enhancement over planar (100) SOI is observed for sub 41 nm nanowire
widths, at high inversion charge densities. In addition, monotonic mobility enhancement with
decreasing nanowire width can be seen, where the mobility is enhanced by 47% relative to the
widest nanowire and 33% over the planar (100) SOI device at Ninv=1.1×1013 cm-2. In fact,
increased contribution of high-mobility sidewalls with reduced sidewall roughness scattering is
believed to be responsible for this mobility enhancement. Figure 6.10 (b) shows the hole
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mobility vs. Ninv for 15 nm circular nanowires, demonstrating mobility enhancement over planar
SOI and the highest mobility nanowires without hydrogen anneal. Significant enhancement is
seen relative to recent published data for sub-15 nm thickness nanowires [23, 24, 138].
It should be mentioned that in all previous sections, the inversion charge density was
normalized by the circumference of the nanowires, were it was assumed that the charge is
located at the nanowire/dielectric interface. However, as can be seen in figure 6.6, the hole
centroid is displaced from surface by the distance δQM, which is a function of VGS. For planar or
very wide nanowire devices, the effective perimeter of the charge is similar to the channel width
(for planar) or physical perimeter of the surface (for nanowires). However, as the nanowire size
is decreased, the effective perimeter of the nanowire diverges from the physical perimeter of the
surface. This leads to an overestimation of the perimeter and underestimation of the Ninv, mostly
at low inversion charge densities.
Figure 6.11: Hole mobility vs. Ninv, normalized by nanowire physical perimeter (dashed line) and with
quantum-mechanical (QM) correction (symbols) for circular (15.6×14 nm, dNW ~ 15 nm) and elliptical
(22×15.7 nm) nanowires. The QM correction to the perimeter was calculated using simulations at each
gate bias.
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To further elucidate the effects of quantum mechanical corrections, Figure 6.11 shows the
hole mobility vs. Ninv, normalized by the nanowire physical perimeter (dashed line) and with
quantum-mechanical (QM) correction (symbols) for circular (15.6×14 nm, dNW ~ 15 nm) and
elliptical (22×15.7 nm) nanowires. The quantum-mechanical correction to the perimeter was
calculated using simulations at each gate bias. It should be noted that the simulated δQM was
observed to follow the Ns-1/3 behavior, similar to equation (2.37) for planar devices. Figure 6.11
indicates that the correction involves an overdrive-dependent shift of the inversion charge
density towards the right-hand side (higher Ninv).
The absence of quantum mechanical
correction leads to an overestimation and underestimation of the hole mobility, at low and high
Ninv, respectively. It can also be noted that for the relatively wide elliptical nanowire, the hole
mobility is almost insensitive of the quantum-mechanical correction, as expected.
Figure 6.12: (a) Transfer characteristics of gate-all-around nanowire p-MOSFETs (with dNW ~ 8, 10, 12,
17, 22 nm and LNW = 0.6 µm subjected to non-optimized hydrogen anneal (condition C). Non-ideal
swings (>80 mV/dec) suggest that nanowires have high density of interface traps due to non-optimized
condition C.
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6.3.3.3 Nanowires with Non-Optimized Hydrogen Anneal (Condition C)
As seen earlier in Figure 5.8 of chapter 5, the widths of nanowires subjected to hydrogen
anneal at higher temperatures (condition C, at 875°C) were significantly reduced, where
rectangular narrow nanowires were reshaped to nanowires with circular cross-sections and with
diameters in the sub-10 nm regime. Figure 6.12 shows the transfer characteristics of gate-allaround nanowire p-MOSFETs (with dNW = 8, 10, 12, 17, 22 nm and LNW = 0.6 µm) subjected to
hydrogen anneal (condition C). Non ideal swings (>80 mV/dec) suggest that the nanowires have
high density of interface traps due to non-optimized condition C (recall from Table 6.1 that these
devices were first annealed at 850°C, followed wet chemical cleaning, and annealed again at
875°C, and subjected to HF dip prior to ALD).
Figure 6.13: Plots of effective hole mobility vs. inversion charge density, for nanowires with (a) WNW =
12-32 nm and (b) WNW < 12 nm subjected to non-optimized hydrogen anneal (condition C). Mobilities are
generally reduced due to high density of interface traps of condition C.
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Figure 6.13 shows the effective hole mobility as a function of inversion charge density for
these nanowires with (a) dNW = 12 - 32 nm and (b) dNW < 12 nm. It can be seen that the hole
mobilities (including the planar FD-SOI) are generally reduced due to the high density of
interface traps associated with condition C, consistent with the non-ideal sub-threshold behavior.
However, the mobilities of nanowires down to dNW,eq = 10 nm exceed the mobility of the planar
FD-SOI MOSFET, particularly at high inversion charge densities. The width dependence of the
hole mobility is investigated in the following section.
Figure 6.14: Width-dependence of hole mobility for nanowires with and without hydrogen anneal, at
Ninv= 5×1012 and 1013 cm-2. Flat mobility behavior is observed without hydrogen anneal due to a balance
between high-mobility non-(100) planes and sidewall roughness scattering. The latter mechanism is
significantly diminished with hydrogen anneal (condition B), and more than 57% enhancement is
observed for WNW < 22 nm.
6.3.4 Width Dependence of Hole Mobility
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Figure 6.14 shows the hole mobility as a function of WNW, for Si nanowires with optimized
hydrogen anneal (condition B) and without anneal, at Ninv= 5×1012 and 1013 cm-2. A nearly flat
mobility behavior is observed for nanowires with no anneal, with a significant drop at around 16
nm nanowire width. The flat trend is due to a balance between increased contribution of highmobility non-(100) planes, and increased sidewall roughness scattering, as WNW is decreased.
For the narrowest nanowire, mobility significantly drops as the transport is completely
determined by the rough sidewalls. On the other hand, the sidewall roughness scattering is
significantly diminished with hydrogen anneal (condition B) and the mobility monotonically
increases, as the nanowire width is decreased, due to increased contribution of smooth high holemobility non-(100) sidewalls. As a result, +57% enhancement is observed for WNW = 22 nm at
Ninv = 1013 cm-2.
Figure 6.15: Hole mobility of Si nanowires vs. WNW at Ninv = 1013 cm-2. Symbols correspond to the
experimental results. Lines are the empirical model with μs = 70 cm2/V.s and rμ = 1.95 (dot-dashed line),
μs = 50 cm2/V.s and rμ = 1.95 (solid line), and μs = 70 cm2/V.s and rμ = 0.9-1.42 (dot-dashed line) to fit the
experimental data.
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To further investigate the width dependence of the hole mobility, the simple analytical model
described in chapter 4 was exploited here and the results are shown in Figure 6.15. The symbols
are experimental measurements while the lines represent the model results. Using SchrödingerPoisson simulations, rn = 1.6 and 1.3 was extracted for WNW = 42 and 22 nm, respectively. The rn
ratio used for the rest of the nanowires was based on a linear interpolation. The effective width of
the surface and the sidewalls were defined at the location of the charge centroid peak. Based on
the planar mobility measurements [73], the (110) and (111) surfaces have a hole mobility
enhancement ratio of 3.2X and 1.5X (at Ninv = 1013 cm-2) compared to (100) surfaces,
respectively. Thus, a mobility enhancement factor of greater than 1 (close to 2) is expected for
non-(100) sidewalls. The dotted-dashed line and solid lines in Figure 6.15 correspond to the
model with rµ = 1.95 and µs = 70 (nominal) and 50 cm2/V.s (the best fit), respectively. While
similar trend for the model and the experiments can be observed using nominal value of the
surface mobility (µs) and rµ = 1.95, the oversimplified model with these parameters overestimates
the experimental data. Considering the simulations and model are both valid, either a constant
reduction of µs (solid line) or a variable sidewall to surface mobility ratio, rµ = 0.9-1.42 (dashed
line) is required to exactly fit the experimental results. Width dependent stress in the Si
nanowires induced by WN metal gate may be a possible explanation for this mobility
dependence.
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Figure 6.16: Hole mobility in Si nanowires subjected to hydrogen anneal at 875°C (condition C) vs.
nanowire diameter (width) for Ninv = 5×1012 and 1013 cm-2. Increased mobility is observed by reducing
dNW to 12 nm diameter (elliptical to circular shape transition), while the mobility of sub-12 nm circular
nanowires is reduced as dNW is decreased.
The variation of the hole mobility of Si nanowires subjected to hydrogen anneal at 875°C
(condition C) vs. nanowire diameter (width) is shown in Figure 6.16, for Ninv = 5×1012 and 1013
cm-2. A peak hole mobility is observed at dNW = 12 nm. The increased mobility trend by reducing
dNW to 12 nm diameter may be a result of the elliptical to circular shape transition, which
increases the contribution of smooth high hole-mobility non-(100) sidewalls. However, the
mobility of sub-12 nm circular nanowires is reduced as dNW is decreased, likely due to phononlimited confinement effects [156].
The nanowires treated with hydrogen anneal at 875°C (condition C) revealed extremely
smooth sidewalls by SEM. The general mobility reduction for condition C might be attributed to
the Hydrofluoric Acid dip (after hydrogen annealing) used for this process which significantly
increase the density of the interface traps. This is consistent with the degraded sub-threshold
slope for both nanowire and planar devices. Moreover, the mobility of the planar devices was
also significantly degraded which is unlikely to be a result of hydrogen anneal process. As a
147
result, to compare the width dependence of the mobility for various post-suspension conditions,
the mobilities were normalized by the mobility of on-chip planar SOI p-MOSFETs, extracted for
each process condition. The normalized results at Ninv = 1013 cm-2 are shown in Figure 6.17.
Interestingly, similar hole mobilities are observed for hydrogen annealed nanowires processed at
conditions B and C, in the common range of WNW. Plotting the mobilities on a log-log scale
indicates that the mobility is proportional to the nanowire diameter, for sub-12 nm nanowire
diameters. Such width dependence suggests the increase in phonon scattering associated with
confinement of the carriers to be the dominant reason for mobility degradation at sub-12 nm
diameters [63, 156].
Figure 6.17: Comparison of the normalized hole mobility (at Ninv = 1013 cm-2) vs. nanowire width, for
various post-suspension treatments. Mobilities are normalized by the mobility of on-chip planar SOI pMOSFET, extracted for each process condition. Similar normalized mobilities are observed for hydrogen
annealed nanowires processed at conditions B and C, in the common range of WNW.
6.5 Chapter Summary
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The intrinsic performance and low-field effective hole mobility of gate-all-around nanowire
p-MOSFETs with a high-κ / metal gate process, for nanowire widths in the range of 8 to 72 nm,
are extensively studied in this chapter. The impact of high-temperature (≥850°C) hydrogen
anneal process on the drain current and hole mobility of Si nanowires, for two annealing
conditions that smooth and reshape the nanowires are also investigated. Sub-micron-long
nanowire devices exhibit near ideal sub-threshold swing of 61.1 ± 0.6 mV/dec, indicating
excellent density of interface traps comparable to high-temperature thermally grown oxide. An
enhancement of ~1.6X in saturation and linear current of 22 nm-wide nanowires were measured,
at a given overdrive, as a result of the optimized hydrogen anneal process. Devices with no
anneal show a flat mobility behavior, as a function of nanowire width down to 22 nm. This is
due to a balance between reduced contribution of low-mobility (100) planes and increased
contribution of sidewalls with considerable surface roughness, which significantly drops the
mobility for ~ 15 nm wide nanowires. On the other hand, increased hole mobility with
decreasing nanowire width down to 12 nm is observed for nanowires subjected to hydrogen
anneal. However, nanowires with sub-12 nm diameters exhibit reduced mobility mostly due to
the phonon-limited confinement of the holes in the scaled nanowires. Measured and simulated
nanowire capacitance are in very good agreement, verifying the accuracy of effective mobility
extraction. In addition, a simulation-based method to extract areal inversion charge density (Ninv)
of Si nanowires is introduced. Using this method, the effective perimeter of the nanowire is
corrected for quantum-mechanical separation of the hole centroid from the surface, leading to a
larger Ninv for a given gate overdrive and non-uniform stretching of the mobility-Ninv plots
towards higher Ninv.
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150
Chapter 7
Summary and Suggestions for Future
Work
7.1 Thesis Summary
The electrical characteristics and intrinsic performance of gate-all-around nanowire
MOSFETs, fabricated using a CMOS compatible top-down approach, were investigated in this
thesis. The gate-all-around device architecture benefits from excellent gate control, cut-off
behavior and immunity to short channel effects compared to planar MOSFETs. Considering the
anisotropic effective-masses for electrons and holes as well as different valence band
mechanisms involved in hole transport at the nanowire sidewalls with various surface
orientations, degraded electron and enhanced hole transport is expected for gate-all-around
nanowire MOSFETs compared to planar fully-depleted SOI MOSFETs. However, degraded
transport is often observed for both types of carriers due to non-ideal sidewalls with rough
surfaces. To overcome this problem, two types of process-based performance boosters,
applicable on suspended Si nanowires, were developed in this thesis: a novel uniaxial strain
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engineering method for n-MOSFETs and hydrogen thermal annealing process for p-MOSFETs.
The impact of these performance boosters on the transport properties of gate-all-around nanowire
MOSFETs with various channel dimensions were studied in detail.
Uniaxial tension was incorporated into the Si nanowire channel by lateral relaxation and
suspension of biaxial SSDOI substrates, strained to Si0.7Ge0.3 virtual substrates with high stress
levels of 2.1 GPa. Detailed Raman studies on the long nanowires indicate that these nanowires
are strained, even after suspension with a tensile stress level of 2 ± 0.3 GPa, which is mainly
uniaxial along the direction of these long nanowires. Gate-all-around strained-Si nanowire nMOSFETs were fabricated with nanowire width, WNW, in the range of 8 to 50 nm and body
thickness, tNW, of 7 to 8.7 nm as confirmed by cross-sectional transmission-electron-microscopy.
The detailed electrical measurements and analysis reveal that uniaxial strain in the nanowire
results in negative Vth shift in strained-Si nanowires compared to their unstrained counterparts.
In addition, a significant enhancement of approximately 2X in long-channel current drive and
transconductance was observed for strained-Si nanowires. Low-field effective mobility of these
devices was extracted using split capacitance-voltage measurements and two-FET method to
cancel the capacitive and resistive parasitics. The mobility analysis indicates enhancement for
strained-Si nanowires over unstrained Si nanowires as well as planar SOI, specifically at high
inversion charge densities. The results also show significant enhancement over the previous
reported data on unstrained-Si nanowire n-MOSFETs, fabricated using different techniques.
However, the mobility of these nanowires was shown to decrease with down-scaling the
nanowire widths, consistent with the reported data on the Si nanowires. A simple model was
developed to investigate the contribution of the sidewalls. Comparison of the model and
experimental data for both strained and unstrained Si nanowires suggests that the mobility
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reduction is more than what expected by the contribution of the orientation-dependent sidewall
mobilities solely and was attributed to the increased contribution of the sidewalls with highsurface roughness scattering.
On the p-MOSFET front, a new design approach was used to accurately investigate the
intrinsic transport and hole mobility of Si nanowires. The new design features nanowires with
tighter contact design (compared to the previously developed process for n-MOSFETs) and
increased number of parallel nanowires (N = 500) to achieve a larger capacitance signal for the
sub-micron long nanowires, which usually offer capacitances in the order of a few tenths of
fF/µm per nanowire. Moreover, the new process combines a high-κ/metal gate process to
uniformly gate various planes involved in the transport as well as an optimized high-temperature
hydrogen anneal to reduce surface roughness scattering. Using this process, long-channel devices
with ideal subthreshold swing (61.1±0.6 mV/dec) were demonstrated. The maskless hydrogen
thermal anneal process on suspended Si nanowires was shown to significantly smooth nanowire
sidewalls and results in evolution of crystallographic {311}, {111} and {110} sidewall facets.
Furthermore, an anisotropic etching and reshaping of Si nanowires was observed after hydrogen
thermal annealing at temperatures higher than 875°C. The electrical characterization of gate-allaround nanowire p-MOSFETs reveals that approximately 1.6X enhancement can be achieved in
hole mobility and linear and saturation ID as a results of an optimized hydrogen anneal process.
Detailed low-field effective hole mobility of sub-micron-long nanowires was studied down to
sub-10 nm nanowires diameter. For this purpose, the intrinsic inversion capacitance of the
nanowires were measured by two-FET method and the results were verified by quantum
mechanical Schrödinger-Poisson’s simulations. The control Si nanowire with no hydrogen
anneal showed a flat mobility behavior with reducing nanowire width down to 22 nm and a hole
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mobility drop at ~15 nm diameter, where the transport is fully-dominated by the rough sidewalls.
On the other hand, increased effective hole mobility with decreasing nanowire width was
observed down to 12 nm for hydrogen annealed nanowires, attributed to the smooth highmobility non-(110) sidewalls. Mobility reduction was observed for sub-12 nm nanowires, mainly
due to the phonon-limited confinement effects. A simulation-based method to extract areal
inversion charge density (Ninv) of Si nanowires was also introduced. Using this method, the
effective perimeter of the nanowire can be corrected for quantum-mechanical separation of the
hole centroid from the nanowire/dielectric interface, leading to a larger Ninv for a given gate
overdrive and non-uniformly stretching the mobility-Ninv plots towards higher Ninv .
In conclusion, without strain-engineering, gate-all-around Si nanowires exhibit enhanced
hole mobility and degraded electron mobility compared to planar fully-depleted SOI MOSFETs.
This study reveals that circular nanowires can enhance the hole mobility by +33% over planar
unstrained-SOI p-MOSFETs, while degraded electron mobility was observed for the entire range
of nanowire width studied. For high-performance CMOS applications, uniaxial strain
engineering is mandatory to further improve nanowire transport behavior to be comparable to
state-of-the art stress-engineered MOSFETs. For the strained-Si nanowire n-MOSFETs studied
in this thesis, a mobility enhancement of ~0-70% was observed compared to planar ultra-thinbody planar SOI n-MOSFETs (with a body thickness of 8 nm), at high inversion charge
densities. While the results are promising, further strain engineering and sidewall improvements
are required for Si nanowires to be considered as future candidates for future HP CMOS
generations. However, possessing excellent scalability with undoped channel, Si nanowire
technology is promising candidate for low-variability, low-power CMOS applications.
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For n-MOSFETs, the naturally low-electron mobility Si nanowire sidewalls, even with
smooth surface, degrade the overall performance of the device and with very-high level of the
uniaxial tension is mandatory to compensate this degraded performance and enhance mobility
planar devices. Application of high-levels of uniaxial compression to the short channel Si
nanowire p-MOSFETs, though technologically difficult, can improve their performance to be
comparable to HP state-of-the-art transistors.
7.2 Suggestions for Future Work
In the future new materials will be required to further enhance carrier transport. One such
material is SiGe and Ge. SiGe provides enhanced hole transport, and Ge is expected to improved
both electron and hole mobilities. A list of suggested future work to possibly enhance the
transport of multi-gate nanowire SiGe transistors over Si nanowires is provided below:
•
Top-down fabrication of Ge nanowire p-MOSFETs by selective growth of high-quality
relaxed Ge on Si micro- or nano-trenches, locally opened on oxide-passivated Si substrates
and investigation of carrier transport on Germanium nanowires n- and p-MOSFETs
•
Epitaxial growth of strained-SiGe or pure-Ge on sub-10 nm Si nanowire fins, subjected to
hydrogen anneal and transport study of gate-all-around p-MOSFETs
•
Epitaxial growth of high-quality strained-Ge on ultra-thin-body SSDOI substrates to realize
uniaxial strained-Ge nanowire fins by nano-patterning and lateral relaxation
•
Investigation of hole transport in uniaxial compressively-strained Germanium nanowire pMOSFETs
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7.3 Contributions
The main contributions of this thesis are summarized as follows:
•
Realization and characterization of suspended uniaxially strained-Si nanowires [133, 157]
•
Process development for gate-all-around Si and strained-Si nanowire n-MOSFETs [158]
•
Transport enhancement and electron mobility investigation of strained-Si nanowire nMOSFETs [159, 160]
•
Realization of strain retention in vertically stacked strained-Si nanowires [137]
•
Study and optimization of maskless hydrogen anneal on suspended Si nanowires[161]
•
Development of process for gate-all-around nanowire p-FETs with high-κ/metal-gate and
high-temperature hydrogen anneal [161]
•
Detailed hole mobility study of gate-all-around nanowire p-FETs and the role of hydrogen
anneal [161]
•
Process development for asymmetrically strained (~2%) Ge heterostructure on insulator
[131, 162]
•
Selective epitaxy of SiGe and Ge on Si nanowires [125, 137]
•
Process development and mobility study of Si/Ge core-shell nanowire p-FETs [125, 137]
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Appendix A
E-beam Lithography with Hydrogen
Silsesquioxane Negative-Tone Resist
A.1 Hydrogen Silsesquioxane Negative-Tone Resist
E-beam lithography utilized in this thesis to fabricate Si nanowires was performed in a Raith
150™ system. A process was optimized for Hydrogen SilsesQuioxane (HSQ) negative-tone ebeam resist. HSQ is a spin-on dielectric with the chemical formula of (HSiO3/2)n, where n is the
number of monomers with a typical value of n = 8, forming a cage-like structure [163, 164].
Upon exposure, high energy electron beam breaks the Si-H bonds and reconfigures the cage-like
HSQ to a long-range network via a cross-linking process [165]. HSQ used in this thesis was a
flowable oxide (FOx) diluted with Methyl-IsoButyl-Ketone (MIBK), available under trade name
of XR-1541™ (from Dow-Corning®). The development mechanism of HSQ is suggested to be
via ionization by bond-decision, rather than dissolution [165]. Hydroxide (OH-) ions in the
developer such as Tetra-Methyl-Ammonium Hydroxide (TMAH) can break the Si-H bonds,
form stronger Si-O bonds and can be carried away the (CH3)4N+ ions and water molecules [166].
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Spinning of the 4% solid XR1541 was performed at a speed of 3500 rpm and a thickness of
~90 nm was measured using laser interferometer and Dektak™ profilometer. Reusable
Polypropylene (PP) pipettes, cleaned with Hydrofluoric Acid and DI water, were used to drop
the resist on the entire wafer. Table A.1 summarizes the optimized process used in this thesis for
e-beam lithography using 4% XR1541 negative tone resist.
Step #
0
Process Step
Resist Storage
1
Resist Spin
2
Prebake
3
Exposure
4
Development
5
Cleaning
Process Details
Refrigerate XR1541 4% in a plastic container (from provider)
Bring the resist to room temperature, drop by PP pipettes to
cover the entire wafer, spin at 3500 rpm for 1 min using TRLPMMA Spinner
at 90°C for 2 minutes on a hot-plate
Immediately after spin, using Raith 150™, e-beam energy: 30
keV (with SEM imaging operated at SE mode), field size: 100
μm, beam diameter: 2 nm, areal dose: 1200 µC/cm2, beam
current: ~230-280 pA
Usually within 8 hrs, in 25% TMAH for 70 sec, spin/rinse/dry
3:1 H2SO4: H2O2, optional SC2 (6:1:1 DI:H2O2:HCl), plasma
ashing for 1 min
Table A.1: Optimized process flow for e-beam lithography using HSQ negative-tone resist.
Figure A.1: Plot of relative remaining Hydrogen Silsesquioxane (HSQ) thickness vs. exposure dose for
HSQ on HOI samples exposed at 10 keV and 30 keV. Both samples were prebaked at 90°C for 4 minutes
and developed with 25 wt. % TMAH for 1 minute. While similar contrast is observed, higher dose is
required to expose HSQ at energy of 30 keV.
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The performance of any resist is usually characterized by its contrast curve. This curve
describes the remaining resist fraction of a uniformly illuminated resist vs. the logarithm of the
applied exposure dose. The contrast is a measure of how well the resist can convert the distorted
patterns of a blurred aerial image into a sharp binary stencil, and directly affects the resolution of
the entire lithography process. Figure A.1 shows the contrast curves of XR-1541 resist for
incident beam energies of 10 keV (the typically used energy for Raith 150 system) and 30 keV
(the highest available energy for Raith 150 system). The starting substrates were Ge HOI wafer
pieces, with prebake and development conditions specified in Table A.1. The relative thickness
of the resist was measured using Dektak™ profilometer on 10×10 µm2 squares, at each exposure
dose in the range of 100-2000 μC/cm2. While imaging at higher energies is typically worse than
lower energies due to the higher volume of scattering, e-beam lithography at higher energies has
certain benefits. From the basic scattering theory, the energy transferred by collision of incident
electrons, T, is inversely proportional the incident electron energy, E, given by:
(A.1)
where q is the charge of the electron and b is the distance of the closest approach between the
electrons. In fact, a decrease of electron energy causes an increase of deposited energy in a given
resist volume (larger T), which explains why the saturation dose is lower at lower incident
energies (Figure A.1). However, exposure at lower energies increases the forward scattering
effects which results in increased proximity effects. Chromatic aberration is also less using
higher acceleration voltages.
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Figure A.2: Contrast curve for 4% XR-1541 Hydrogen Silsesquioxane (HSQ) exposed at 30 keV and
developed in 0.26N TMAH and 25 wt. % TMAH at the room temperature. The contrast is significantly
enhanced using 25 wt. % TMAH.
Figure A.3: Contrast curve for 4% XR-1541 Hydrogen Silsesquioxane (HSQ) prebaked at 200°C and
90°C for 2 minutes, exposed at 30 keV and developed in 25 wt. % TMAH for 1 minute. While similar
contrast is observed, prebaking at 90°C has a wider exposure window.
As mentioned earlier, TMAH is commonly used for HSQ development. Two types of TMAH
chemistries are typically used in CMOS and semiconductor manufacturing: 0.26N TMAH,
which is commonly used to develop photoresists, and 25 wt. % TMAH, which is used to etch Si
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at elevated temperatures (around 80°C). Figure A.2 shows the contrast curve for 4% XR-1541
HSQ exposed at 30 keV and developed in 0.26N TMAH and 25 wt. % TMAH at the room
temperature. The contrast (defined as slope of the relative thickness vs. dose) is significantly
enhanced using 25 wt. % TMAH.
Resist prebake is often used to evaporate the remaining solvent in the resist. Figure A.3
shows the contrast curve for XR-1541 prebaked at 90°C and 200°C. While, similar contrast is
observed for both conditions, prebake at 90°C shows a slightly less saturation dose. For practical
purpose, as the contrast curves are very similar and to save time, a prebake at 90°C was chosen.
In addition, no change in the resolution was observed even for samples without any prebake.
Figure A.4: (a) Typical plan-view SEM image of 20 nm-wide 4% XR-1541 Hydrogen Silsesquioxane
(HSQ) line and (b) corresponding line edge profile. HSQ was developed in 25 wt % TMAH for 60
seconds. (c) Tilted SEM image of HSQ lines (various width) on Si wafer after Si etch and (d) magnified
cross-sectional SEM of 17.3 nm HSQ line (with an aspect ratio of ~5) on a Si fin.
Figure A.4 (a) and (b) illustrate a typical plan-view SEM image of a 20 nm-wide 4% XR1541 HSQ line and the corresponding line edge profile. The profile analysis shows a line width
average (Wavg) of 20.0 nm (similar to the targeted value) with a variation characterized by 3σ =
2.4 nm. The minimum line width achieved using a 90 nm HSQ is around 17 nm. Figure A.4 (c)
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shows tilted (low-angle) cross-sectional SEM image of HSQ lines with various line width on a Si
wafer after Si reactive-ion etch in Cl2/HBr plasma. HSQ shows very high etch selectivity to Si
etch and very high adhesion to Si, which makes it a good candidate to be used as the prototype of
non-planar Si MOSFETs, for technology development purposes. Figure A.4 (d) shows a highmagnification cross-sectional SEM image of a high aspect-ratio (~5) 17.3 nm-wide HSQ line on
top of a Si fin.
Figure A.5: SEM images of the e-beam alignment marks with various sizes in the range of ~0.2 µm to ~
6 µm created by photolithography and over-exposure.
A.2 Hybrid Lithography
E-beam lithography is a very low throughput process, mostly due to the slow transition of the
stage. As a result, e-beam lithography was only used to create critical dimensions (such as
nanowire or short gate lengths) and the rest was done using photolithography with a better
overlay accuracy and much higher throughput. For example, in fabrication of nanowire
transistors used in this thesis, the nanowires were patterned using e-beam lithography while the
S/D anchors were patterned by photolithography using an i-line Nikon stepper. Toward this end,
cross-like e-beam alignment marks, with cross widths as narrow as 250 nm, were fabricated by
photolithography using a separate mask at a few locations near device regions. This global mask
162
also contains the alignment marks needed for the following photolithography step to pattern
active regions. The crosses were then etched through the SOI layer and buried oxide and into the
bulk Si layer, forming a total step height of ~0.8-1 μm. This provides acceptable (though not
great) contrast when imaging using SE mode at energy of 30 keV. Figure A.5 shows a series of
SEM images of e-beam alignment marks with various sizes in the range of ~0.2 µm to ~6 µm
created by photolithography and over-exposure. Three of these alignment marks were used for
each exposure using Raith 150 system, via “three-point alignment” technique. After e-beam
lithography, developing and cleaning, the sample was coated with photoresist (~ 1 µm thick),
exposed and developed. The developer is compatible with HSQ and doesn’t impact the e-beam
lithography. Figure A.6 (a) shows an SEM image of e-beam and photo-resists on top of an SOI
wafer, patterned using hybrid lithography. A similar structure after Si reactive-ion etching and
photoresist ashing is shown in Figure A.6 (b). The HSQ was removed in the 50:1 DI water: HF
dip to release the Si nanowire.
Figure A.6: SEM image of nanowire/pad structure created using hybrid lithography process (a) before Si
reactive-ion etching and (b) after Si reactive-ion etching and photoresist ashing.
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Figure A.7: SEM images of ultra-dense 10 nm 6% XR-1541 Hydrogen Silsesquioxane (HSQ) lines in 30
nm pitch achieved by a salty developed.
A.3 Fabrication Process for Ultra-Dense Si Nanowires
As discussed earlier in section 3.3, fabrication of ultra-dense strained-Si nanowires has
potential to enhance the Raman signal-to-noise ratio for sub-20 nm nanowire widths. Ultra-dense
suspended strained-Si nanowires were fabricated utilizing resolution improved e-beam
lithography, with thin-body HSQ. For this purpose, 6% solid XR1541™ negative tone e-beam
resist was first diluted in MIBK in a 1 HSQ: 3 MIBK by volume ratio and spin-coated onto the
sample at a speed of 6000 rpm to a thickness of 35 nm. The sample was then exposed in a
Raith150™ electron-beam lithography tool at a 30 kV acceleration voltage. Nanowire structures
were exposed using single-pass lines with the linear dose of 14.0-24.3 mC/cm while the large
pads were exposed as filled-in rectangles using an areal dose of 2.2 mC/cm2. The sample was
typically exposed within 4 hours of resist spin-coating. A high-contrast salty development
process of HSQ was used to achieve dense, high-resolution structures [134]. The sample was
then developed in an aqueous mixture of 1% NaOH and 4% NaCl at 24°C for 4 minutes, then
rinsed in DI water and dried using a pressurized N2 gun. The addition of NaCl salt to aqueous
164
NaOH developer was found to increase the contrast of the resist, which enabled the fabrication of
high-resolution nanostructures with minimal loss in resist thickness [134]. The subsequent
process steps were similar to the steps discussed earlier in this appendix. Figure A.7 illustrates
sample high-resolution SEM images of ultra-dense (33 nanowire per micron) 10 nm resist lines
in 30 nm pitch.
165
166
Appendix B
Raman Spectroscopy of Strained-Si
Nanowires
B.1 Raman Characterization of Suspended Nanowires
This section provides with the Raman data used to characterize the stress in suspended
strained-Si nanowires, introduced in section 3.3. The UV Raman spectrometer was operated in
additive mode using 325 nm He-Cd laser line, with a power density was ~300 kW/cm2 and the
beam diameter was ~0.4 μm. The Raman spectra of the Si-Si LO phonon mode of suspended
strained-Si nanowires with pads attached to the buried oxide with widths of 40, 25, and 20 nm
are shown in Figure B.1 (a)-(c), respectively. The nanowires were ~20 nm thick and 2 μm long.
The laser was scanned from pad to pad in a direction parallel to the nanowire length.
All strain calculations are based on a manual software fit to the spectral data using one or two
Lorentzian functions depending on the overall signal line shape and position of the laser beam,
after canceling the linear background signal (for example of such a fit, see Fig. 9). Stress errors
were calculated based on various sources such as unstrained Si reference frequency, SSOI
167
frequency, phonon deformation potentials, and elastic constants. These measurements were
performed at the limit of both the spatial and spectral resolution of convention UV micro-Raman
and the data and analysis should be viewed within that context. Additionally, micro-Raman
configurations are not conducive to observing the TO phonon band and thus a planar stress
model with biaxial strain is generally assumed. Therefore, to calculate stress in nanowire and
pad regions from the observed peak shifts, isotropic biaxial relaxation was assumed.
Figure B.1: Raman spectra of the Si-Si LO phonon mode as the laser is scanned from pad to pad in a
direction parallel to the nanowire length for (a) 40 nm, (b) 25 nm and (c) 20 nm-wide nanowires. The
nanowires are ~25 nm thick and 2 μm long.
The total in-plane stress, σxx + σyy, for the structures with nanowire widths of 40 to 20 nm are
shown in Figure B.2 (a)-(d). The location of the spectra corresponding to the signal from the
nanowires is indicated in each plot. It should be noted that the y-axis in Figure B.2 corresponds
to the sum of the stress in two perpendicular in-plane directions, and micro-Raman
measurements are not able to resolve the individual in-plane stress components. After
suspension, since the wires are free standing, elastic in-plane relaxation in the direction
168
perpendicular to the nanowires is highly likely, and we can assume that the strain is mainly
uniaxial with only a longitudinal component remaining.
Figure B.2: Total in-plane stress extracted from the data assuming biaxial isotropic strain for each
spectrum along the Raman line scan for nanowires with widths of (a) 40, (b) 30, (c) 25, and (d) 20 nm.
B.2 Raman Characterization of Ultra-Dense StrainedSi Nanowires
UV micro Raman spectroscopy with a 325 nm He-Cd laser line was used to measure the
stress in ultra-dense suspended nanowires. The Raman spectrometer was operated at a high
power density of 280 kW/cm2 to enhance the relatively weak SNR from the nanowires. Fig. 9
shows the spectra of the Si LO phonon for nanowires measured at power densities of 122 and
169
280 kW/cm2. The total in-plane stress measured at higher power density is around 0.18 GPa
more than the stress measured at lower power density. This artificial shift in the phonon
frequency is due to laser heating, which hydrostatically expands the lattice and redshifts the
phonon frequency [161].
Figure B.3: (a) Low (b) and high laser power spectra of the Si LO phonons from the nanowires and
substrate. Thermal expansion contributes to an apparent ~0.18 GPa total in-plane stress shift in the high
power case.
Figure B.4: (a) Raman spectra of the Si-Si LO phonon mode and (b) total in-plane stress as the laser is
scanned from pad to pad in a direction parallel to the nanowire length, for ultra-dense 18 nm-wide
nanowires. The nanowire pitch size was reduced to 40 nm to improve the Raman signal-to-noise ratio.
Raman spectra of the Si-Si LO phonon mode and total in-plane stress for ultra dense 18 nmwide nanowires at 40 nm pitch are shown in Figure B.4 (a) and (b), respectively. The Raman
170
spectra associated with the pads and 1 μm long nanowires are indicated. The nanowires are
strained to total in-plane stress of 1.7 GPa.
171
172
Appendix C
Fabrication Flow and Stress
Characterization of Vertically-Stacked
Strained-Si Nanowires
C.1 Starting Substrates
The schematic of the starting substrates used to fabricate vertically-stacked strained-Si
nanowires is shown in Figure C.1 (a) and (b). Starting 150 mm p-type Si wafers were RCA
cleaned, followed by deposition of 250 nm epitaxial Si, 3 µm graded Si1-xGex (x = 0 - 0.30), and
500 nm relaxed Si0.7Ge0.3 layers. Then a superlattice with N periods of strained-Si / relaxed
Si0.7Ge0.3 layers were in-situ grown. All layers were grown in an Applied Material Epi Centura™
chemical-vapor-deposition reactor.
Micro–Raman spectroscopy was used to measure the amount of strain in the as-grown
substrates as well as the nanowires. The micro-Raman measurements were performed in a
backscatter configuration (no sample tilt) with an Olympus™ 0.8 NA objective, allowing for
sub-micron spatial resolution.
The signal was energy dispersed with an Acton SP-275
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spectrometer and collected with an Andor iDus™ CCD camera. The system resolution was 3.6
cm-1 when using the 458 nm argon laser line with an average power of 1 mW for excitation. The
XY-movement of the excitation on the device structure was controlled with a Burleigh
Inchworm™ stage capable of 50 nm step size.
Figure C.1: Schematic of starting as-grown epitaxial substrates with (a) single and (b) N = 5 period
superlattice of strained-Si/Si0.7Ge0.3; (c) Raman spectra of the Si LO phonon from the as grown substrate
with N = 5 periods using 4 different excitation wavelengths which vary the penetration depth into the
layers. No change in Raman peak position was observed using different laser lines with different
penetration depths, indicating similar stress in all layers; (d) Raman spectra of starting substrates with
N=1 to 5 periods using 458 nm laser and (e) relative Raman shift from a Si reference corresponding to
strained-Si and relaxed SiGe peaks. For all samples (up to 5 periods), the starting substrates show fully
strained Si. The bulk Si signal is successfully eliminated for an excitation wavelength of 458 nm via the
intervening thick relaxed SiGe layer.
174
Figure C.1 (c) shows the Raman spectra of the starting substrate with N = 5 periods using 4
different excitation wavelengths which vary the penetration depth into the layers. According to
experiments conducted by Holtz et al. [168], the 458 nm line samples the first two layers (60
nm), the 488 nm line approximates the first 4 layers (200 nm), the 532 nm line approximates all
5 layers plus the relaxed SiGe buffer (500 nm), and the 647 nm line penetrates into the graded
SiGe and shows a low Ge allowable Si peak at 520.5 cm-1. This is slightly lower than the
Reference Si measured signal. The strained-Si peak position is about 512.2 cm-1 for all but the
647 nm case which has a peak at 511.8 cm-1. The Si-Si mode of the SiGe peak is nearly 501.6
cm-1 for all spectra except 647 nm case which has a peak at 501.3 cm-1. Hence, the 458 nm laser
line was utilized in the subsequent measurements to collect signal from the top layers.
Raman spectra of the Si LO phonon from starting substrates with N = 1 to 5 periods and their
relative Raman shifts from a Si reference are shown in Figure C.1 (d) and (e). Two peaks are
discernible in all spectra: the right one corresponds to biaxially-strained-Si and the left one
corresponds to relaxed Si0.7Ge0.3. As can be seen from the spectra, compared to experiments
performed on the strained-Si directly on insulator substrates (section 3.3.1), the use of a thick,
relaxed SiGe substrate in the present structures blocks the signal from the bulk Si substrate,
reducing interference between the bulk and strained-Si peaks. As a result, enhanced signal to
noise ratio is expected when scanning the strained-Si nanowires. Figure C.1 also indicates that
the Si is fully strained even after 5 periods, with an average biaxial tensile strain 1.17% (2.1
GPa).
175
C.2 Fabrication Steps
Table C.1 provides with process details to fabricate vertically-stacked strained-Si nanowires.
Step #
Process Step
1
RCA Clean
2
Epitaxy
3
E-beam
Lithography
4
Pattern Transfer
5
Resist Strip
Selective SiGe
Removal
Imaging
6
7
Process Details
p-Si wafer or 30% SSDOI cleaned using standard RCA
recipe, followed by HF dip and SRD at the end
For Si: Epitaxial growth of 250 nm Si, 3 µm graded
Si1-xGex (x = 0 - 0.30), 500 nm relaxed Si0.7Ge0.3,
followed by N periods of strained-Si/ relaxed
Si0.7Ge0.3, for SSDOI: N-1 periods of relaxed Si0.7Ge0.3/
strained-Si
Similar to Table A.1, various widths in 100-nm pitch
Time controlled Cl/HBr RIE (~75 sec, Si etch rate: 4
nm/sec, SiGe etch rate: 5.2 nm), recipe: PouyaSiEtch1
in 50:1 DI:HF, for 1 min
in 3:2:1 CH3COOH:H2O2:HF bath for 1 minute, the
bath was stabilized for 4 hours before process
SEM imaging
Machine Name
RCA/ICL
Epi Centura/ICL
PMMA
Spinner/TRL,
SEBL/RLE,
Acidhood2/TRL
AME5000/ICL
Acidhood2/TRL
Acidhood2/TRL
SEMZeiss/ICL
Table C.1: Process flow utilized to realize vertically stacked strained-Si nanowires.
176
Appendix D
Process Flow for Gate-All-Around Si
(Strained-Si) Nanowire n-MOSFETs
D.1 Fabrication Flow
Table D.1 shows the process flow used to fabricate gate-all-around nanowire n-MOSFETs with
LTO/Poly-Si gate stack at MIT Microsystems Technology Laboratories and MIT Research
Laboratories of Electronics.
Step #
1
Process Step
Substrate
Preparation
(30% SSDOI and
Control SOI)
2
Elipsometry
3
PR Coating
4
Photolithography
5
PR Developing
Process Details
Machine Name
Control SOI: sacrificial wet oxidation at 800
°C (recipe: 3W800) and removal in buffered
oxide etch
Both substrates: Si thinning by multiple steps
of SC1 (1 min), HF (10 sec) to tSi = 24 nm.
Measurements of Si thickness, go to step #1
until desired thickness is achieved
Recipe: T1HMDS
E-beam alignment-mark (EAM) layer, reticle:
Pouya 1, recipe: POUYA-EAM Focus: 0,
exposure time: 180 msec
Recipe: DEV6
RCA/ICL, 5CFieldOx/ICL, oxEtchBOE/ICL
177
Acidhood2/TRL
UV1280/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
6
E-beam Alignment
Mark (EAM) Etch
7
PR Ashing
8
Resist Spin
9
Prebake
10
E-beam Exposure
11
Development
12
13
14
Post SEBL Clean
PR Ashing
PR Coating
15
Photolithography
16
PR Developing
17
Metrology
18
NW Etch
19
20
PR Ashing
Elipsometry
NW Release / HSQ
Strip
21
22
Elipsometry
23
Clean
24
LTO Deposition
25
Poly-Si Deposition
26
27
Elipsometry
PR Coating
28
Photolithography
29
PR Developing
30
Metrology
Recipes: CAIT OX BT: as original, 5000STI:
25 sec, BASELINE OX NEW: 110 sec,
5000STI: 30 sec, deep into Si
2 min
Bringing resist to the room temperature, drop
by PP pipettes all over the wafer, spin at 3500
rpm for 1min
at 90°C, for 2 minutes
Immediately after spin, using Raith 150™, ebeam energy: 30 keV (with SEM imaging
operated at SE mode), field size: 100 μm, beam
diameter: 2 nm, areal dose: 1200 µC/cm2,
beam current: ~230-280 pA
within 8 hrs (often immediately), in 25%
TMAH for 70 sec, spin/rinse/dry
3:1 H2SO4: H2O2 for 5 min
2 min
Recipe: T1HMDS
Mesa layer, reticle: Pouya 1, recipe: POUYASTI Focus: 0, exposure time: 145 msec
Recipe: DEV6
Check if the photo to e-beam alignment is
acceptable, if not go to step 13
Mesa and NW/pad RIE, Recipes: POUYA OX
BT:15 sec resist descum, 2 sec native oxide
breakthrough) + POUYA NW ETCH: 20 sec
main, 5 sec soft, 15 sec overetch (OE)
2 minutes ashing
Measure Si and BOX thicknesses
Time controlled wet etch in 50:1 DI-H2O:HF
Measure BOX thicknesses, go to step 21 until
the desired undercut is achieved (~50-70 nm
tBOX reduction)
Standard RCA clean
Recipe: LTO-Gate1, 9 min (total run: 2 hr and
41 min), 2 controls (tox = 13.3 nm)
N+ doped-poly-Si deposition, Recipe:
560DOPED-PH3Flat, 1hr and 18 min (78min),
(total run time: 4 hr and 22 min)
tpoly=79 nm
Recipe: T1HMDS
Gate layer, reticle: Pouya 1, recipe: POUYAFG Reticle shift: 11000.28,11000.10, Focus:
0, exposure time: 135 msec
Recipe: DEV6
Check if the alignment is acceptable, if not ash
PR and then go to step 27 until desired
alignment is achieved
178
AME5000/ICL
Asher-ICL/ICL
PMMA spinner/TRL
Hot-plate/TRL
Raith150/SEBL
Acidhood2/TRL
Acidhood2/TRL
Asher-ICL/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
SEM/ICL
AME5000/ICL
Asher-ICL/ICL
UV1280/ICL
Acidhood2/TRL
UV1280/ICL
RCA/ICL
6C-LTO/ICL
6A-nPoly/ICL
UV1280/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
SEM/ICL,
Asher-ICL/ICL
31
Gate Etch
32
33
34
36
Elipsometry
PR Strip
Clean
Screen Oxide
Deposition
Elipsometry
37
Ion Implantation
38
39
Post Implant Clean
PR Coating
40
Photolithography
41
42
43
PR Developing
PR Ashing
Pre-RCA Clean
44
Clean
45
ILD Deposition
46
47
49
Elipsometry
PR Coating
Backside Oxide
Etch
Clean
50
S/D/G Activation
35
48
Poly-Si gate etching, recipe: CAIT OX BT (
DESCUM: 10 sec, BT: 8 sec), CAIT SOFT
POLY ETCH, OE = 20 sec
tSi = 15 nm on the large pads, tox = 13.8 nm
Double Piranha clean, no HF
Modified RCA clean: Piranha, HF, SC2
UV1280/ICL
Premetal-Piranha/ICL
RCA/ICL
Recipe: LTO-Gate1, 7 min
6C-LTO/ICL
Total tox=15 nm
Phosphorous, no tilt, dose: 2.5×1015 cm-2,
energy: 14keV
Double Piranha clean
Recipe: T1HMDS
Stringer etch layer, reticle: Pouya 3, recipe:
POUYA-SS1, Focus: 0, exposure time: 160
msec
Recipe: DEV6
2 minutes ashing
Piranha clean
Modified RCA clean: piranha (10 min), HF (5
sec), SC2 (12 min)
Inter-Layer-Dielectric (ILD) deposition,
Recipe: LTO Gate1, 2 hr:20 min (total run
time: 5 hr:41 min) + 5 control wafers
tox = 135-140 nm
Recipe: T1HMDS
UV1280/ICL
Innovion Corp.
Premetal-Piranha/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
Asher-ICL/ICL
Premetal-Piranha/ICL
RCA/ICL
6C-LTO/ICL
UV1280/ICL
coater6/ICL
40 sec in BOE (etch rate: 5.55 nm/sec)
oxEtch-BOE/ICL
Double Piranha clean
Recipe 625a800: (2 min at 625°C, 10 sec at
800°C)
Premetal-Piranha/ICL
500°C, 30 min in forming gas (H2/N2)
A3-Sinter/TRL
coater6/ICL
52
Forming-Gas
Anneal
PR Coating
53
Photolithography
54
PR Developing
Recipe: T1HMDS
Contact via layer, reticle: Pouya 1, recipe:
POUYA-FV, Focus: 0, exposure time: 150
msec
Recipe: DEV6
55
Oxide RIE
Oxide etch until ~10-15 nm oxide remains
56
57
Elipsometry
Oxide Wet Etch
58
Elipsometry
59
60
PR Ashing
Pre-metal Clean
62
Metal Deposition
tox = 13 nm
50:1 DI: HF
tox < 1 nm was measured (below measurement
accuracy limit of the system)
2 minutes ashing
Double Piranha clean + 10 sec 50:1 DI:HF
1.5 kÅ Ti/ 1 µm Al, on two dummies as well,
total process time: 1 hr:10 min for 6 wafers
51
AME5000/ICL
179
RTP-Si/ICL
i-stepper/ICL
coater6/ICL
Centura/ICL or
AME5000/ICL
UV1280/ICL
Acidhood2/TRL
UV1280/ICL
Asher-ICL/ICL
Premetal-Piranha/ICL
Endure/ICL
63
PR Coating
64
Photolithography
65
PR Developing
66
Metal RIE
67
PR Ashing
Forming-Gas
Anneal
Measurements and
Imaging
68
69
Recipe: T1HMDS
Metal layer, reticle: Pouya 2, recipe: POUYAFM, Focus: 0, exposure time: 140 msec
Recipe: DEV6
Metal Etch, recipe: Pouya-metaletch-AlTi:100
sec + 10 sec overetch
3.5 minutes ashing
coater6/ICL
Asher-ICL/ICL
At 450°C, for 30 min in forming gas (H2/N2)
A3-Sinter/TRL
SEM imaging after electrical measurements
SEM/ICL
i-stepper/ICL
coater6/ICL
Rainbow/ICL
Table D.1: process flow to fabricate gate-all-around nanowire n-MOSFETs.
Figure D.1: (a) SEM image of the gate photoresist on the S/D anchors after successive alignment
corrections, demonstrating excellent alignment (< 30 nm accuracy). (b) SEM image of the photoresist
masking layer to etch poly-Si stringers from the S/D anchor edges. Note this is a test structure with no
poly-Si gate (not a real device) to demonstrate the position of the stringer-etch mask.
D.2 Gate-Alignment and Stringer Etch
As the gate overlay on the nanowires is required through a non-self-aligned photolithography
step, it is important to fabricate a symmetric device with minimal misalignment. Towards this
end, the gate layer was exposed using a Nikon stepper and devices located on the neighboring
die from the nanowire devices were imaged by SEM. Any misalignments were then calculated
180
and stored and the photoresist was stripped and respun. The stored misalignments were input to
the Nikon stepper, the reticle was shifted accordingly, and the wafers were re-exposed. This
sequence is repeated, usually two or three times, until the desired accuracy (less than 30 nm) is
achieved. Figure D.1 (a) shows an SEM micrograph of the gate photoresist mask aligned to the
S/D anchor test structure.
To etch the poly-Si gate stringers formed on the S/D edges due to simultaneous undercut of
the nanowires as well as S/D edges, a mask was designed to trim the S/D anchors and remove the
stringers. Figure D.1 (b) shows the position of the masking photoresist on the S/D anchors. It
should be noted that the gate line is protected using this mask.
181
182
Appendix E
Process Flow for Gate-All-Around Si
Nanowire p-MOSFETs with High-κ /
Metal Gate Process
E.1 Fabrication Flow
Table E.1 shows the process flow used to fabricate gate-all-around nanowire p-MOSFETs
with High-K/metal gate stack and hydrogen anneal process at MIT Microsystems Technology
Laboratories and MIT Research Laboratories of Electronics.
Step #
Process Step
Process Details
Machine Name
1
2
Clean
Oxidation
RCA/ICL
5C-FiledOx/ICL
3
Oxide Removal
4
Elipsometry
5
PR Coating
6
Photolithography
7
PR Developing
SOI wafers with tSi = 100 nm, tBOX = 200 nm
Wet oxidation at 800°C, Recipe: 3W800
Oxide etch in BOE, until the wafer surface
dewets
Measurements of Si thickness, repeat steps 1
to 4 until 20 nm Si remains
Recipe: T1HMDS
E-beam alignment-mark (EAM) layer,
reticle: POUYA NWSC-1, recipe: POUYAEAM Focus: 0.5, exposure time: 145 msec
Recipe: PUDDLE2
183
oxEtch-BOE/ICL
UV1280/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
8
Etch EAM
9
PR Ashing
10
Resist Spin
11
Prebake
12
E-beam Exposure
13
Development
14
15
16
Post SEBL Clean
PR Ashing
PR Coating
17
Photolithography
18
PR Developing
19
Metrology
20
NW Etch
21
PR Ashing
22
Elipsometry
23
PR Coating
24
Photolithography
25
26
PR Developing
NW Local Release
27
Elipsometry
28
29
30
PR Ashing
Pre-RCA Clean
Pre-Epi RCA
31
Hydrogen Anneal
32
ALD
Recipes: POUYA SI ETCH1 15 sec,
BASELINE OX NEW: 70 sec, POUYA SI
ETCH1:70 sec deep into Si
2 min
Bringing resist to the room temperature, drop
by PP pipettes all over the wafer, spin at
3500 rpm for 1 min
at 90°C for 2 minutes
Immediately after spin, using Raith 150™, ebeam energy: 30 keV (with SEM imaging
operated at SE mode), field size: 100 μm,
beam diameter: 2 nm, areal dose: 1200
µC/cm2, beam current: ~230-280 pA
within 8 hrs (often immediately), in 25%
TMAH for 70 sec, spin/rinse/dry
3:1 H2SO4: H2O2 for 5 min
2 min
Recipe: T1HMDS
Mesa layer, reticle: POUYA NWSC 1,
recipe: NWSC-STINEW, reticle shift:
(11000, 0.5) Focus: 0.5, exposure time: 145
msec
Recipe: PUDDLE2
Check if the photo to e-beam alignment is
acceptable, if not go to step 15
Mesa and NW/pad RIE, Recipes: POUYA
OX BT:5 sec resist descum, 3 sec native
oxide breakthrough) + POUYA NW ETCH:
9 sec main, 9 sec soft, 10 sec overetch (OE)
2 minutes ashing
Measure Si and BOX thicknesses, to verify
Si is completely etched
Recipe: T1HMDS
NW local release layer, reticle: NWSC4,
recipe: NWSC4-LR, reticle shift: 11000, 0.5,
Focus: 0.5, exposure time: 145 msec
Recipe: PUDDLE2
45+6 sec etch in BOE (etch rate: 1.5 nm/sec)
Measure SiO2 (BOX) thickness, repeat 26
and 27 until ~75 nm SiO2 is etched
2 minutes ashing
Piranha + 20 sec 50:1 DI:HF
SC1: 2 min, HF: 5 s, SC2: 2 min, HF: 15 s
for 2 min in pure hydrogen at 100 torr and
temperatures of 850°C-875°C
Immediate transfer, wafer temp.: 250°C,
manifold temp.: 150°C, 7 cycles O3, 55
cycles Al2O3, bring manifold temp. to 115°C,
1200-1400 cycles WN at 340°C
184
AME5000/ICL
Asher-ICL/ICL
PMMA spinner/TRL
Hot-plate/TRL
Raith150/SEBL
Acidhood2/TRL
Acidhood2/TRL
Asher-ICL/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
SEM/ICL
AME5000/ICL
Asher-ICL/ICL
UV1280/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
oxEtch-BOE/ICL
UV1280/ICL
Asher-ICL/ICL
Premetal-Piranha/ICL
RCA/ICL
Epi-Centura/ICL
ALD/ICL
33
PR Coating
34
Photolithography
35
PR Developing
36
Metrology
37
Gate Etch
38
Elipsometry
39
Ion Implantation
40
PR Ashing
Post-Implant/Pre-ILD
Clean
41
Recipe: T1HMDS
Gate layer, reticle: TFET-2, recipe: NWSCFGNEW, Focus: 0.8, exposure time: 140
msec
Recipe: PUDDLE2
Check if the alignment is acceptable, if not
ash PR and then go to step 33 until desired
alignment is achieved
Recipe: WN-ETCH2: 42 sec main etch, very
high selectivity to Al2O3 and HfO2
to verify WN is fully etched
Boron implant, no tilt, dose: 2×1015 cm-2,
energy: 5 keV
3:30 minutes ashing
Asher-ICL/ICL
in Nanostrip for 1.5 min
Acidhood2/TRL
42
ILD Deposition
43
44
45
46
Elipsometry
PR Coating
Backside Oxide Etch
PR Ashing
47
S/D Activation
48
49
Forming-Gas Anneal
PR Coating
50
Photolithography
51
PR Developing
Inter-Layer-Dielectric (ILD) deposition,
Recipe: LTO SPK 400 53A, 32 min
tox = 180-190 nm
Recipe: T1HMDS
For 1.5 min in BOE
2 min
at 635-645°C for 15 min then cool down to
580°C (takes about 10 minutes) and then
take the sample out of the tube
480-500°C, 30 min in forming gas (H2/N2)
Recipe: T1HMDS
Contact via layer, reticle: POUYA NWSC-4,
recipe: NWSC4-FVNEW, Focus: 1.2,
exposure time: 140 msec
Recipe: PUDDLE2
52
Oxide RIE
Time-controlled partial oxide etch
53
54
55
56
tox = 20 nm, tAl2O3 = 6 nm
40 sec in 50:1 DI: HF
tox < 1 nm, Al2O3 was fully etched
2 minutes ashing
58
Elipsometry
Oxide Wet Etch
Elipsometry
PR Ashing
Native-Oxide
Removal
Rinse/Dry
59
Metal Deposition
60
PR Coating
61
Photolithography
62
63
PR Developing
Metal RIE
57
coater6/ICL
i-stepper/ICL
coater6/ICL
SEM/ICL
Rainbow/ICL
UV1280/ICL
Innovion Corp.
6C-LTO/ICL
UV1280/ICL
coater6/ICL
oxEtch-BOE/ICL
Asher-ICL/ICL
A3-Sinter/TRL
A3-Sinter/TRL
coater6/ICL
i-stepper/ICL
coater6/ICL
Centura/ICL or
AME5000/ICL
UV1280/ICL
Acidhood2/TRL
UV1280/ICL
Asher-ICL/ICL
40 sec in 50:1 DI: HF
Acidhood2/TRL
Rinse and dry
1.5 kÅ Ti/ 1 µm Al deposition + two
dummies
Recipe: T1HMDS
Metal layer, reticle: POUYA NWSC-2,
recipe: NWSC-FM, Focus: 1.3, exposure
time: 170 msec
Recipe: PUDDLE2
Metal Etch, recipe: Pouya-metaletch-
SRD/TRL
185
Endure/ICL
coater6/ICL
i-stepper/ICL
coater6/ICL
Rainbow/ICL
64
65
66
67
Elipsometry
PR Ashing
Forming-Gas Anneal
Wafer Cleave
AlTi:115 sec + 5 sec overetch
to verify metal is fully etched
3:30 minutes ashing
450°C, 20 min in forming gas (H2/N2)
Die sawing
68
XSEM
Cross-sectional FIB cut and imaging
UV1280/ICL
Asher-ICL/ICL
A3-Sinter/TRL
Diesaw/ICL
Helios 600
FIB/DMSE
Table E.1: process flow to fabricate gate-all-around nanowire p-MOSFETs.
E.2 Polycrystalline-Si/WN Gate Stack
It is worth mentioning that deposition of WN by ALD is a very slow process. It takes around
two hours to reach the deposition temperature set point, i.e. 340°C and the deposition rate is 2.7
cycles per minute. Each cycle corresponds to 0.3-0.4 Å of WN. For example, ~56 nm WN can be
deposited at 1400 ALD cycles for total run time of about 10 hours. A resistivity of ~1.2 kΩ/□
was measured for 1400 cycles of ALD WN. An alternate way to save ALD deposition time is to
deposit a thin layer of WN, i.e. 10 nm (with Rs = 6-7 kΩ/□), followed by deposition of in-situ
doped poly-Si at 560°C. This is challenging since relatively high temperatures are required to
activate poly-Si. To study the activation of poly-Si, 75 nm of in-situ N+ doped (phosphorous)
amorphous-Si was deposited on top of a thermally-grown oxide (tox = 4 nm) at 560°C. The wafer
was broken into four pieces and the amorphous-Si was annealed at temperatures of 600°C,
650°C, 675°C and 700°C for 15 minutes in a N2 ambient. Figure E.1 (a) shows the optical
photograph of poly-Si/oxide wafer pieces, demonstrating color change from green to magenta as
the temperature is increased from 600°C to 700°C. The plot of sheet resistance as a function
activation temperature, for in-situ N+ doped poly-Si deposited at 560°C is shown in Figure E.1
186
(b). It can be seen that amorphous-Si converts to poly-Si at temperatures between 650°C and
675°C. Therefore, for a gate stack of poly-Si (75 nm) / WN (10 nm), the corresponding sheet
resistance is about 1.3 and 0.58 kΩ/□, if poly-Si is activated at 650°C and 675°C, respectively.
Figure E.1: (a) Optical photograph of in-situ N+ doped poly-Si wafer pieces deposited at 560°C and
annealed at temperatures between 600°C and 700°C, demonstrating color change from green to magenta
as the temperature is increased; (b) Plot of sheet resistance as a function annealing temperature, for in-situ
N+ doped poly-Si deposited at 560°C.
187
188
Appendix F
Si/Ge Core-Shell Nanowire p-MOSFETs
F.1 Fabrication of Si/Ge Core-Shell Nanowire pMOSFETs
As discussed in section 2.4.3, growth of Ge on Si nanowires is of great interest to improve
the transport in nanowire p-MOSFETs. The preliminary results for fabrication of Si/Ge CoreShell Nanowire p-MOSFETs are presented in this section. Starting material was 150 mm SOI
wafers with 35 nm Si and 400 nm buried oxide. Using hybrid lithography and reactive-ionetching, 4 μm long, <110>-oriented Si fins were defined with the final widths in the range of 20
to 70 nm. Each device was designed to have 500 parallel wires (N = 500) to obtain measurable
inversion capacitance, as schematically shown in Figure F.1 (a). The wafer was then cleaned
with a standard pre-epitaxial cleaning recipe with an HF-last step and the SOI thickness was
reduced to 27 nm after wet chemical cleaning. Following a prebake step at 800°C for 3 minutes
in H2 ambient, epitaxial Ge was selectively grown at a temperature of 365°C for 25 sec in an
Applied Materials Epi Centura™ reactor. After 5 minute exposure to ozone, an 8 nm Al2O3/ 35
189
nm WN gate stack was deposited on the wafers using an ALD system. The gate was then
patterned and source/drain regions were boron implanted to a dose of 5×1014 cm-2 and energy of
5 keV. LTO was then deposited as the interlayer dielectric, and S/D regions were activated at a
low temperature of 550°C for 30 minutes to minimize Ge/Si inter-diffusion. The device
fabrication was completed by Ti/Al metallization and a sinter process in forming gas ambient at
425°C for 20 minutes.
Figure F.1: (a) Top-view schematic of Si/Ge nanowire PMOS device with N parallel nanowires and a
cutline indicating where the TEM cross-section was obtained; (b) cross-section TEM image of Sicore/Ge-shell NW with Al2O3/WN gate stack.
A cross-sectional Transmission-Electron-Microscopy (TEM) image of the fabricated Sicore/Ge-shell multi-nanowire p-MOSFET device with Al2O3/WN gate stack is shown in Figure
F.1 (b). The core-Si nanowire is 20 nm wide and 27 nm tall. The thickness of epitaxial Ge on the
(001) Si surface is 10 nm. Epitaxial Ge facets along {111} crystallographic planes are inclined
by 54.7° to the top (001) Ge facet. This hexagonal faceting phenomena is believed to minimize
the surface energy [169] and has been recently reported for SiGe nanowires created by Ge
condensation technique [170] or hydrogen annealed SiGe nanowires fabricated by selective
removal of Si in SiGe/Si superlattices [171]. In Figure F.1 (b), dislocations and defects, mostly
190
propagating from the core-Si corners, are visible from this image, as the Ge exceeds the critical
thickness. Such defects have recently been reported by Smith et al. on the growth of low
germanium content SiGe layers on Si fins with sharp corners [172]. Further optimization of the
shape of the core Si nanowire and the Ge growth conditions is required to reduce the formation
of these defects.
Figure F.2: (a) Transfer characteristics of Si-core/Ge-shell nanowire p-MOSFET for various core Si
nanowire widths in the range of 20–50 nm; (b) Output characteristics of Si-core/Ge-shell nanowire pMOSFET with WSi-NW = 20 nm; (c) Measured inversion capacitance of each wire normalized per wire
length as a function of WSi-NW.
F.2 Electrical Characterization and Mobility
Calculation
Figure F.2 (a) and (b) show the measured transfer and output characteristics of Si-core/Geshell wrap-gate nanowire p-MOSFETs, for various core-Si nanowire widths (WSi-NW, as defined
in the inset) in the range of 20 to 50 nm. The widths were measured by plan-view SEM prior to
Ge epitaxy and the offset (defined as the Si loss due to the pre-epitaxy cleaning and pre-bake)
191
was calibrated by the cross-section TEM. While the nanowires exhibit poor subthreshold slope
due to the Ge/high-K interface as well as crystalline defects in the Ge epitaxial layer, it is
interesting to see that the drain current saturates as WSi-NW is decreased. In order to confirm if the
nanowire size scales as expected from the nano-lithography, the inversion capacitance was
measured using the split Capacitance-Voltage (CV) method with subtraction of parasitics. Figure
F.2 (c) shows the inversion capacitance of the Si-core/Ge-shell nanowire MOSFETs per wire,
normalized by the length of the wires, as a function of the core-Si nanowire width. Excellent
linear scaling by the core-Si width is observed confirming the uniformity of ALD Al2O3 and the
similarity of the sidewall dimensions for all the wires in the range of study.
Figure F.3: (a) Hole mobility of Si-core/Ge-shell multi-nanowire p-MOSFETs with Al2O3/WN gate
stack, as a function of inversion charge density; (b) Hole mobility and enhancement factor over the widest
wire with WSi-NW = 70 nm, as a function of core-Si NW width, indicating enhanced hole transport with
decreasing wire width.
Figure F.3 (a) shows the extracted low-field effective hole mobility as a function of estimated
inversion charge density (Ninv) for nanowires with Wcore-Si in the range of 20 to 70 nm. The
effective hole mobility of these devices was extracted from the current-voltage characteristics
192
and the inversion capacitance and was corrected for the series resistance (~2.5 kΩ.μm as
measured on test structures). It should be mentioned that the split CV measurements at low
vertical fields were affected by interface states and as a result, the inversion charge density
cannot be accurately calculated by integrating the CV data. Therefore, the maximum inversion
capacitance was used to estimate the inversion charge and the low field effective mobility. Use
of maximum inversion capacitance for mobility extraction results to an overestimation of the
inversion charge density and thus underestimation of the effective mobility, particularly at low
inversion charge densities. The variation of hole mobility as a function of core Si width for two
different inversion charge densities is plotted in Figure F.3 (b). The left vertical axis shows the
absolute value of mobility and the right vertical axis shows the relative mobility ratio compared
to the widest fin with WSi-NW = 70 nm. While wide wires with WSi-NW in the range of 40 to 70 nm
exhibit similar hole mobilities, a monotonic mobility increase, as high as 40%, is observed with
decreasing WSi-NW. Evidence of hole mobility enhancement in GeOI substrates has been recently
reported with decreasing mesa width down to 290 nm in 60 nm-thick GeOI substrates, where the
mobility enhancement was attributed to the increased contribution of {311} and {111} sidewalls
[173]. In our core/shell nanowire system the sidewalls are {111} Ge planes which theoretically
[174] and experimentally [175] should have hole mobility comparable to (001) Ge planes.
However, based on our TEM results on various nanowires, the {111} Ge facets have less surface
roughness compared to the top-surface (001) planes, and increased mobility for narrower NWs
could be due to reduced contribution from surface roughness scattering in the top-surface (001)
Ge. It should be noted that for these devices the epitaxial Ge layer is mostly relaxed as suggested
by the thickness and defect density. It is possible that the observed mobility increase may be
193
associated with a decreased number of dislocations as the lateral dimension of the core-Si is
decreased [169].
Figure F.4: Finite element (a) transverse and (b) longitudinal stress simulations of wide (WSi-NW = 55
nm) and narrow (WSi-NW = 20 nm) Si-core/Ge-shell nanowires based on 1.4 GPa intrinsic stress of the gate
stack. Both nanowires show similar longitudinal compressive stress. The wide nanowire shows transverse
compression while narrow nanowire shows transverse tension in the top Ge surface.
The stress induced by the WN gate (deposited at 350°C), is also a possible explanation for
the observed mobility increase. To address this, the intrinsic stress of the gate stack was
measured by wafer bow measurements and was input to the Taurus Process™ simulator to
calculate the stress profile in nanowires with two different widths. An intrinsic tensile stress level
of 1.4 GPa was measured for the gate stack. For the ease of simulations, it was assumed that the
Ge is fully relaxed prior to deposition of the gate stack. Figure F.4 shows the stress profile of the
(a) transverse and (b) longitudinal stress components for wide (WSi-NW = 55 nm) and narrow
194
(WSi-NW = 20 nm) Si-core/Ge-shell nanowires. Both structures show similar longitudinal
compressive stress profiles, with slight increase in stress for the narrower structure. It is
interesting to see that the wide nanowire shows transverse compression while the narrow
nanowire shows significant transverse tension near the top Ge surface. Considering the positive
longitudinal and negative transverse piezo-resistance coefficients of germanium [176], the
observed hole mobility increase for narrow wires may be associated with a transformation in the
lateral stress type as well as an increase in the magnitude of the longitudinal stress component.
F.3 Appendix Summary
In summary, Si-core/Ge-shell nanowire p-MOSFETs with Al2O3/WN were demonstrated by
selective epitaxial growth of Ge thin-films on Si-nanowires fabricated by a top-down approach.
Cross-sectional TEM analysis revealed that supercritical-thickness epitaxial Ge-shell facets
along {111} crystallographic planes. Hole mobility increase, as high as 40%, was observed as
the core-Si-nanowire width was decreased from 70 down to 20 nm. Increased population of the
holes in {111} faceted sidewalls with reduced surface roughness compared to the (100) top
plane, as well as stress induced by the gate stack are suggested mechanisms for this width
dependent behavior.
195
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