An Overview of Collaborative Testbeds Within the Future Renewable Electric Energy Delivery and Management Center
1
FREEDM Center
2
GEH
3
Green Energy Hub
• The Green Energy Hub testbed is an integrated hardware system demonstration incorporating technologies from the Enabling Technology and Fundamental Science research planes.
• Functions include testing and demonstration of
–
–
–
–
–
Solid State Transformer ‐ SST (Gen I, Gen II)
Fault Isolation Device ‐ FID (Gen I, Gen II)
Distributed Energy Storage Device – DESD (AC and DC)
Distributed Renewable Energy Resource ‐ DRER (PV, Wind)
Household Load Emulator
• Previous focus on basic power (Intelligent Power Management ‐ IPM) and fault management (Intelligent Fault Management ‐ IFM) functions.
4
SST Development
•
Software
– Redesign of Dual Active Bridge Code for Interleaved Operation – HIL Tested
– Inverter Implementation – HIL Tested
– Original LV‐SST Started by Sumit – Full Hardware Tested
•
Hardware
– 2x21 Semiconductor and Busbar
Mounting – Complete
– 14 Gate Drivers ‐ Complete
– Interface Board – Borrowing MMC Boards
– Transducers – Borrowing MMC Boards
– 3/12 HF Transformers – Complete
– Inverter, Rectifier – Sumit Version Working
•
Other Results
– DRER Tested in HIL
– DESD Tested in HIL
5
Hardware in the Loop Testbed
6
HIL •
HIL experiments with 10 kW Gen‐II SST at FSU‐CAPS
– Setup will also incorporate DESD interface developed under DESD sub‐thrust (Dr. Li)
•
•
Implement and test invariants for Multi‐Domain Cyber‐Physical Systems control in the HIL‐TB real‐time environment
Implement and test DGI algorithms with Cyber‐Physical Security
– Develop and test new security association (SA) mechanisms, and demonstrate the Ipsecbased
security platform using OPNET network emulator on the HIL‐TB
•
RTDS SST Model Validation
– Will validate switching and average models of SSTs used in HIL‐TB through correlation with test results from Gen‐II SST hardware
•
Advanced Controller Validation
– Implement robust control laws partly developed in Y6 (impedance uncertainty) and new robust control laws to be developed in Y7 as part of SMC project (communication uncertainty) in the DSP/FPGA controller board used for SST CHIL on HIL‐TB
•
Model Maintenance
– Develop, maintain, and version control SST simulation model library; ensure compatibility with the analytical models delivered to SMC
– Engage with the FREEDM Architecture Working Group (FAWG)
7
LSSS
Project Objectives
To demonstrate FREEDM capabilities and
functionalities in a large scale, multi-bus, distribution
system
Technical Approach
Develop a consistent distribution system on several
software platforms to provide
System Integration
Describe the ways that this project interacts with
other projects and it’s role in the overall FREEDM
system
Project Number: Y7.LSSS
PI: Crow
Co-PIs: Baran, Bhattacharya, Karady, Ferdowsi
Major Milestones
•
PSCAD model of FREEDM system – stable operation
•
OpenDSS model of FREEDM system
•
SST and FID coordinate with pilot protection to isolate
and clear fault – radial system
•
Centralized volt-var control
Final Deliverables
•
Looped/meshed pilot protection for fault management
•
Decentralized volt-var control
Significant Technical Challenges
• Computational burden of fully-modeled system
• SST model validation
Accomplishments
• Extension of system to mesh-looped system with
performance validation (stable small signal operation)
Date 1/28/2015
8
Background/Motivation
B
P = 0.1328
Q = -0.002456
V = 0.8932 BUS820
B
A
V
302
7.291 [nF]
Q822A
0.0
Q822A
0.0
Q826B
BUS864
Timed
Breaker
Logic BRK13
Closed@t0
BRK14
BUS818
0.86 [nF]
300
300
300
V = 0.9325
0.226675 [ohm]0.325 [mH]
Q824B
0.0
Q824B
4.824 [nF]
0.3012245 [ohm]0.424 [mH]
Tabc
301
PQ
301
BUS824
C
0.81225 [mH] 0.57699925 [ohm]
6.0
(MW)
Q834B
0.0
Q860C
Q860C
Q834C
#1
BUS890
#2
300
PQ
BUS888
Tabc
SST890
BRK16
Q890A
Q890B
0.0
Q890C
Q890C
BUS862
PQ
0.0
Q890A
0.0
Q890B
Q828C
BRK6
0.0
Q830A
Q830A
0.0
Q830B
Q830B
0.0
Q830C
Q830C
P = 0.003866
Q = -0.0008682
V = 0.9138
0.77311 [ohm]
A
V
Tabc
B
A
BUS828
Q810B
7.8532e-4 [H]
feeder1
feeder3
0.1003 [ohm]
0.066948 [ohm] 5.2356e-4 [H]
feeder1
0.066948 [ohm] 5.2356e-4 [H]
feeder2
feeder1
0.066948 [ohm] 5.2356e-4 [H]
0.089179 [ohm] 6.9807e-4 [H]
7.8532e-4 [H]
feeder1
feeder3
0.1003 [ohm]
0.066948 [ohm] 5.2356e-4 [H]
Tabc
Tabc
Tabc
Tabc
SST
SST
SST
SST
SST
Q4A
0.0
Q5A
0.0
Q6A
0.0
BRK64
SST
BUS838
SST
A
C
BRK63
BRKcon2
B
Timed
Breaker
Logic BRK24
Open@t0
0.0
Q856B
Tabc
0.0
0.007991 [uF]
BUS856
BRK23
Tim ed
Breaker
Logic
Open@t0
Tim ed
Breaker
Logic BRK23
Closed@t0
SST
Q3A
A
V
B
Timed
Breaker
Logic
BRKcon1
Open@t0
Tabc
0.0
Q = -0.0001951
V = 0.9136
3.2645 [mH]
C
0.089179 [ohm] 6.9807e-4 [H]
SST
Q2A
2.31933 [ohm]
303
BRKcon2
Tabc
0.0
1.08825 [m H]
A
V
feeder2
7.8532e-4 [H]
301
V = 0.8755
0.1003 [ohm]
BUS830
BRK24
0.089179 [ohm] 6.9807e-4 [H]
301
37.14 [nF]
feeder3
feeder2
PQ
BUS854
BRKcon1
12.38 [nF]
0.0
Q810B
Ec
0.6505 [mH]
SST830
BRK5
Eb
2.664 [nF]
SST
BUS810
Ea
304
BUS852
Tim ed
Breaker
Logic BRK6
Open@t0
C
0.089179 [ohm] 6.9807e-4 [H]
Q1A
Q858C
500 [kVA]
12.47 [kV] / 4.16 [kV]
A
V
V = 0.9788
5.0
Q858B
0.081657 [ohm]
4.0
0.0
Q858B
0.0
Q858C
Eb
3.0
0.0
Q834B
0.0
Q834C
SST840
Ec
2.0
Q860B
Ea
1.0
0.0
Q860B
PQ
0.0
Q828C
Timed
Breaker
Logic BRK5
Closed@t0
0.0
Q860A
Q834A
301
x
0.0
Q860A
0.0
Q834A
BUS832
SST
1.0
0.0
Timed
Breaker
Logic BRK16
Open@t0
A
2.0
301
Tabc
Q858A
B
9.24 [nF]
-1.0
BUS836
301
Tabc
0.36055225 [ohm] 216.75 [uH]
3.0
Q836C
BUS840
301
301
5.0
4.0
PQ
SST860
0.0
Q858A
C
3.08 [nF]
Main : Graphs
feeder2
0.0
Timed
Breaker
Logic BRK15
Clos ed@t0
303
Q806C
0.0
Q806C
Ps
6.0
Tabc
SST834
BRK15
Q806B
0.0
Q806B
A
301
PQ
SST858
301
BRK1
B
Q836B
BUS860
PQ
SST
BRK3
Q836A
0.0
Q836B
0.0
Q836C
PQ
BRK4
SST
0.27075 [mH] 0.192333 [ohm]
BRK2
SST836
301
Timed
Breaker
Logic BRK4
Open@t0
A
V
Timed
Breaker
Logic BRK3
Clos ed@t0
Q848C
0.0
Q836A
PQ
Qs
Timed
Breaker
Logic BRK2
Open@t0
P = 0.01551
Q = -0.0001993
V = 0.9791
1
Q848B
Tabc
303
PQ
Q848A
0.0
Q848B
0.0
Q848C
BUS834
Tabc
1.608 [nF]
BUS816
Ps
0
Timed
Breaker
Logic BRK1
Clos ed@t0
Q846C
BUS842
BUS858
0.10040825 [ohm]
141.25 [uH]
301
0.0
Q846C
0.0
Q848A
302
SST824
BUS850
PQ
Q844C
BUS826
B
PQ
BUS814
Q844B
Q846B
A
300
BUS812
0.0
Q844B
0.0
Q844C
0.0
Q846B
C
300
BUS808
BUS848
Tabc
SST848
A
A
V
P = 0.1702
Q = -0.001092
V = 0.9159
BUS806
301
Tabc
Q844A
0.0
Q844A
A
Timed
Breaker
Logic BRK63
Clos ed@t0
Q856B
Timed
Breaker
Logic BRK64
Open@t0
Q838B
0.0
Q838B
Q7A
Main : Graphs
0.0
Q1B
0.0
Q2B
0.0
Q3B
0.0
Q4B
0.0
Q5B
0.0
Q6B
0.0
Q7B
0.0
Q1C
0.0
Q2C
0.0
Q3C
0.0
Q4C
0.0
Q5C
0.0
Q6C
0.0
Q7C
10.0
I890
I890
I890
7.5
5.0
2.5
0.0
(kA)
PQ
12.47, 60.0 [Hz]
12.0 [MVA]
BUS802
A
V
301
SST846
SST
B
0.0
P = 5.929
Q = 0.1502
V= 1
BUS800
BUS846
BUS844
Tabc
SST844
2.579 [nF]
BRK13
301
P = 0.1703
Q = -0.001093
V = 0.9167
302
Tim ed
Breaker
Logic BRK14
Open@t0
C
301
3.6 [nF]
A
V1.59559575 [ohm] 2.24575 [mH]
25.55 [nF]
302
Q864A
Q826B
PQ
SST
A
A
V
BRK9
0.0
Q864A
4.7867875 [ohm] 6.7375 [mH]
B
SST
SST
76.65 [nF]
C
V = 0.8596
21.873 [nF]
BRK10
*
Ph
Timed
Breaker
Logic BRK38
Open@t0
BRK37
A
BRK38
BRK8
0.16105 [ohm] 226.75 [uH]
A
V
0.4553165 [ohm ]
0.0536835 [ohm]75.5 [uH]
BUS822
0.64075 [m H]
A
V
Timed
Breaker
Logic BRK10
Open@t0
1.36594925 [ohm]
P = 0.00194
Q = -0.0001317
V = 0.8596
Timed
Breaker
Logic BRK9
Clos ed@t0
1.9225 [mH]
A
V
P = 0.1321
Q = -0.001661
V = 0.888
12.47
V
Timed
Breaker
Logic BRK8
Open@t0
BRK7
A
IEEE Description papers and discussion available.
1.2
Timed
Breaker
Logic BRK37
Clos ed@t0
C
Tim ed
Breaker
Logic BRK7
Closed@t0
C
Developed June 2006
by Jen Z. Zhou, Dharshana Muthumuni, and Paul Wilson
This version has no wind generators and can only run in
professional version of PSCAD.
Main ...
Vs
Q820A
0.0
Q820A
IEEE 34 BUS DISTRIBUTION TEST MODEL
301
The ultimate customer of the FREEDM system are utilities. Utilities will not adopt the SST and FID until they can be assured that
• The SSTs and FIDs will not interact poorly
• System stability will be maintained
• System reliability and resiliency will be improved (benefit > cost)
The LSSS is the demonstration platform that will provide the evidence of SST and FID operation in a distribution system
-2.5
-5.0
-7.5
-10.0
-12.5
x
2.580
2.590
2.600
9
2.610
2.620
2.630
2.640
2.650
2.660
Example Project 1
Pilot directional protection
Unsymmetrical faults
•
For a fault at the given location, R1, R2 and R3 calculate the direction of fault currents. The directionality of
fault current is communicated between the relays R1, R2 and R2, R3.
•
Since R1 and R2 have the same direction of fault current, fault is not located in between them. R2 and R3
have different fault current directions. Hence fault location is in between them.
Relay
R1
R2
Trip signal
Fault
direction
Forward
Forward
No trip
Relay
Fault direction
R2
R3
Trip signal
Forward
Reverse
Trip generated
Fault is between relay 1 and relay 2
Green signal is +1  Forward fault for relay 1
Red signal is ‐1 Reverse fault for relay 2
10
Remainder of system
Example Project 1
Fault Interruption Device (FID)
11
Example Project 1
SST response inside of Fault Region
SST response outside of Fault Region
SST Waveforms
SST838B : SST Output
300
Vhs
Vhs
10.0k
200
5.0k
Input Voltage
100
y
0
-100
0.0
-5.0k
-10.0k
-200
-300
30
30
Ipl
20
10
Input Current
10
y
0
-10
0
-10
-20
-20
-30
-30
4.8k
200
100
y
0
-100
-200
-300
30
400.20
Vhdc
4.4k
4.2k
4.0k
3.8k
3.6k
3.4k
Vldc
10
y
0
-10
-20
-30
0.0
4.6k
Inl
20
x
HVDC Capacitor Voltage
Vnl
LVDC Capacitor Voltage
300
Ihs
20
1.0
2.0
3.0
4.0
5.0
6.0
7.0
400.10
400.00
399.90
399.80
399.70
x
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
12
Example Project 2
Actual solar insolation
Non‐VVC SSTs hold unity pf
Distributed Volt‐Var Control
13
Example Project 2
14