Muon Trigger Electronics in
the Counting Room
Darin Acosta
DOE/NSF Review
February 18, 1999
US CMS DOE/NSF Review: February 17-19, 1999
1
Outline
Overview of System Design
• Evolution since May 98 Lehman Review
Issues Concerning CSC/DT Interface
Progress
Plans
US CMS DOE/NSF Review: February 17-19, 1999
2
CSC Muon Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver Sector Processor
OPTICAL
FE
SR
TMB
PC
2µ / chamber
3µ / port card
SP
LCT
FE
Wire FE cards
3µ / sector
Wire LCT card
In counting house
CSC Muon Sorter
RPC
On chamber
In periphery crate
4µ
DT
4µ
4µ
Global µ Trigger
Global L1
4µ
US CMS DOE/NSF Review: February 17-19, 1999
3
Muon Track-Finding
Link trigger primitives into tracks
Assign PT, ϕ, and η
Send highest PT candidates to Global L1
θ
ϕ
US CMS DOE/NSF Review: February 17-19, 1999
4
CSC Track-Finder
Requirements
High efficiency
Trigger Rate:
• Single muon rate < few kHz at L = 1034cm-2 s-1
Resolution:
• σPt / Pt ≤ 30%
(Requires η information)
Selection:
• ≤ 3 muons per 60° sector
Redundancy
• Require only 2 stations out of 3 (or 4)
Minimal latency, pipelined, programmable
US CMS DOE/NSF Review: February 17-19, 1999
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Muon Rate dN/dηdt (Hz)
CSC Muon Trigger Rates
10 7
10
34
• Single µ rate from
Pythia, convoluted
with efficiency curve
-2 -1
L = 10 cm s
6
10 5
50%
10 4
40%
10 3
10 2
30%
• Require rates < 1 kHz
per unit rapidity
10
1
10
10
• Thresholds set for
90% efficiency
20%
CSC resolution from CMSIM
-1
10% resolution
-2
1
PYTHIA6
10
10
2
Effective PT Threshold (GeV/c)
US CMS DOE/NSF Review: February 17-19, 1999
• Not satisfied for PT
resolution worse than
30%
6
Trigger Regions in η
Overlap
1.2 > η > 0.9
Separate
trigger
regions
DT
η = 0.5
η = 1.1 η = 1
MB/1/4
MB/2/4
YB/1/3
YB/2/3
ME/1/3
7.380 m
7.000 m
MB4
5.975 m
MB3
4.905 m
MB2
YB/0/3
MB/1/3
MB/0/3
YB/2/2
YB/1/2
YB/0/2
MB/2/2
YB/2/1
MB/1/2
YB/1/1
MB/0/2
YB/0/1
MB/2/1
MB/1/1
MB/0/1
ME/1/2
ME/2/2
MB/2/3
4.020 m
3.800 m
MB1
CB/0
2.950 m 2.864 m
2.700 m
ME/1/1
YE/1
HB/1
1.9415 m
HE/1
1.711 m
HF/1
1.811 m
EB/1
EE/1
η = 3.0
ME/2/1
ME/3/1
ME/4/1
4
YE/2
η = 2.
YE/3
10.86 m
CSC
ME/3/2
ME/4/2
η = 1.479
MB/0/4
1.290 m 1.185 m
SB/1
0.440 m
η = 5.31
0.00 m
ME3 ME2
US CMS DOE/NSF Review: February 17-19, 1999
ME1
0.000 m
2.935 m
3.90 m
4.332 m
5.68 m
6.66 m
6.45 m
7.24 m
8.495 m
9.75 m
10.83 m
10.63 m
10.91 m
14.53 m
14.96 m
14.56 m
SE/1
CMS - PARA- 003 - 14/10/97
PP
/pg/hr
7
Trigger Regions in ϕ
ME1/3
MB2/2
Illustration of
overlap region
US CMS DOE/NSF Review: February 17-19, 1999
MB2/1
8
Overlap Region Issues
• CSC and DT segments are required for efficient
coverage of 0.9 < |η| < 1.2
• Agreement with Vienna and Bologna on
Barrel/Endcap boundary
• Barrel and Endcap Track-Finders are
fundamentally different (2D vs. 3D)
• Information sent both ways
• MB2/1+MB2/2 ⇒ CSC T-F
ME1/3+ME2/2 ⇒ DT T-F
• Programmable sharp η boundary
• Avoids duplication of single muon in overlap region
• Separate sorting of CSC and DT muons
US CMS DOE/NSF Review: February 17-19, 1999
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Sector Partitioning for ME1
has Changed
20°
20°
20°
Sector Sector Sector
30° → 20°
sectors
ME1 Left
ME1/3
10°
10° 10° 10° 10° 10°
ME1/2
10° 10° 10° 10° 10° 10°
ME1/1
ME1/A
10° 10° 10° 10° 10° 10°
3 → 2 µ / MPC
Muon
Port
Card
16µ
ME2/2 10°
10° 10° 10° 10° 10°
ME2/1
20°
20°
20°
ME3/2
10°
ME3/1
10° 10° 10° 10° 10°
20°
2µ
2µ
18µ
16µ
Muon
Port
Card
Sector
Receiver
Accommodates
split of ME1/1 into
two regions
60° Sector
20°
20°
ME2 and ME3
60° sectors are
unchanged
10° 10°10°10° 10°10°
16µ
2 → 3 MPC
60° Sector
ME1 Center ME1 Right
Muon
Port
Card
18µ
Muon
Port
Card
Muon
Port
Card
2µ
3µ
6µ
Barrel
CSC
Sector
Processor
OVR
Sector
Processor
6µ
3µ
Sector
Receiver
Barrel
MPC and SR
designs preserved
Barrel
US CMS DOE/NSF Review: February 17-19, 1999
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Sector Receiver Functionality
• Receives 6 µ segments via 12 optical links
from 2 Muon Port Cards (3 in ME1)
• Synchronizes the data
• Reformats the data
• LCT bit pattern → η, ϕ, Ψ, ...
via LUT
• Applies alignment corrections
• Design changes since last review:
• Communicates to Sector Processors via
custom backplane (Channel Link)
• Fans out signals to DT Track-Finder
• No longer repeats signals to Sector
Receivers in overlap crates
}
US CMS DOE/NSF Review: February 17-19, 1999
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Sector Receiver Block
Diagram
FPGAs
RAM
FPGA
Optical Links
Channel Links
US CMS DOE/NSF Review: February 17-19, 1999
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Sector Processor
Functionality
• Initial system design is new since 5/98 review
• Functional block diagram developed
• FPGA and board partitioning started
• Identify and measure muons from ~ 600 bits
every 25ns (3 GB/s)
US CMS DOE/NSF Review: February 17-19, 1999
EU7
3-4
EU6
2 -4
TAU 4
EU5
2-3
TAU 3
FSU
EU4
1**-3
TAU 2
EU3
1*-3
TAU 1
EU2
1**-2
EU1
1*-2
MUX
CLOCKED
FIFO
• Perform all possible station-to-station
extrapolations in parallel
• Simultaneously search roads in ϕ and η
• Assemble 2-, 3- and 4-station tracks
from 2-station extrapolations
• Cancel redundant short tracks if track is
3 or 4 stations in length
• Select the three best candidates
• Calculate PT, ϕ, η and send to CSC
muon sorter: 22 bits × 3 = 66 bits
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Pt
LUT
Sector Processor Block
Diagram
EU7
3-4
3–4
(9 Extrapolations or
18 bits)
Extrapolation Units
Track Assembler
4 (3x21)
2-3
TAU 4
AST4
TAU 3
AST3
Final Selection Unit
- Control Line
- Downloading/
Readout Line
2 (3x21)
EU5
2-3
2–3
(18 bits)
3-4
2-3
1*-3
3 (3x21)
EU4
1**(3x21) 1**-3
1** – 3
(18 bits)
2-4
2-3
EU3
1*-3
2 (3x21)
EU2
1**-2
2 (3x21)
2-4
EU1
1*-2
1** – 2
(18 bits)
TAU 1
AST1
1*-2
Assignment Unit
1* – 2
(18 bits)
CLOCKED
FIFO
1*(3x21)
AST2
1* – 3
(18 bits)
2-3
1**(3x21)
TAU 2
1**-2
3 (3x21)
1*(3x21)
FSU
STA
- Data Line
3 (3x21)
Input Data
15x26=390
Control
INPUT DATA &
CONTROL
INTERFACE
9U CUSTOM
BACKPLANE
1**-3
Data
VME BUS
EU6
2 -4
US CMS DOE/NSF Review: February 17-19, 1999
MUX
LID
6x21
Pt
LUT
Output
Data
3x22=66
OUTPUT
CONNECTOR
2 (3x21)
3-4
DOWNLOADING/
READOUT
INTERFACE
Input
2–4
(18 bits)
15x1
4 (3x21)
3 (3x21)
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Extrapolation Unit Detail
η1
5
η2
5
η1−η2
6
LUT
SM
& Match η
64x1
η1
5
η road finder
η1−η2
LUT
LUT
32x6
32x1
η2
5
LUT
LUT
32x6
32x2
Input Data
42 Bits
η1
η2
5
5
φ1
7
φ2
ψ1
SL
MUX
2x1
5
8
7
SM
φ1−φ2
6
LUT
LUT
32x6
6
6
6
6
LUT
6
CMP
η∗, ∆φ
6
CMP
η∗∗, ∆φ
6
CMP
η∗∗∗, ∆φ
3
LUT
6
6
6
64x6
Q1 3
Q2 3
6
PRE
LUT
16x2
2
3-2
Match φ
2
Output Data
2
&
q1,q2
Result quality
Coarse PT assign
&
8x1
6
ψ2
z
SM
7
∆φ−ψ1
SM
7
∆φ−ψ2
LUT
Match ψ1
128x1
LUT
Match ψ2
ϕ road finder
128x1
ϕ
2
64x2
US CMS DOE/NSF Review: February 17-19, 1999
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Muon Sorter Functionality
• New processor added since last review
• The 3 highest rank muons from each Sector
Processor are sent to the CSC muon sorter,
which selects the 4 highest rank
• Total muon count:
• 3 muons × 6 sectors × 2 endcaps × 2 regions = 72 muons
for CSC and OVL regions
• Sort is based on 7 bits (5 bits for PT and 2 bits
for quality)
• Basic sorting unit design (4 best out of 8) is complete
• Input: 72 × 22 bits = 1584 bits
• Output: 4 × 22 bits = 88 bits
• Sent to Global L1 Muon Trigger for association with RPC
and DT triggers
US CMS DOE/NSF Review: February 17-19, 1999
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Muon Sorter Block Diagram
US CMS DOE/NSF Review: February 17-19, 1999
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Old CSC Track-Finder Crate
Organization
Endcap 1
360°
Endcap 2
CSC
OVL
OVL
CSC
Rack 1
Rack 2
Rack 3
Rack 4
180°
ϕ
0°
CSC Counting House electronics:
Racks: 4
Three 60° sectors
per crate
Crates: 8 (including power supply, controller, CCC)
Sector Receivers: 48
Sector Processors: 24
US CMS DOE/NSF Review: February 17-19, 1999
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New CSC Track-Finder Crate
Organization
Endcap 1
360°
CSC+OVL
Endcap 2
CSC+OVL
CSC and overlap regions
now handled in same crate
240°
120°
ϕ
Two 60° sectors
per crate
0°
CSC Counting House electronics:
Racks: 3 or 4
Crates: 6 (was 8)
Sector Receivers: 24 (was 48)
Sector Processors: 24
Muon Sorter: 1 (new)
US CMS DOE/NSF Review: February 17-19, 1999
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New Layout for CSC
Track-Finder Crate
S
R
C
S
C
S
SP SP
R
CSC OVL C
S
C
ME 1
ME2,3
208
D
T
I
M
S
R
C
S
C
S
SP SP
R
CSC OVL C
S
C
ME 1
D
T
I
M
C
C
C
C
P
U
ME2,3
208
208
208
204
204
• Two 60° sectors housed in one 9U VME crate with
custom backplane
• Each SR-CSC sends 6 CSC muon stubs × 34 bits
and 4 bits BXN = 208 bits
• Each DT-IM sends 8 DT muon stubs × 25 bits
and 4 bits BXN = 204 bits
US CMS DOE/NSF Review: February 17-19, 1999
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Required Precision of Data
Azimuthal angle ϕ:
• 12 bits / 60° ⇒ 1 bit / 0.26 mrad (0.1 strip)
Bend angle Ψ:
Ψ
• 6 bits / ±45° ⇒ 1 bit / 60 mrad
ϕ2
ϕ1
Polar angle η:
• 6 bits / 1.5 units ⇒ 1 bit / 0.025
∆ϕ
Quality:
• 3 bits
Chamber i.d.:
• 6 bits
34 bits per CSC
segment to Sector
Processor
Accelerator µ flag: 1 bit
US CMS DOE/NSF Review: February 17-19, 1999
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Track Segments per 60°
Sector
Region Station
Chamber Segments No. of ϕ
per sector sectors
No. of
Extrapsegments olations
CSC
1
2
3
4*
ME1
ME2
ME3
ME4*
2
3
3
3*
3
1
1
1*
6
3
3
3*
12, 15*
OVL
1
2
3
4
MB1
MB2
ME1
ME2
2
2
2
3
2
2
3
1
4
4
6
3
17
81
106
Segments sent by Muon Port Cards to
Sector Receivers via optical links.
Processed by Sector Processor
US CMS DOE/NSF Review: February 17-19, 1999
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Design Progress
• Full conceptual design from trigger primitives
to Global L1 Trigger
• Bit counts fully documented
• Crate design underway
• Sector Receiver functionality defined
• Sector Processor algorithms defined
• Sort algorithms defined
• Simulation of Track-Finder performance
underway
• resolution, efficiency, rate, chamber
misalignment
• Prototyping started
US CMS DOE/NSF Review: February 17-19, 1999
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Milestones / Schedule
√ D387 – 1999 Mar, Sector Receiver Initial System Design
√ D331 – 1999 Mar, Sector Processor Initial System Design
D390 – 1999 Sep, Sector Receiver Prototype Design
D332 – 1999 Sep, Sector Processor Prototype Design
started
D391 – 2000 Jan, Sector Receiver Prototype
D334 – 2000 Jan, Sector Processor Prototype
D335 – 2000 Apr, Sector Receiver / Processor Crate Test
tests to do:
MPC → SR optical link test
2 × SR + SP + CCC crate test
3 × MPC + 2 × SR + SP + CCC sector test
US CMS DOE/NSF Review: February 17-19, 1999
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