Sector Processor Design Status
D. Acosta, S.M. Wang
University of Florida
A. Atamanchuk, V. Golovstov, B. Razmyslovich
PNPI
CSC Muon Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver Sector Processor
OPTICAL
FE
SR
TMB
PC
2µ / chamber
3µ / port card
SP
LCT
FE
Wire FE cards
3µ / sector
Wire LCT card
In counting house
CSC Muon Sorter
RPC
On chamber
4µ
In periphery crate
DT
4µ
Global µ Trigger
D. Acosta, University of Florida
3/27/99
4µ
4µ
Global L1
2
Muon Track-Finding
• Link trigger primitives into tracks
• Measure PT, ϕ, and η
• Transmit highest PT candidates to Global L1
θ
ϕ
D. Acosta, University of Florida
3/27/99
3
CSC Track-Finder Requirements
• High efficiency
• Trigger Rate:
– Single muon rate < few kHz at L = 1034cm-2 s-1
• Resolution:
– σPt / Pt ≤ 30%
– Ideally
(Requires η information)
≤ 20% ⇒ 3-station sagitta measurement
• Selection:
– ≤ 3 muons per 60° sector
• Redundancy
– Require only 2 stations out of 3 (or 4)
• Minimal latency, pipelined, programmable
D. Acosta, University of Florida
3/27/99
4
Trigger Regions in η
Separate
trigger
regions
Overlap
1.2 > η > 0.9
DT
MB4
MB3
MB2
CSC
MB1
ME3 ME2
D. Acosta, University of Florida
3/27/99
ME1
5
Trigger Regions in ϕ
ME1/3
MB2/2
Illustration of
overlap region
D. Acosta, University of Florida
MB2/1
3/27/99
6
Sector Partitioning
20°
20°
20°
Sector Sector Sector
30° → 20°
sectors
60° Sector
60° Sector
ME1 Left ME1 Center ME1 Right
ME1/3
10° 10° 10° 10° 10° 10°
ME1/2
10° 10° 10° 10° 10° 10°
ME1/1
ME1/A
10° 10° 10° 10° 10° 10°
10° 10° 10° 10° 10°
ME3/2
ME2/1
20°
ME3/1
20°
20°
10°
10° 10° 10° 10° 10°
20°
20°
20°
ME2 and ME3
60° sectors are
unchanged
10° 10° 10° 10° 10°10°
16µ
2 → 3 MPC
ME2/2 10°
16µ
Muon
Port
Card
3 → 2 µ / MPC
Muon
Port
Card
2µ
S
R
2µ
e c t o r
18µ
16µ
Muon
Port
Card
18µ
Muon
Port
Card
Muon
Port
Card
2µ
3µ
CSC
6µ
Sector
e c e i v e r
S
6µ
R
3µ
e c t o r
e c e i v e r
Processor
Accommodates
split of ME1/1 into
two regions
OVR
Barrel
Sector
Processor
Barrel
MPC and SR
designs preserved
Barrel
D. Acosta, University of Florida
3/27/99
7
Sector Processor Functionality
– Perform all possible station-to-station extrapolations in parallel
• Simultaneously search roads in ϕ and η
– Assemble 3- and 4-station tracks from 2-station extrapolations
– Cancel redundant short tracks if track is 3 or 4 stations in length
– Select the three best candidates
– Calculate PT, ϕ, η and send to CSC muon sorter: 22 bits × 3 = 66
bits
D. Acosta, University of Florida
3/27/99
8
Sector Processor Block Diagram
4 (3x26)
Final Selection Unit
EU4
2-4
2–4
(18 bits)
3-4
3-2
TAU 2
3-1
- Control Line
- Downloading/
Readout Line
D. Acosta, University of Florida
Track 4
2-4
2-3
2-1
3 (3x26)
1(6x26)
EU2
1-3
1– 3
(36 bits)
TAU 1
Track 3
Track 2
Track 1
2 (3x26)
1(6x26)
EU1
1-2
1–2
(36 bits)
Assignment Unit
Data
Extraction
MUX
CLOCKED
FIFO
U – Extrapolation Unit
AU – Track Assembling Unit
SU – Final Selection Unit
TA –Selected Track Address
ID – Look-Up Input Data
2(3x26)
2–3
(18 bits)
FSU
Track 5
3 (3x26)
EU3
2-3
Track 6
VME BUS
2 (3x26)
LID
Pt
LUT
Output
Data
3x22=66
3/27/99
OUTPUT
CONNECTOR
- Data Line
Track Assembler
DOWNLOADING/
READOUT
INTERFACE
Control
EU5
3 -4
4 (3x26)
Input Data
15x34=510
Data
3 (3x26)
INPUT DATA &
CONTROL
INTERFACE
9U CUSTOM
BACKPLANE
Input
Extrapolation Units
3–4
(9 Extrapolations or
18 bits)
9
Extrapolation Unit Detail
η1
6
SM
η2
6
η1−η2
7
LUT
128 x 1
η road finder
&
Match η
z
η1
6
LUT
6
64 x 1
LUT
7
7
1
η2
6
LUT
6
64 x 1
CMP
128 x 7
LUT
128 x 7
PRE
3-2
CMP
7
7
1
η∗,∆φ
η∗∗,∆φ
LUT
2
16 x 2
6
6
LUT
128 x 7
10
SM
φ2
10
φ1−φ2
7
11
3
6
SM
∆φ−ψ1
6
ψ2
6
Q1
3
Q2
3
AMB1
1
AMB2
1
7
Match φ
&
Coarse PT assign
6
6
LUT
64 x 2
∆φ−ψ2
LUT
Match ψ1
128 x 1
6
SM
Accel. µ
LUT
LUT
64 x 6
ψ1
Result quality
η∗∗∗,∆φ
8x1
6
Quality
2 Q
CMP
7
1
φ1
&
2 Bits
Input Data
52 Bits
η1
2
7
LUT
Match ψ2
128 x 1
ϕ road finder
2
ϕ
NAND
FIG.2. EXTRAPOLATION UNIT. BLOCK DIAGRAM.
D. Acosta, University of Florida
3/27/99
10
Sector Processor Logic
Chamber
M E4
4
4
1
4
2
3
Chamber
M E3
3
3
1
3
2
3
Chamber
M E2
2
2
1
2
2
3
Chamber
M E1
1 *
1 *
1
1 *
1 *
2
1 **
3
1 **
1
• Perform all combinations
of extrapolations in
parallel:
– 1i ↔ 2k, 1i ↔ 3k, 2i ↔ 3k,
2i ↔ 4k
– But not 1i ↔ 4k
• Track Assembler takes
best 2 or 3 extrapolations
per reference segment
1 **
2
3
1 **
D. Acosta, University of Florida
3/27/99
11
Data Stream Paths
2 best
33 – 4
33
2 best
2 – 33
32
1 – 3, 2 – 3, 3 – 4
Extrapolations
3 best
1 – 33
2 best
32 – 4
2 best
2 – 32
3 best
1 – 32
Track Assembler Unit
(TAU2)
Str eam 2
Track types:
2 best
31 – 4
31
2 best
2 – 31
1–3
2–3
3–4
3 best
1 – 31
1–3–4
2–3–4
Extrapolation
Units
2 best
21 – 3
2 best
21 – 4
Track Assembler Unit
(TAU1)
3 best
1 – 21
21
Stream 1
Track types:
1–2
2–4
1–2–3
1–2–4
1–2–3–4
2 best
22 – 3
1 – 2, 2 – 3, 2 – 4
Extrapolations
2 best
22– 4
22
3 best
1 – 22
2 best
23 – 3
D. Acosta, University of Florida
3/27/99
2 best
23 – 4
23
3 best
1 – 23
12
15 ([2bits Quality + 3bits Number] x 3)
8 ([2bits Quality + 2bits Number] x 2)
21 – 3
21 – 4
22 – 1
22 – 3
22 – 4
23 – 1
23 – 3
23 – 4
6
6
3 best
extrapolations
4 (2+2) best
extrapolations
15
8
8
15
12
6
6
12
6
6
3 best
extrapolations
4(2+2) best
extrapolations
3 best
extrapolations
4(2+2) best
extrapolations
15
Multiplexer
8
8
15
15
8
8
Sel1
6
4
21 – 1
21 – 3
21 – 4
6
4
4
15
To Final Selection Unit
21 – 1
12
4
LUT
32Kx16
Link
21
6
4
4
Link
22
6
4
4
Extrapolations Quality
Link
23
4
A3
4
A2
4
A1
4
B3
4
B2
4
B1
4
C3
4
C2
4
C1
Sel2
Selection
Unit
(3 Best
Tracks)
4
4
4
Track Local Quality
Fig.2.Track Assembling Unit (TAU1)
Sel3
15 bits:
Hit number (1st chamber) – 3 bits
Hit number (2nd chamber) – 2 bits
Hit number (3rd chamber) – 2 bits
Hit number (4th chamber) – 2 bits
2 – 1 Quality – 2 bits
2 – 3 Quality – 2 bits
2 – 4 Quality – 2 bits
15 ([2bits Quality + 3bits Number] x 3)
8 ([2bits Quality + 2bits Number] x 2)
31 – 2
31 – 4
32 – 1
32 – 2
32 – 4
33 – 1
33 – 2
33 – 4
6
6
3 best
extrapolations
4 (2+2) best
extrapolations
15
8
8
15
12
6
6
12
6
6
3 best
extrapolations
4(2+2) best
extrapolations
3 best
extrapolations
4(2+2) best
extrapolations
15
Multiplexer
8
8
15
15
8
8
Sel1
6
4
31 – 1
31 – 2
31 – 4
6
4
4
15
To Final Selection Unit
31 – 1
12
4
LUT
32Kx16
Link
31
6
4
4
Link
32
6
4
4
Extrapolations Quality
Link
33
4
A3
4
A2
4
A1
4
B3
4
B2
4
B1
4
C3
4
C2
4
C1
Sel2
Selection
Unit
(3 Best
Tracks)
4
4
4
Track Local Quality
Fig.2a.Track Assembling Unit (TAU2)
Sel3
15 bits:
Hit number (1st chamber) – 3 bits
Hit number (2nd chamber) – 2 bits
Hit number (3rd chamber) – 2 bits
Hit number (4th chamber) – 2 bits
3 – 1 Quality – 2 bits
3 – 2 Quality – 2 bits
3 – 4 Quality – 2 bits
Selection Unit Implementation in TAU
A3
B3
C2
C1
B3
C3
A2
A1
A3
C3
B2
B1
A2
B2
C2
D. Acosta, University of Florida
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
LUT
64Kx4
LUT
4
32Kx16
LUT
64Kx4
4
4
Sel3
4
Sel2
4
Sel1
LUT
64Kx4
4
LUT
64Kx4
3
3/27/99
15
8 bits:
1st track segment number – 4 bits;
2nd track segment number – 4 bits.
Stream 2
Track 5
Track 4
8
8
8
Track 3
1
From Track Assemling Unit
(Hit Number Part)
To Data Extraction Multiplexer
MUX
Track 6
(if we need only 2 track segments
for Pt calculation)
Track 2
Track 1
Sel1 Sel2 Sel3
We should compare:
Track1-Track4; Track1-Track5;
Track1-Track6; Track2-Track4;
Track2-Track5; Track2-Track6;
Track3-Track4; Track3-Track5;
Track3-Track6 (9 bits as total)
10
10
10
9
9
Stream 2
Stream1
From Track Assemling Unit
(Extrapolations Quality Part)
9
Track 6
Track 5
Track 4
Track 3
Track 2
Track 1
6
6
6
6
6
6
9
Final
Decision
Unit
Track1
18
Fig.5. Final Selection Unit
2–1
2–3
2–4
3–1
3–2
3–4
Track4
2
2
2
2
2
2
Extrapolations
Quality Comparator
(1 Units)
9
Extrapolations
Quality Comparators
(9 Units)
9
Hit Number
Comparators
(9 Units)
9
Each track consists of 4 track
segments as maximum
⇓
6 Tracks has 24 track
segments
⇓
We need 10 (5+5)bits to
describe all possible
combinations
Track1>Track4
Track1=Track4
Track1<Track4
2
New CSC Track-Finder Crate Organization
Endcap 1
360°
CSC+OVL
Endcap 2
CSC+OVL
240°
120°
ϕ
CSC and overlap regions
now handled in same crate
0°
CSC Counting House electronics:
Racks: 3 (was 4)
Two 60° sectors
per crate
Crates: 6 (was 8)
Sector Receivers: 24 (was 48)
Sector Processors: 24
Muon Sorter: 1 (new)
D. Acosta, University of Florida
3/27/99
17
New Layout for CSC Track-Finder Crate
S
R
C
S
C
S
R
C
S
C
ME 4
ME 1
S
SP SP
R
CSC OVL C
S
C
D
T
I
M
ME2,3
S
R
C
S
C
S
R
C
S
C
ME 4
ME 1
208
S
SP SP
R
CSC OVL C
S
C
D
T
I
M
C
C
C
C
P
U
ME2,3
208
208
208
204
204
106
106
– Two 60° sectors housed in one 9U VME crate with custom backplane
– Each SR-CSC sends 6 CSC muon stubs × 34 bits and 4 bits BXN = 208 bits
(3 stubs for ME4)
– Each DT-IM sends 8 DT muon stubs × 25 bits and 4 bits BXN = 204 bits
D. Acosta, University of Florida
3/27/99
18
Required Precision of Data
• Azimuthal angle ϕ:
– 12 bits / 60° ⇒ 1 bit / 0.26 mrad (0.1 strip)
• Bend angle Ψ:
– 6 bits / ±45° ⇒ 1 bit / 60 mrad
• Polar angle η:
– 6 bits / 1.5 units ⇒ 1 bit / 0.025
• Quality:
Ψ
ϕ2
ϕ1
∆ϕ
– 3 bits
• Chamber i.d.:
– 6 bits
• Accelerator µ flag: 1 bit
34 bits per CSC
segment to Sector
Processor
D. Acosta, University of Florida
3/27/99
19
Track Segments per 60° Sector
Region Station
Chamber Segments No. of ϕ
per sector sectors
No. of
Extrapsegments olations
CSC
1
2
3
4*
ME1
ME2
ME3
ME4*
2
3
3
3*
3
1
1
1*
6
3
3
3*
12, 15*
OVL
1
2
3
4
MB1
MB2
ME1
ME2
2
2
2
3
2
2
3
1
4
4
6
3
17
81
106
• Segments sent by Muon Port Cards to Sector Receivers via
optical links.
• Processed by Sector Processor
D. Acosta, University of Florida
3/27/99
20
2- or 3-station PT Assignment
0.5 strip resolution (0.06°)
Range Limited
η
ϕ1
10
ϕ2
10
4
1 sign
3 MSB
Subtract
1 match
< 7.5°
∆ϕ12
8
7 LSB
5
ϕ2
ϕ3
1 sign
8
8
4Mb
x5
4 MSB
Subtract
< 3.75°
1 match
4 LSB
∆ϕ23
5
Could also be Ψ
i.d.
di-strip resolution (0.25°)
PT
4
1-2, 1-3, 1-4, 2-3, 2-4, 3-4
1-2-3, 1-2-4, 1-3-4, 2-3-4
D. Acosta, University of Florida
3/27/99
21