Status of the CSC Track-Finder
D. Acosta, S.M. Wang
University of Florida
A.Atamanchook, V.Golovstov, B.Razmyslovich
PNPI
CSC Muon Trigger Scheme
Strip FE cards
Strip LCT card
LCT
CSC Track-Finder
Motherboard
Port Card
Sector Receiver Sector Processor
OPTICAL
FE
SR
TMB
PC
2µ / chamber
3µ / port card
SP
LCT
FE
Wire FE cards
3µ / sector
Wire LCT card
In counting house
CSC Muon Sorter
RPC
On chamber
4µ
In periphery crate
DT
4µ
Global µ Trigger
D. Acosta, University of Florida
3/27/99
4µ
4µ
Global L1
2
Muon Track-Finding
• Link trigger primitives into tracks
• Measure PT, ϕ, and η
• Transmit highest PT candidates to Global L1
θ
ϕ
D. Acosta, University of Florida
3/27/99
3
Design Status
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Nearly complete conceptual design presented
late March at SR/SP review
Primary concern is the design of the Track
Assembler, the heart of the Track-Finder
– Digests extrapolation results and must determine
the quantity and quality of trigger muons
– Scheme proposed, but must be validated with
physics simulation
– Must avoid ghost tracks for multi-muon trigger, yet
maintain high efficiency for high PT single muons
Sector Processor Block Diagram
4 (3x26)
Final Selection Unit
EU4
2-4
2–4
(18 bits)
3-4
3-2
TAU 2
3-1
- Control Line
- Downloading/
Readout Line
D. Acosta, University of Florida
Track 4
2-4
2-3
2-1
3 (3x26)
1(6x26)
EU2
1-3
1– 3
(36 bits)
TAU 1
Track 3
Track 2
Track 1
2 (3x26)
1(6x26)
EU1
1-2
1–2
(36 bits)
Assignment Unit
Data
Extraction
MUX
CLOCKED
FIFO
U – Extrapolation Unit
AU – Track Assembling Unit
SU – Final Selection Unit
TA –Selected Track Address
ID – Look-Up Input Data
2(3x26)
2–3
(18 bits)
FSU
Track 5
3 (3x26)
EU3
2-3
Track 6
VME BUS
2 (3x26)
LID
Pt
LUT
Output
Data
3x22=66
3/27/99
OUTPUT
CONNECTOR
- Data Line
Track Assembler
DOWNLOADING/
READOUT
INTERFACE
Control
EU5
3 -4
4 (3x26)
Input Data
15x34=510
Data
3 (3x26)
INPUT DATA &
CONTROL
INTERFACE
9U CUSTOM
BACKPLANE
Input
Extrapolation Units
3–4
(9 Extrapolations or
18 bits)
9
Sector Processor Logic
Chamber
M E4
4
4
1
4
2
3
Chamber
M E3
3
3
1
3
2
3
Chamber
M E2
2
2
1
2
2
3
Chamber
M E1
1 *
1 *
1
1 *
1 *
2
1 **
3
1 **
1
• Perform all combinations
of extrapolations in
parallel:
– 1i ↔ 2k, 1i ↔ 3k, 2i ↔ 3k,
2i ↔ 4k
– But not 1i ↔ 4k
• Track Assembler takes
best 2 or 3 extrapolations
per reference segment
1 **
2
3
1 **
D. Acosta, University of Florida
3/27/99
11
Data Stream Paths
2 best
33 – 4
33
2 best
2 – 33
32
1 – 3, 2 – 3, 3 – 4
Extrapolations
3 best
1 – 33
2 best
32 – 4
2 best
2 – 32
3 best
1 – 32
Track Assembler Unit
(TAU2)
Str eam 2
Track types:
2 best
31 – 4
31
2 best
2 – 31
1–3
2–3
3–4
3 best
1 – 31
1–3–4
2–3–4
Extrapolation
Units
2 best
21 – 3
2 best
21 – 4
Track Assembler Unit
(TAU1)
3 best
1 – 21
21
Stream 1
Track types:
1–2
2–4
1–2–3
1–2–4
1–2–3–4
2 best
22 – 3
1 – 2, 2 – 3, 2 – 4
Extrapolations
2 best
22– 4
22
3 best
1 – 22
2 best
23 – 3
D. Acosta, University of Florida
3/27/99
2 best
23 – 4
23
3 best
1 – 23
12
15 ([2bits Quality + 3bits Number] x 3)
8 ([2bits Quality + 2bits Number] x 2)
21 – 1
21 – 3
21 – 4
22 – 1
22 – 3
22 – 4
23 – 1
23 – 3
23 – 4
12
6
6
12
6
6
3 best
extrapolations
4 (2+2) best
extrapolations
3 best
extrapolations
4(2+2) best
extrapolations
9
15
3bits + 3bits + 3bits
according to the order of
priority (PCB Layout)
8
4
9
4
8
2bits + 2bits
according to the order of
priority (PCB Layout)
15
9
9
8
4
8
4
15
9
9
Multiplexer
4
12
6
6
3 best
extrapolations
4(2+2) best
extrapolations
4
8
4
8
4
Sel1 Sel2
36
6
4
21 – 1
21 – 3
21 – 4
6
4
4
4
LUT
32Kx16
Link
21
6
4
4
Link
22
6
4
4
Extrapolations Quality
Link
23
4
A3
4
A2
4
A1
4
B3
4
B2
4
B1
4
C3
4
C2
4
C1
4
Selection
Unit
Sel3
4
4⇒5
4⇒5
4⇒5
To Final Selection Unit
(Hit Number Part)
To Final Selection Unit
(Extrapolation Quality Part)
7 bits:
Hit number (1st chamber) – 3 bits
Hit number (2nd chamber) – 2 bits
Hit number (3rd chamber) – 2 bits
Hit number (4th chamber) – 2 bits
5
5
5
Track Absolute Quality
4
4
(3 Best
Tracks)
Track Local Quality
Track Assembler Unit (TAU1)
2bits + 2bits:
2 bits select 21, 22 or 23 stream
2bits select h., m. or l. priority track.
9
Track 5
9
Track 4
9
MUX
8
Track 3
9
Track 2
9
Track 1
9
8
Sel1 Sel2 Sel3
We should compare:
Track1-Track4; Track1-Track5;
Track1-Track6; Track2-Track4;
Track2-Track5; Track2-Track6;
Track3-Track4; Track3-Track5;
Track3-Track6 (9 bits as total)
10
10
10
9
9
9
Stream1 Stream 2
From Track Assemling Unit
(Extrapolations Quality Part)
9
Track 6
Track 5
Track 4
Track 3
Track 2
Track 1
5
5
5
5
5
5
Extrapolations
Quality Comparators
(9 Units)
9
Hit Number
Comparators
(9 Units)
9
9
Final
Decision
Unit
LUT
256Kx32
9
Final Selection Unit
To Data Extraction Multiplexer
Stream 2
Track 6
(if we need only 2 track segments
for Pt calculation)
8
Stream 1
From Track Assemling Unit
(Hit Number Part)
8 bits:
1st track segment number – 4 bits;
2nd track segment number – 4 bits.
Each track consists of 4 track
segments as maximum
⇓
6 Tracks has 24 track
segments
⇓
We need 10 (5+5)bits to
describe all possible
combinations
A3
B3
C2
C1
4
4
4
4
B3
C3
A2
A1
4
4
4
4
A3
C3
B2
B1
4
4
4
4
A2
B2
C2
4
4
4
LUT1
64Kx4
LUT
4
32Kx16
LUT2
64Kx4
4
4
Sel3
4
Sel2
4
Sel1
LUT3
64Kx4
4
LUT4
3
64Kx4
A3 ≥ A2 ≥ A1
B3 ≥ B2 ≥ B1 C3 ≥ C2 ≥ C1
Selection Unit (TAU1,TAU2) hardware realization
Preparation for full SP review in July
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Finalize backplane and SR↔SP signals,
including 4-station capability
Determine connector space at backplane
Estimate FPGA and RAM count
Estimate board area (must fit on 9Ux400mm)
Estimate cost
Validate basic scheme with simulations