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Next Generation Sector Processor I/O Specification
University of Florida
St. Petersburg Nuclear Physics Institute
May 28, 2016
Abstract
The conceptual design of the next generation Sector Processor, which merges the
Sector Receiver functionality onto the same board, is described in this document.
Table 1: Data delivered from the Muon Port Card to the Sector Receiver. Data for one
stub fit on one optical link.
Signal
Bits / stub
½ Strip
CLCT
pattern
L/R bend
Quality
8
4
Bits / 3 stubs
(1 MPC)
24
12
1
4
3
12
Wire group
CSC i.d.
BXN
Valid pattern
Error
Total:
7
4
2
1
1
32
21
12
6
3
3
96
Bits / 15 stubs Description
(ME1–ME4)
120
½ strip label
60
Pattern number. Can be
combined with L/R bend.
15
Sign bit for pattern
60
Comes from ALCT and CLCT
patterns, TMB status, BXN
match, and Accel. Muon bit
105
Wire group label
60
Chamber label in subsector
30
2 LSB of BXN
15
Must be set for above to apply
15
Synch. Error upstream
480
(240 bits at 80 MHz to SR)
Table 2: Format of the 2 data frames sent at 80 MHz between the Muon Port Card and
the Sector Receiver.
15
FR1
VP
FR2
14
13
12
11
Quality
CSC ID
10
09
08
07
06
BC
0
SE
04
03
02
01
00
Wire Group ID
CLCT Pattern #
BC
1
05
L/R
CLCT half-strip
Table 2: Data delivered from the Sector Receiver to the Sector Processor (on the same
board). The CSC i.d. bits are for ME1 only.
Signal
Bits / stub

b

CSC i.d. *
Quality
12
5
7
4
4
Bits / 6 stubs
(ME1)
72
30
42
24
24
Total:
32
192
Bits / 15 stubs
(ME1–ME4)
180
75
105
24
60
444
Description
Azimuth coordinate
 bend angle
Pseudorapidity
Chamber label (ME1 only)
Computed by TMB,
includes Accel. Muon bit
Table 3: Data delivered from the Sector Receiver to the DT Track-Finder through a
transition board behind the backplane. Two connections are needed, each of which
delivers 3 stubs. Data should be sent at 40 MHz using LVDS.
Signal
Bits / stub


Quality
BXN
Clock
BC0
Total:
12
1
3
–
–
–
16
Bits / 3 stubs
(ME1: 30)
36
3
9
2
1
1
52
Bits / 6 stubs
(ME1: 60)
72
6
18
4
2
2
104
Description
Azimuth coordinate
DT/CSC region flag
Derived from 4 bit Quality
2 LSB of BXN
Clock for data
Bunch Crossing 0
Table 4: Data delivered from the DT Track-Finder to the Sector Processor through a
transition board behind the backplane. Two stubs from one chamber in the same bunch
crossing are transmitted on consecutive bunch crossings. Two connections from two
different DT Sector Processors are implemented using LVDS at 40 MHz.
Signal

b
Quality
Muon Flag
BXN
Clock
BC0
Calib.
Total:
Bits / stub
12
5
3
1
2
1
1
1
26
Bits / 2 stubs
(MB1: 60)
24
10
6
2
4
2
2
2
52
Description
Azimuth coordinate
 bend angle
2nd muon of previous BX
2 LSB of BXN
Clock for data
Bunch Crossing 0
Special DT mode
Table 5: Data delivered to/from the Sector Processor to the Muon Sorter on a backplane.
An asterisk denotes data sent from the Muon Sorter back to the Sector Processor.
Signal
Bits / 


Rank
Halo Muon
Charge
Valid Charge
5
5
7
1
1
1
BXN
Error
Spare
MS winner bits*
Total:
–
–
–
20
Bits / 3 
(1 SP)
15
15
21
3
3
3
Bits / 36 
(12 SP)
180
180
252
36
36
36
2
1
1
4
68
24
12
12
48
816
Description
Azimuth coordinate
Pseudorapidity
5 bits pT + 2 bits quality
Halo muon trigger
Muon sign
Charge assignment OK?
(8th bit from Rank LUT)
2 LSB of BXN
(408 bits at 80 MHz, 34 per SP)