Conceptual Design for SR/SP
Topics:
è
è
è
è
è
Board Layout
Bit counts and data serialization
Memory architecture
(PNPI)
SP to Verilog Translation (Madorsky)
DDU plans
USCMS Trigger Meeting, August 2001
1
Darin Acosta
Possible Single Crate Solution
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
CCB/MS
CCB/MS Card
(CCB +
Muon Sorter)
BIT3 Controller
Track-Finder crate (1.6 Gbits/s optical links)
SR SR SR SR SR SR
/ / / / / /
SP SP SP SP SP SP
SR/SP Card
(3 Sector Receivers +
Sector Processor)
(60° sector)
From MPC
(chamber 4)
From MPC
(chamber 3)
From
TTC
From MPC
(chamber 2)
From MPC
(chamber 1B)
To
Global Trigger
From MPC
(chamber 1A)
From / To
Barrel
•
•
•
•
Total latency: ~ 20Bx (from input of SR/SP card to output of CCB/MS card)
Power consumption: ~ 500W per crate
17 optical connections per SR/SP card (15 - from endcap, 2 – from/to barrel)
15
Custom backplane for SR/SPs < > CCB/MS connection
USCMS Trigger Meeting, August 2001
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Darin Acosta
Merged SR/SP
15 trigger links, 1 DAQ
Small Form
Factor
Deserializer Front
Transceivers
Chips
FPGAs
From
trigger
primitives
45 SRAM
Memory
Look-up
Tables
From MPC
(chamber 4)
~45 SRAM chips
80 MHz speed
VME
Interface
Sector
Processor
FPGA chip
From MPC
(chamber 3)
From MPC
(chamber 2)
To Muon
Sorter
From MPC
(chamber 1C)
Ptassignment
LUTs
From MPC
(chamber 1B)
To/From
Barrel
From MPC
(chamber 1A)
To CSC DAQ
1 April 2001
Input: 528 bits/sector/b.x.
USCMS Trigger Meeting, August 2001
From Clock
and Control
Board
Output: 60 bits/sector/b.x.
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Darin Acosta
Salient Features
Bi-Directional Optical Links
èSince
we have both transmitters and receivers in the optical
connection, this allows the option to send data as well as
receive
è Makes testing much easier
p One board sends data to other, or even itself through links
SR memory set for each muon stub
è
No muon multiplexing means shortest latency
SP chip on a mezzanine board
è
è
Decouples board development from FPGA technology
Makes upgrades easier
DT fan-out on transition board
Deliver all possibly needed signals to backplane connector
è Settle transmission technology, connector type, connector
count on transition board at a later date
è
USCMS Trigger Meeting, August 2001
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Darin Acosta
SR/SP Inputs
è
Muon Port Cards deliver 15 track stubs each BX via optical
Signal
Sent on
first
frame
èDT
Bits / stub
½ Strip *
CLCT
pattern *
L/R bend *
Quality *
Wire group
Accelerator µ
CSC i.d.
8
4
Bits / 3 stubs
(1 MPC)
24
12
Bits / 15 stubs
(ME1–ME4)
120
75
1
3
7
1
4
3
9
21
3
12
15
45
105
15
60
BXN
Valid pattern
2
1
6
3
30
15
Spare
Total:
1
32
3
96
15
480
Description
½ strip label
Pattern number without
4/6, 5/6, 6/6
Sign bit for pattern
Computed by TMB
Wire group label
Straight wire pattern
Chamber label in
subsector
2 LSB of BXN
Must be set for above
to apply
(240 bits at 80 MHz)
Reduced
from 5
Needed
for frame
info
Track-Finder delivers 2 track stubs each BX via LVDS
Signal
Bits / stub
φ
φb
Quality
BXN
Synch/Calib
Muon Flag
Total:
12
5
3
2
1
1
24
USCMS Trigger Meeting, August 2001
Bits / 2 stubs
(MB1: 60° )
24
10
6
4
2
2
48
5
Description
Azimuth coordinate
φ bend angle
Computed by TMB
2 LSB of BXN
DT Special Mode
2nd muon of previous BX
Darin Acosta
SR/SP Outputs
6 track stubs are delivered to DT Track-Finder each BX
(delivered at 40 MHz to transition board)
è
è
Signal
Bits / stub
12
Bits / 2 stubs
(ME1: 20° )
24
Bits / 6 stubs
(ME1: 60° )
72
Bits / 6 stubs
@ 80 MHz
36
φ
η
1
2
6
3
Quality
3
6
18
9
BXN
–
2
6
3
16
34
102
51
Description
Azimuth
coordinate
DT/CSC
region flag
Computed
by TMB
2 LSB of
BXN
Total
3 muons per SP are delivered to Muon Sorter via GTLP backplane
Sent on
first
frame
Signal
Bits / µ
φ
η
Rank *
Sign *
BXN *
Error *
Spare *
Total:
USCMS Trigger Meeting, August 2001
5
5
7
Bits / 3 µ
(1 SP)
15
15
21
Bits / 36 µ
(12 SP)
180
180
252
1
–
–
1
19
3
2
1
3
60
36
24
12
12
720
6
Description
Azimuth coordinate
Pseudorapidity
5 bits pT + 2 bits
quality
2 LSB of BXN
(360 bits at 80 MHz)
Darin Acosta
SR/SP Internal Dataflow
è
ME1
only
Data delivered from SR to SP
Signal
Bits / stub
12
5
6
1
1
Bits / 6 stubs
(ME1)
72
30
36
6
6
Bits / 15 stubs
(ME1–ME4)
180
75
90
15
6
φ
φb
η
Accelerator µ
Front/Rear *
CSC ghost *
–
4
4
Quality
Total:
3
28
18
172
45
415
USCMS Trigger Meeting, August 2001
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Description
Azimuth coordinate
φ bend angle
Pseudorapidity
η bend angle
ME1 chamber
stagger
2 stubs in same
ME1 CSC
Computed by TMB
(sent at 80 MHz)
Darin Acosta
Old SR Memory Scheme
Now in TMB
USCMS Trigger Meeting, August 2001
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Darin Acosta
New SR Memory Scheme
0.5 BX
½ Strip
8
Pattern
4
Quality
3
L/R Bend 1
Muon #
Local
φ LUT
128K× 16
0.5 BX
φlocal 10
10 φlocal
ALCTWG 5
6 φb, local
CSCID
Muon #
1
4
1
φlocal 10
Frame 1
Frame 2
ALCTWG 5
CSCID
Muon #
ALCTWG 7
CSCID 4
φb, local 6
Don’t need “muon #”
if not multiplexing
muons
USCMS Trigger Meeting, August 2001
4
1
9
φlocal
2
Muon #
1
Global
φ LUT
(CSC)
1M×12
12 φCSC
Global
φ LUT
(DT)
1M×12
12 φDT
Global
η LUT
(CSC)
1M×11
6 ηCSC
5 φb,CSC
Darin Acosta
Same
memory
with 24
output
bits
Discussion of SR Memory (1)
Data Frames:
Data arrives off links @ 80 MHz
è The proposed framing scheme implies no latency loss
p First LUT operates on first frame only
(but must reduce CLCT pattern label by 1 bit)
è This frame definition must be applied in the TMB where the
data is generated and first serialized (i.e. before MPC) to avoid
latency penalty
è
Memories:
LUT for DT only applies to ME1
è Chip count is 3 per stub, down from 6 originally
è Increased memory size to 0.5M (okay for synch. SRAM)
è “Muon #” only applies if more than one stub in a BX is sent
through same memory
è
USCMS Trigger Meeting, August 2001
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Darin Acosta
Discussion of SR Memory (2)
One memory set per stub:
è
è
è
15×3 = 45 chips
1 BX latency
415 signals to SP
First SR had 36 chips and 1 BX latency
Memory choices:
è
è
synch SRAM clocked at 160 MHz (tested to this frequency)
Flow Through SRAM clocked at 80 MHz (see PNPI)
USCMS Trigger Meeting, August 2001
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Darin Acosta
SP Memory Scheme
SP
FPGA
∆φ12
∆φ23
8
4
Sign 1
η
4
F/R 1
Mode 4
Muon 1
Rank
LUT
4M×8
Rank1
7
OE
∆φ23 could be
replaced by φ b
Added F/R bit
to improve PT
resolution
∆φ12
∆φ23
8
4
Sign
η
F/R
Mode
1
4
1
4
Muon 2
Rank
LUT
4M×8
Rank2
7
OE
∆φ12
∆φ23
8
4
Sign 1
η
4
F/R 1
Mode 4
Muon 3
Rank
LUT
4M×8
Must serialize to fit data on
backplane
è No latency penalty for
serialization if Rank sent
first to Muon Sorter
è SP FPGA contains tri-state
buffers and generates
enable for memories
è
Rank3 7
OE
Frame 1
Sign1 , Sign2, Sign 3, BXN, Error
φ1 , φ2 , φ3
η1 , η2 , η3
USCMS Trigger Meeting, August 2001
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30
15
GTLP
backplane
80 MHz
Frame 2
15
12
Darin Acosta
SP to Verilog translation
What we said last time:
Will overhaul some of the SP software/firmware to
facilitate changes to both
è
è
Have SW algorithms match Verilog/Schematics better
Have SW read same HW LUTs (it already generates them)
Plan to test next SP design even before construction!
Add utilities to write ORCA data into Xilinx simulator format and
to compare simulator output to ORCA
è Gives us a head start on validating logic design
è Will allow us to focus on HW debugging rather than SW
debugging when testing the next prototype
è
This is now done! Latency: 12 → 5 BX (See Madorsky)
USCMS Trigger Meeting, August 2001
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Darin Acosta
CSC TF DAQ Plans
Send input of SR and output of SP to DAQ stream for
diagnostics
Track-Finder DAQ acts as additional DDU for EMU
system
è
Plan to use existing DDU design by OSU
p OSU has decided to use T.I. Chip for serialization
p 12 SP fiber connections fits well into 15 planned for DDU
p (Don’t even need separate links as ours are bi-directional)
Next step is to have Lev work with OSU (Jason
Gilmore) to learn their design
è
è
è
Check bandwidth and buffer limitations
Understand how to format our data
Design buffers and readout on SR/SP
USCMS Trigger Meeting, August 2001
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Darin Acosta
Mirror CSC DAQ Path
OSU now
plans 20°
slices to
equalize
bandwidth
CSC DDU
designed
by Ohio
State Univ.
15 optical fibers
× 36
Sector
Processors
send L1
data
USCMS Trigger Meeting, August 2001
12 optical fibers
DDU
15
SLINK
Darin Acosta
+ 1 (2?)