I. MOSFET Circuit Models
A. Large Signal Model - NMOS
• Cutoff: (VGS ≤ VTn)-----> ID = 0
• Triode: (VGS ≥ VTn and VDS ≤ VGS - VTn)
I
D
= µ C ( W ⁄ L) V
–V –V
⁄ 2 V  1 + λ V 
n ox
GS
Tn  DS  DS 
n DS 
• CLM term added to ensure continuous curve for ID vs. VDS
• Saturation: (VGS ≥ VTn and VDS ≥ VGS - VTn)
I
2
–V  1+λ V 
= ( 1 ⁄ 2) µ C ( W ⁄ L)  V
D
n ox
Tn  
n DS 
 GS
.
B. Backgate Effect
• The threshold voltage is a function of the bulk-to-source voltage
V Tn = V TOn + γ n  – V BS – 2 φ p – – 2 φ p 
• where VTOn is the threshold voltage with VBS = 0
• γn is the backgate effect parameter
γ n =  2qε s N a  ⁄ C ox
EECS 6.012 Spring 1998
Lecture 10
II. MOSFET Small-Signal Model
A. Small Signal Modelling Concepts
• Find an equivalent circuit which relates the incremental changes in
iD, vGS, vDS, etc.
• Since the changes are small, the small-signal equivalent circuit has
linear elements only (e.g., capacitors, resistors, controlled sources)
• Mathamatically we perform a Taylor expansion around the DC
operating point (also called the quiescent point or Q point) defined
by the DC voltages Q(VGS, VDS, VBS):
• The total drain current in saturation:
iD = (1/2) µn Cox (W/L) (vGS - VTn )2 (1 + λnvDS) = iD(vGS, vDS, vBS)
where vGS = VGS + vgs , iD = ID + id
• We want to find id = (?) vgs
2
∂i D
1∂ iD
( v gs ) + --iD = I D +
∂ v GS
2 2
∂ v GS
Q
2
( v gs ) + …
Q
If the small-signal voltage is really “small,” then we can neglect everything past the
linear term -∂i D
iD = I D +
( v gs ) = I D + g m v gs
∂ v GS
Q
where the partial derivative is defined as the transconductance, gm.
EECS 6.012 Spring 1998
Lecture 10
B. Transconductance
• The small-signal drain current due to vgs is therefore given by
id = gm vgs.
iD = ID + id
D
G
+
+
B
vgs
_
+
_
VDS = 3 V
S
VGS = 3 V_
iD
(µA)
400
ID + id
300
ID
200
id = gmvgs
VGS + vgs
id
Q
100
VGS
VDS
1
2
3
4
5
vDS (V)
EECS 6.012 Spring 1998
Lecture 10
C. Quantifying Transconductance
• Evaluating the partial derivative:
W
g m = µ n C ox  -----  ( V GS – V Tn ) ( 1 + λ n V DS )
L
• We neglect the effect of CLM when calculating the transconductance
so that gm in terms of VGS becomes
W
g m = µ n C ox  -----  ( V GS – V Tn )
L
• In many circuits we want an expression for gm in terms of the DC
drain current
gm =
W
2µ n C ox  -----  I D
L
• For typical values (W/L) = 10, ID = 100 µA, and µnCox = 50 µAV-2
we find that gm = 320 µAV-1 = 0.32 mS
• The circuit which expresses id = gm vgs
id
gate
+
vgs
drain
gmvgs
_ source
EECS 6.012 Spring 1998
Lecture 10
D. Output Conductance
iD
(µA)
400
ID + id
ID
id = govds
id
300
VGS , VBS
Q
200
vds
100
VDS VDS + vds
1
2
3
4
VDS (V)
5
• The change in drain current due to an incremental change in the
drain-source voltage is:
∂i D
2
1
W
g o = ------------ = --- µ n C ox  -----  ( V GS – V T ) λ n ≅ λ n I D
2
L
∂v
DS
Q
• The output resistance is the inverse of the output conductance
1
1
r o = ----- = -----------go
λn I D
• The small-signal circuit model with ro added looks like:
id = gm vgs + (1/ro)vds
gate
drain
+
vgs
_ source
gmvgs
id
ro
+
vds
_
EECS 6.012 Spring 1998
Lecture 10
E. Backgate Transconductance
iD
(µA)
400
ID + id
300
ID
200
VGS , VBS + vbs
id = gmbvbs
id
Q
100
VGS , VBS
VDS
1
2
3
4
VDS (V)
5
• The change in drain current due to an incremental change in the
backgate bias is found using the by the chain rule:
∂i D ∂V Tn
∂i D
g mb = ------------ = ------------ -----------∂V Tn ∂v BS
∂v BS
Q
∂i D
-----------∂V Tn
Q
Q
W
= – µ n C ox  -----  ( V GS – V Tn ) ( 1 + λ n V DS ) ≈ – g m
L
Q
∂V Tn
g mb = ( – g m ) -----------∂v BS
Q
–γ n
γ n gm


= ( – g m )  ------------------------------------  = -----------------------------------2 – 2 φ p – V BS
 2 – 2 φ p – V BS 
.
EECS 6.012 Spring 1998
Lecture 10
E. Backgate Transconductance (con’t)
• The ratio of the backgate transconductance gmb to the “front-gate”
transconductance gm to is:
2qε s N
C b(y=0)
qε s N a
g mb
1
a
--------- = ---------------------------------------------- = --------- --------------------------------------- = -------------------C ox 2 ( – 2 φ p – V BS )
gm
C ox
2C ox – 2 φ p – V BS
• where Cb (y=0) is the depletion capacitance -gate
source
channel
Cb(0)
depletion
region
bulk
F. MOSFET Small Signal Model at Low Frequency
id
gate
drain
+
vgs
_
source _
+
gmvgs
gmbvbs
ro
vds
_
source
vbs
+
bulk
EECS 6.012 Spring 1998
Lecture 10
,,
III. MOSFET Small Signal Model at High Frequency
A. Terminal Capacitances
fringe electric
field lines
gate
drain
,,,
,
,,
,,,
source
n+
n+
Csb
qN (vGS)
depletion
region
Cdb
overlap LD
overlap LD
• Cgs - Overlap capacitanceCov + Channel charge
• Cgd - Overlap capacitanceCov only
• Cgb - Only parasitic since bulk charge does not change
• Cdb - Drain depletion charge
• Csb - Source depletion charge
Cgd
gate
id
+
drain
vgs
Cgs
Cgb
gmvgs
gmbvbs
ro
_ source
_
Csb
vbs
Cdb
+
bulk
EECS 6.012 Spring 1998
Lecture 10
B. Channel Charge
L
q (v ) = – W ∫ C  v
– V – v (y)  dy
N GS
ox  GS
Tn C 
0
• Recalling that current is related to the electric field
 W C ox µ n 
dy =  ----------------------   v
– V – v  dv
Tn C  C
 GS
i


D
 W 2 µ C 2  v GS – V Tn
2

n ox 

q (v ) = –  -------------------------- 
v
–
V
–
v
dv

∫
N GS
GS
Tn C  C
i


D
0
2
q (v ) = – --- WLC  v
–V 
N GS
ox  GS
Tn 
3
• Note bulk Charge is constant with vGS so the channel charge
component of Cgs is given by
q (v ) = – q (v ) – q
G GS
N GS
B, max
• In saturation the drain has no control over the channel charge so only
Cgs has a channel charge component given by
dq
G
-------------dv
GS
2
= --- WLC
ox
3
V
GS
EECS 6.012 Spring 1998
Lecture 10
C. Parasitic Capacitance from Source & Drain Depletion
Regions
• The drain n and p regions have depletion regions whose stored
charge changes during the transient.
• Depletion qJ(vD) is non-linear --> take the worst case and use the
zero-bias capacitance Cjo as a linear charge-storage element during
the transient.
• Perimeter of the drain diffusion is also important and must be
included in the calculation as a capacitance/length x perimeter of
diffusion:
Area of drain diffusion:
gate contact
Adiff = W Ldiff
gate
interconnect
Perimeter of drain diffusion:
P = W + 2 Ldiff
(side next to gate
isn’t counted)
n+ polysilicon gate
source contacts
W
source
interconnect
drain
interconnect
Ldiff
EECS 6.012 Spring 1998
Lecture 10