PROJECT TITLES
1. A new approach to power estimation and reduction in CMOS digital circuits.
2. Reducing parasitic BJT effects in partially depleted SOI digital logic circuits
3. A new approach to power estimation and reduction in CMOS digital circuits
4. Dynamic differential self-timed logic families for robust and low-power security
ICs,
5. Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide
leakage current
6. Low-swing current mode logic (LSCML): A new logic style for secure and robust smart cards
against power analysis attacks
7. High performance low power CMOS dynamic logic for arithmetic circuits (Selected in INTEL
Scholar program 2008)
8. The CMOS Carry-Forward Adders
9. DESIGN OF COMPACT STATIC CMOSCARRY LOOK-AHEAD ADDER USING
RECURSIVE OUTPUT PROPERTY
10. AN IMPROVEMENT FOR DOMINO CMOS LOGIC
11. DESIGN AND IMPLEMENTATION OF A HIGH SPEED LOW POWER 4-BIT FLASH
ADCA Distortion Compensating Flash Analog-to-Digital Conversion Technique
12. A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed
ADCs
13. LOW POWER DATA BUS ENCODING & DECODING SCHEMES Digitally Programmable
Delay Element Design and Analysis
14. Technology and Design Challenges for Low Power and High Performance(Invited Paper)
15. Fast Compact Dynamic Ripple Carry Adder Using DCVS Logic
16. Low Power Arithmetic Circuits in Feed through Dynamic CMOS Logic
17. Fast Feed through Logic: A High Performance Logic Family for GaAs
18. A Compact Gate-Level Energy and Delay Model of Dynamic CMOS Gates
19. Ultrafast Compact 32-bit CMOS Adders in Multiple-Output Domino Logic Multiple output
domino logic (MODL)
20. Testing of Multiple- Output Domino Logic ( MODL) CMOS Circuits
21. High-Performance Microprocessor Design
22. Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic
23. A Novel Multiplexer-Based Low-Power Full Adder
24. A CMOS differential difference operational mirrored amplifier
25. A new high speed and low power four-quadrant CMOS analog multiplier in current mode
26. iCOACH: A circuit optimization aid for CMOS high-performance circuits
27. Detailed study of particle detectors OTA-based CMOS Semi-Gaussian shapers
28. Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects
29. Dynamic low-frequency noise cancellation in quantum well Hall sensors (QWHS)
30. Dynamic noise model and its application to high speed circuit design
31. PMOS NBTI-induced circuit mismatch in advanced technologies
32. Noise in Digital Dynamic CMOS Circuits
33. Dynamic logic is an attractive circuit technique giving reduced area and increased speed for
CMOS circuits.
34. A power efficient and simple scheme for dynamically biasing cascade amplifiers and telescopic
op-amps
35. Energy-recovery flip-flop design using improved adiabatic pseudo-domino logic structure
36. Differential and pass-transistor CMOS logic for high performance systems
37. CMOS regenerative logic circuits
38. On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic.
39. Sleep switch dual threshold voltage domino logic with reduced sub threshold and gate oxide
leakage current
40. Mixed Full Adder topologies for high-performance low-power arithmetic circuits
41. Designing leakage tolerant, low power wide-OR dominos for sub-180 nm CMOS technologies
42. Dynamic noise model and its application to high speed circuit design
43. AN IMPROVEMENT FOR DOMINO CMOS LOGIC
44. 1-out-of-n dynamic CMOS checker
45. A 1.0-GHz 0.18- um 8-bit Carry Look ahead Adder Using PLA-Styled All-N-Transistor Logic
46. A 64-Bit Fast Adder with 0.1 8pm CMOS Technology
47. DFT Technique for low frequency delay fault testing in high performance digital circuit.
48. A HIGH PERFORMANCE LOW POWER DYNAMIC PLA WITH CONDITIONAL
EVALUATION SCHEME
49. High Speed CMOS 64-bit Adder Design
50. A High-Performance Body-Charge-Modulated SO1 Sense Amplifier
51. A High-speed CMOS Incrementer Decrementer
52. A NEW HIGH-SPEEDLOW-POWER DYNAMIC CMOS LOGIC AND ITS APPLICATION
TO THE DESIGN OF AN AOI-TYPE ROM
53. A Novel Approach to Domino Circuit Synthesis
54. A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices
55. A Novel Noise Tolerance Technique
56. Battery-level indicator.
57. 5-BAND GRAPHIC EQUALISER
58. SOLAR LIGHTING SYSTEM
59. Design of Micro Components
60. SMS (From Mobile to PSTN & vice versa)
61. Interactive Rodotic Dim Control using SDK-86
62. Orthogonal Frequency Division Multiplexing System
63. Energy Management
64. Subband Coding for Audio Signal
65. Single Phase Digital Energy Meter
66. Digital Data Transfer through FM
67. Multi-user Detector for CDMA/WLL System
68. Simulation Model of AMBA AHB BUS using VHDL
69. Controlling of Home Appliances over LAN/Internet
70. Mobile Robotics System
71. VHDL Interfacing Temprature Controller Using USB 1.1 Port
72. Remote Monitoring & Control of Instruments through Embedded Web Server
73. DTFM -[Remote Control System]