QDR/DDR SRAM & LLDRAM
Renesas Electronics America Inc.
Waqar Haidari, Computing and Communications BU
Sales Training June 24th ,2010
© 2010 Renesas Electronics America Inc. All rights reserved.
Agenda
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2
Introductions
Overview
Applications
Target customers
QDR Status and Roadmap
QDR Competitive Landscape
LLDRAM Status and Roadmap
LLDRAM Competitive Landscape
Criteria for qualifying opportunities
Collateral
Summary
Call to action
© 2010 Renesas Electronics America Inc. All rights reserved.
Contacts in the C & C BU for Memory
 QDR and LLDRAM – Waqar Haidari
 TCAM – Rob Raghavan
3
© 2010 Renesas Electronics America Inc. All rights reserved.
Overview
 Our product development is mainly focused on the
network equipment market
 QDR and DDR SRAM
 Low Latency DRAM
 TCAM
 Committed to long term support
 Roadmap with advanced technology, higher density
and higher performance products
 Validation activities with NPU & FPGA suppliers
 Confirm interoperability
4
© 2010 Renesas Electronics America Inc. All rights reserved.
SRAM Market Share Rankings - Worldwide
Other
Samsung
17%
NECEL
9%
GSI
10%
26%
CY09
$912M
22%
16%
Renesas Technology
Cypress
Source: Gartner Dataquest Mar. ‘10
5
© 2010 Renesas Electronics America Inc. All rights reserved.
Renesas Memory Solutions for Networking Applications
Memory
Critical Requirement
LLDRAM
eDRAM
Density and Bandwidth
QDR
Random Cycle Time
Look-Up
Table
DDR SRAM
TCAM
LLDRAM
Read Latency
Random Cycle Time
Control
Statistics
Linked List
QDR
Random Cycle Time
and Read Latency
Application
Packet
Buffer
6
© 2010 Renesas Electronics America Inc. All rights reserved.
Other markets/applications
 Test equipment
 Imaging
 Any applications requiring
 High bandwidth
 Fast random access
 Low latency
7
© 2010 Renesas Electronics America Inc. All rights reserved.
Target customers
ACME packets
Alcatel-Lucent
Allied Telesis
Brocade
Ciena
Cisco
Cloudshield
Emulex
Enterasys
Ericsson
Extreme Networks
Force10
Fujitsu
F5 Networks
Hitachi
HP
Huawei
IBM
Ixia
Juniper Networks
Matrox
Motorola BCS
Nokia/Siemens
Nortel Networks/Avaya
Palo Alto Networks
Spirent
Tellabs
* Not doing business at present with customers shown in red
8
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR SRAM Co-Development Team
URL http://www. qdrconsortium.com/
Renesas is a member of QDR Co-Development team
1. Multiple sources
2. Compatible with LA-1 (Look-Aside) interface from NPF
3. Highest bandwidth solution (>2 Gbps @ 533 MHz)
4. Data Valid Window – 65% of clock cycle
5. Package Migration defined through 288 Mb
9
© 2010 Renesas Electronics America Inc. All rights reserved.
2A
QDR Status
 18M
 Current business being supported by 100nm(NEC) die bank
expected to last until March 2011
 55nm die sampling in Sep timeframe
– Transition customers to 55nm die by Q410/Q111
 36M
 90nm (RT) die will continue to be supported
 100nm(NEC) die expected to last until Oct 2010
– 55nm (NEC) die sampling now
– Transition all 36M 100nm customers to 55nm asap
 55nm die to be qualified in all new 36M opportunities
10
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR Status contd.
 72M
 55nm (NEC) die is available now and will continue to be
supported
– QDRII B2 300MHz
– QDRII+ 450MHz
 45nm (RT) die going through re-spin and will be sampling in
Aug/Sep timeframe
– QDRII B2 250MHz
– QDRII+ 533MHz
 Positioning of 72M for new opportunities may depend on several
factors such as
– 72M history with the customer
– Customer qualification window
– Performance requirements
– Cost sensitivity
11
© 2010 Renesas Electronics America Inc. All rights reserved.
72M Power Comparison
Renesas
(NEC) 55nm
Renesas
(RT) 45nm
Cypress
65nm
GSI
(?)
QDRII B2
300MHz
840mA
NA
910mA
NA
QDRII B4
300MHz
650mA
850mA
790mA
950mA
QDRII+
450MHz
925mA
1130mA
1100mA
NA
12
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR/DDR SRAM Validation with NPU/FPGA
Company
NPU / FPGA
Device
Renesas Part Number
Result
AMCC
nP3710
36Mb QDR B4 x36 250MHz
UPD44325184
Pass
Broadcom
BCM56624 & 56634
36Mb DDR B2 x36 250MHz
UPD44324362B
In progress
Marvell
Prestera
18Mb DDR B2 x18 300MHz
UPD44164182A
Pass
Bay Microsystems
Chesapeake
72Mb QDR II+ B4 x36 400MHz
UPD44647366A
Pass
72Mb DDR II+ B2 x36 400MHz
UPD44646363A
Pass
18Mb DDR B2 x36 250MHz
UPD44164362A
Pass
36Mb DDR B2 x36 250MHz
UPD44324362
Pass
Xelerated
PMC Sierra
PM5420 and 5426
72Mb QDR II+ B4 x36 400MHz
UPD44647366A
Pass
Ezchip
NP2
18Mb QDR B2 x9 250MHz
UPD44165092A
Pass
36Mb QDR B2 x18 250MHz
UPD44325182
Pass
18Mb QDR B4x36 300MHz
UPD44165184A
Pass
36Mb QDR B4 x36 250MHz
UPD44325184
Pass
Stratix III
18Mb QDR B4 x36 300MHz
UPD44165184A
Pass
Stratix IV
72Mb QDR II+ B4 x18 400MHz
UPD44647186A
Pass
Altera
13
X11
Stratix II
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR SRAM Roadmap
CY10/1H
CY10/2H
CY11/1H
CY11/2H
45nm
144M
QDR-II+
QDR-II
533MHz
333MHz
250MHz
CY12/1H
CY12/2H
144/288M
800MHz
Next Gen SRAM
45nm
533MHz
QDR-II+ 333MHz
QDR-II 250MHz
72M
55nm
450MHz
QDR-II+300MHz
QDR-II 300MHz
72M
45nm
36M
55nm
36M
QDR-II
300MHz
300MHz
QDR-II+
533MHz
90nm & 100nm
36M
300MHz
QDR-II 250MHz
55nm
18M
100nm
18M
QDR-II
14
QDR-II
300MHz
250MHz
300MHz
300MHz
: MP
© 2010 Renesas Electronics America Inc. All rights reserved.
: Under development
: Planning
QDR Competitive Landscape
 Samsung




Historically a major player but no new SRAM development
Supporting existing products based on ~90nm
Customers concerned about EOL
No 72M QDRII+/DDRII+
 Cypress
 65nm 72M available
 Claim to have 72M QDRII+ 500MHz in production
 Customers continue to experience supply shortages on 36M and 72M
 GSI




Offer 18M compatible to QDRII+
Sampling 144M now - QDRII b2-250MHz, b4-333MHz and QDRII+ 450MHz
72M 65nm expected soon - 550MHz
Promoting Sigma Quad IIIe - b4(625MHz) and b2(500MHz) but customers may be
reluctant to go sole sourced
 ISSI
 No 18M QDR compatible offering
 72M sampling but no ODT
 No performance advantage over Renesas in any density
15
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR Competitive Landscape contd.
 Renesas
 Strength:
– 55nm die should help grow 18M and 36M QDRII business
– Two 72M solutions (55nm and 45nm) give us more flexibility
in capturing 72M QDRII/QDRII+ design-wins
– 55nm has lower power consumption than Cypress
– excellent SER and SEL test results
– I-temp support available on all 45nm products
 Weakness:
– No 18M QDRII+ offering
– Late in 36M QDRII+ and 144M
16
© 2010 Renesas Electronics America Inc. All rights reserved.
Low Latency DRAM
LLDRAM has a DRAM core and a SRAM like interface
tRC Performance
QDR II
18Mb~144Mb
tRC=4.8~7.5ns
LLDRAM
288~576Mb
tRC=~20ns
DDR2/3
DRAM
256Mb~2Gb
tRC= ~40ns
Cost
• QDR is better in applications that require fast random access
• LLDRAM is better suited where density is a higher priority
17
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Advantages
 Better tRC than Commodity DRAM (Cycle Time or Random
Access Time)
 Lower cost per bit compared to SRAM
 ECC (parity) Bit for Higher System Security
 Some system need parity bit for ECC correction.
– Standard DRAM : No parity bit (x8, x16 and x32)
– LLDRAM: Has parity bit (x9, x18 and x36)
 288M and 576M LLDRAM offer an alternate source to
customers that are sole sourced with Micron RLDRAM II
18
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Status
 288M LLDRAM in mass production
 Cisco and Juniper are the main customers
 Trying to expand customer base
– Alcatel, Extreme Networks, ACME packets, Ciena
 576M LLDRAM expected in Q410
 Cisco, Juniper, Alcatel, Brocade and others anxious to have a
second source
 1.1G LLDRAM III
 Developed based on spec from Cisco
 First ES will be delivered to Cisco within June
– General availability TBD
– No restriction on selling to other customers
 Cisco had chosen GSI to second source but GSI apparently had
some issues and their status is now unclear
19
© 2010 Renesas Electronics America Inc. All rights reserved.
288M LLDRAM Line up
I/O
Bit
Config.
Part Number
SIO
16M x 18
uPD48288118FF-EFxx-DW1/-A
32M x 9
uPD48288209FF-EFxx-DW1/-A
16M x 18
uPD48288218FF-EFxx-DW1/-A
8M x 36
uPD48288236FF-EFxx-DW1/-A
16M x 18
uPD48288118FF-Exx-DW1/-A
32M x 9
uPD48288209FF-Exx-DW1/-A
16M x 18
uPD48288218FF-Exx-DW1/-A
8M x 36
uPD48288236FF-Exx-DW1/-A
CIO
SIO
CIO
20
© 2010 Renesas Electronics America Inc. All rights reserved.
Vext
[V]
2.5
+0.13/
-0.12
VDD
[V]
VDDQ
[V]
Max.
Freq.
[MHz]
1.5
+/0.1
1.8
+/0.1
Schedule
ES
CS
MP
400
300
200
Now
Now
Now
300
200
Now
Now
Now
1.8
+/0.1
288M LLDRAM Validation
Network Processors
Vendor
Processor
Validation status
EZChip
NP2
Complete
Xelerated
X11
Complete
AAP650
Complete
Chesapeake
Complete
Chipset
Validation status
DDP 3020 & 3021
Complete
LSI
Bay Micro
Visual Media
Vendor
Texas
Instruments
21
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Roadmap
CY10/1H
CY10/2H
CY11/1H
CY11/2H
CY12/1H
CY12/2H
Not RLDRAM-II Compatible
40nm
Low Latency
DRAM III
x18/x36
1.1G 800MHz
RLDRAM-II Compatible
T.B.D
70nm
Low Latency
DRAM
x9/x18/x36
1.1G 533MHz
Low Latency
DRAM
x9/x18/x36
576M 533MHz
70nm
90nm
Low Latency
DRAM
x9/x18/x36
288M 533MHz
Vddq=1.5V
Low Latency
DRAM
x9/x18/x36
288M 400MHz
90nm
Vddq=1.8V
Low Latency
DRAM
x9/x18/x36
288M 400MHz
: MP
22
© 2010 Renesas Electronics America Inc. All rights reserved.
: under Development
: Planning
LLDRAM Competitive Landscape
 Micron is the only competitor at the present time
 Micron 288M and 576M RLDRAM II in mass production
 Micron RLDRAM III spec not open to the public
 GSI was developing 576M RLDRAM II compatible product
and was chosen by Cisco to second source 1.1G LLDRAM III
but has apparently had some issues and their status is
unclear
 ISSI is proposing a 576M Network DRAM solution to Cisco
but Cisco is not interested
 Renesas is well positioned for growth in the LLDRAM area
23
© 2010 Renesas Electronics America Inc. All rights reserved.
Criteria for qualifying new opportunities
 No minimum volume requirements for QDR or LLDRAM
 Opportunities in Medical or Military applications may require
details on the application and end product
24
© 2010 Renesas Electronics America Inc. All rights reserved.
Collateral
 For QDR and LLDRAM datasheets not posted on the web and
simulation models email Waqar.Haidari@renesas.com or call
(408) 588-6354
 Low Latency DRAM Design Guide
http://america2.renesas.com/memory/products/ld/ll-info.html
25
© 2010 Renesas Electronics America Inc. All rights reserved.
Summary
 We are unique in that we are the only supplier that offers
QDR/LLDRAM/TCAM
 We have extensive experience in delivering high quality, high
volume QDR/LLDRAM production support
 Our products are very competitive in price and performance
 Samsung’s potential exit from the SRAM market presents
tremendous opportunities for Renesas
26
© 2010 Renesas Electronics America Inc. All rights reserved.
Call to action
 We need more design-wins. Please follow up on any pending
QDR/LLDRAM qualifications
 Promote 36M 55nm in all new 36M opportunities
 Find new 72M opportunities and we’ll recommend the right
72M solution that best fits the opportunity
 Many customers are still sole sourced with Micron RLDRAMII.
Highlight the risk of being sole sourced and motivate them
to qualify Renesas LLDRAM. For 288M check I/O voltage
 Let’s work together and develop account penetration plan for
customers that we are not currently engaged with
27
© 2010 Renesas Electronics America Inc. All rights reserved.
Appendix
28
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR II vs. QDR II+ Feature differences
QDRII+
QDRII
Max.Freq.
I/O,Data Rate,
Interface
K,/K
C,/C
(6P,6R)
Burst Length
B2
Write Latency
0
Q driver strength
B4
1
2
1.5
2.5
ZQ-pin calibration 35ohm to 70 ohms
Q valid indicator
QVLD-pin (6P)
Input Termination
ODT Control
Package
29
In case of single clock mode,
K,/K is used for output
CQ,/CQ
Echo Clock
Read Latency
533Mhz
Separate, DDR,HSTL
Input Clocks
Output Clocks
400Mhz
250Mhz 300Mhz
© 2010 Renesas Electronics America Inc. All rights reserved.
165BGA
(6R)
288M LLDRAM Features
Design Rule
Density
Bit Organization
I/O
Burst Length
Bank Size
Vcc
Vddq
Vext
Max Frequency
Min tRC/tRL
Refresh Rate
Package
Status
30
:
:
:
:
90nm DRAM Process
288Mb
x9/x18/x36
Common I/O for x9/x18/x36
Separate I/O for x18 only
: 2/4/8 for x9/x18
2/4 for x36
:8
: 1.8V
: 1.5V or 1.8V
: 2.5V
: 400MHz (for 1.5V Vccq)
: 300MHz (for 1.8V Vccq)
: 20ns
: 32ms @8kword, 8bank (0.49us/1bank)
: 144pin uBGA
: MP
© 2010 Renesas Electronics America Inc. All rights reserved.
576M LLDRAM Features
Design Rule
Density
Bit Organization
I/O
Burst Length
Bank Size
Vcc
Vddq
Vext
Max Frequency
Min tRC/tRL
Refresh Rate
Package
Status
31
:
:
:
:
70nm DRAM Process
576Mb
x9/x18/x36
Common I/O for x9/x18/x36
Separate I/O for x9/x18
: 2/4/8 for x9/x18/x36
:8
: 1.8V
: 1.5V or 1.8V
: 2.5V
: 533MHz
: 15ns
: 32ms @16kword, 8bank
(0.49us/1bank)
: 144pin uBGA
ES: Dec.'10, CS: Q1CY11,
Q2CY11
© 2010 Renesas Electronics America Inc. All rights reserved.
MP:
1.1G LLDRAM III Features
 Frequency : 800MHz@BL4 , 600MHz@BL2
 Organization
 x36 or x18
 Common I/O
 8 Banks
 Burst Length : 2 or 4
 Latency
 tRC=13.75ns@BL4 , 13.3ns@BL2
 tRL=tRC+3 @BL4 , tRC+2 @BL2
 tWL=tRL+1
 Training Sequence for per-bit deskew
 External Refresh : 2ms data retention time
 Supply Voltage
 Vdd (Core)=1.5V , Vddq (I/O)=1.0V HSIO, Vext=2.5V
 Vref : 0.7*VDDQ
 PKG : 180 pin BGA (14x18.5, 1.0mm x 1.0mm ball pitch)
32
© 2010 Renesas Electronics America Inc. All rights reserved.
Future products under consideration
 QDR-III
 144Mb ~ 288Mb
 800MHz+
 LLDRAM-IV
 1.1Gb ~ 2.2Gb
 1.6GHz / 3.2Gbps
 CAM-V
 80Mb ~ 160Mb
 600Msps+
 Serial Interface Memory
 1.1Gb ~ 2.2Gb (1T) / 144Mb ~ 288Mb (6T)
 3.2GAps+ (16 x 10G Serial)
33
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Part Number Guide
uPD48288236FF-EF18-DW1-A
Density
288 : 288Mb
576 : 576Mb
Package
Package Size
Lead Free
FF : uBGA
DW1: 11x18.5mm
(none) : Pb
(RoHS5/6)
A : Pb Free
(RoHS6/6)
I/O
VDDQ
1 : SIO
2 : CIO
E : 1.8V
EF : 1.5V
Speed Grade
Bit Configuration
09 : x9 bit
18 : x18 bit
36 : x36 bit
34
Die Revision
(none) : 1st die
A : A-die (Shrink)
© 2010 Renesas Electronics America Inc. All rights reserved.
18 : 533MHz
24 : 400MHz (tRC=15ns)
25 : 400MHz
33 : 300MHz
50 : 200MHz
QDR/DDR-II Part Number Guide
100nm/55nm
uPD44645182AF5-E40-FQ1-A
Density
16 : 18Mb
32 : 36Mb
64 : 72Mb
Function
4 : DDR-II
5 : QDR-II
Bit Configuration
08 : x8 bit
09 : x9 bit
18 : x18 bit
36 : x36 bit
35
Package
F5 : BGA
Package
Size
EQ2/3:13x15mm
FQ1:15x17mm
Lead Free
(none) : Pb
(RoHS5/6)
A : Pb Free
(RoHS6/6)
Die Revision
(none) : 1st die
A : A-die (Shrink)
B : B-die (2nd Shrink)
Burst Length
Speed Grade
2 : 2B
4 : 4B
5 : 2B (DDRII SIO)
E33 : 300MHz
E40 : 250MHz
E50 : 200MHz
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR/DDR-II+ Part Number Guide (RL=2.5)
100nm/55nm
uPD44647186AF5-E22-FQ1-A
Density
16 : 18Mb
32 : 36Mb
64 : 72Mb
Function
6 : DDR-II+
7 : QDR-II+
Bit Configuration
09 : x9 bit
18 : x18 bit
36 : x36 bit
36
Package
F5 : BGA
Package
Size
EQ2:13x15mm
FQ1:15x17mm
Lead Free
(none) : Pb
(RoHS5/6)
-A : Pb Free
(RoHS6/6)
Die Revision
(none) : 1st die
A : A-die (Shrink)
B : B-die (2nd Shrink)
Burst Length
(RL=2.5)
3 : 2B
6 : 4B
7 : 2B (DDRII+ SIO)
© 2010 Renesas Electronics America Inc. All rights reserved.
Speed Grade
E22 : 450MHz
E25 : 400MHz
E30 : 333MHz
E33 : 300MHz
QDR/DDR-II Part Number Guide
Lead Free
90nm/45nm
R1Q2A7218ABG-40IA0
Function
2:
3:
4:
5:
6:
QDR-II 2B
QDR-II 4B
DDR-II 2B
DDR-II 4B
DDR-II 2B (SIO)
Core Voltage
Package
BG : BGA
(15x17mm)
36 : 36Mb
72 : 72Mb
37
For 72M
A0 : Pb
(RoHS5/6)
B0 : Pb Free
(RoHS6/6)
Temp. Range
Die Revision
A : 1.8V
Density
For 36Mb
(None) : Pb
(RoHS5/6)
B0 : Pb Free
(RoHS6/6)
Bit Configuration
09 : x9 bit
18 : x18 bit
36 : x36 bit
© 2010 Renesas Electronics America Inc. All rights reserved.
R : 0 to 70 deg.C
I : -40 to 85 deg.C
Speed Grade
30 : 333MHz
33 : 300MHz
40 : 250MHz
50 : 200MHz
QDR/DDR-II+ Part Number Guide (RL=2.5)
Lead Free
90nm/45nm
R1QAA7218ABG-22IA0
Function
(RL=2.5)
A:
B:
C:
D:
E:
F:
QDR-II+ 4B
DDR-II+ 2B
DDR-II+ 4B
QDR-II+ 4B ODT
DDR-II+ 2B ODT
DDR-II+ 4B ODT
Core Voltage
Package
BG : BGA
(15x17mm)
For 36Mb
(None) : Pb
(RoHS5/6)
B0 : Pb Free
(RoHS6/6)
For 72M
A0 : Pb
(RoHS5/6)
B0 : Pb Free
(RoHS6/6)
Temp. Range
Die Revision
R : 0 to 70 deg.C
I : -40 to 85 deg.C
A : 1.8V
Density
36 : 36Mb
72 : 72Mb
38
Speed Grade
Bit Configuration
18 : x18 bit
36 : x36 bit
© 2010 Renesas Electronics America Inc. All rights reserved.
19 : 533MHz
20 : 500MHz
22 : 450MHz
Renesas Electronics America Inc.
© 2010 Renesas Electronics America Inc. All rights reserved.