QDR SRAM, LLDRAM and TCAM Products
Renesas Electronics America Inc.
Computing and Communications BU
FAE Training - June 2010
© 2010 Renesas Electronics America Inc. All rights reserved.
What will I learn from this?
 Renesas is now the 364kg gorilla of networking memory
solutions
 Who is our competition and what are our
strengths/weaknesses
 What is a TCAM and how is it different from a Tparty
 TCAM has an unknown state, Tparty has Kentucky
 Who uses our memory and why
 Why reps who sell memory drive BMWs
2
© 2010 Renesas Electronics America Inc. All rights reserved.
Router functions
Packet Forwarding
Shallow Packet Inspection (SPI)
Extracts basic protocol information such
as IP addresses (source, destination)
3
© 2010 Renesas Electronics America Inc. All rights reserved.
Packet Classification
Deep Packet Inspection (DPI)
The process of categorizing packets into
“flows” in an internet router is called
packet classification
So, why is this important?
 Suppose you want to classify a packet based on an 80 bit
long field (TCAMs have up to 640 bit search fields)
 There are two methods, hardware and software
 Software can work for low speed networks, but what
happens when you have a 10Gbps linecard feed?
 You need hugely parallel processing to maintain the line speed
 You need really big buffers to hold the data while the processing
is done
 Hardware could use a lookup memory table, but how big
does it need to be for an 80 bit address field?
 one million billion billion bits
– roughly the amount of oil BP has leaked in the gulf
 Or, make the 80 bits the data and the memory responds
with the address (really a pointer)
4
© 2010 Renesas Electronics America Inc. All rights reserved.
TCAM Description
 CAM stands for Content Addressable Memory
 With a CAM, the operating system supplies the data, and the CAM returns a
list of addresses where the data is stored, if it finds any
 A CAM searches the entire memory in one cycle, so it is considerably faster
than RAM
 A TCAM is a Ternary CAM. This allows the operating system to match a
third state, "X.“
5
© 2010 Renesas Electronics America Inc. All rights reserved.
Packet Classification Search
All packets belonging to the same
flow obey a pre-defined rule and are
processed in a similar manner by the
router.
TCAM
3 (Pointer)
Associative
Data
QDR SRAM
QoS, QoE, ACL, SLA
(Ingress)
Header
Payload
trailer
1
Network
Processor
(NPU)
Header
Payload
trailer
NSE
4 (Next Switch Address, QoS, QoE, ACL, SLA)
(Egress)
Priority
Header
Payload
Packet filtering
Policy routing
Accounting & billing
Traffic rate limiting
Traffic shaping
Intrusion detection
6
trailer
2
Quality of Service
QoS provides preferential
delivery service for the
applications that need it by
ensuring sufficient bandwidth
Header
Payload
trailer
Packet classification is needed for
services that require the capability to
distinguish and isolate traffic in different
flows for suitable processing.
© 2010 Renesas Electronics America Inc. All rights reserved.
Access Control List
An ACL is a common means by
which access to and denial of
services is controlled
Renesas Memory Solutions for Networking Applications
Memory
Critical Requirement
LLDRAM
eDRAM
Density and Bandwidth
QDR
Random Cycle Time
Look-Up
Table
DDR SRAM
TCAM
LLDRAM
Read Latency
Random Cycle Time
Control
Statistics
Linked List
QDR
Random Cycle Time
and Read Latency
Application
Packet
Buffer
7
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR SRAM Roadmap
CY10/1H
CY10/2H
CY11/1H
CY11/2H
45nm
144M
QDR-II+
QDR-II
533MHz
333MHz
250MHz
CY12/1H
CY12/2H
144/288M
800MHz
Next Gen SRAM
45nm
533MHz
QDR-II+ 333MHz
QDR-II 250MHz
72M
55nm
450MHz
QDR-II+300MHz
QDR-II 300MHz
72M
45nm
36M
55nm
36M
QDR-II
300MHz
300MHz
QDR-II+
533MHz
90nm & 100nm
36M
300MHz
QDR-II 250MHz
55nm
18M
100nm
18M
QDR-II
8
QDR-II
300MHz
250MHz
300MHz
300MHz
: MP
© 2010 Renesas Electronics America Inc. All rights reserved.
: Under development
: Planning
Renesas QDR Status
 18M
 Current business being supported by 100nm(NEC) die bank
expected to last until March 2011
 55nm die sampling in Q310
– Targeting to transition customers to 55nm die by
Q410/Q111
 36M
 90nm (RT) die will continue to be supported
 100nm(NEC) die expected to last until Oct 2010
– 55nm (NEC) die sampling now
– Targeting to transition all 36M 100nm customers to 55nm
asap
 55nm die to be qualified in all new 36M opportunities
9
© 2010 Renesas Electronics America Inc. All rights reserved.
Renesas QDR Status contd.
 72M
 55nm(NEC) die will continue to be supported
 45nm (RT) die will be sampling in Q310
 Positioning of 72M for new opportunities may depend on several
factors such as
– 72M history with the customer
– Customer qualification window
– Performance requirements
– Cost sensitivity
10
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR Competitive Landscape
 Samsung




Historically a major player but no new SRAM development
Supporting existing products based on ~90nm
Customers concerned about EOL
No 72M QDRII+/DDRII+
 Cypress
 65nm 72M available, availability of lower densities based on 65nm unclear
 Claim to have 72M QDRII+ 500MHz in production
 Customers have recently reported supply shortages on 36M and 72M
 GSI




Offer 18M compatible to QDRII+
Sampling 144M now - QDRII b2-250MHz, b4-333MHz and QDRII+ 450MHz
72M 65nm expected soon - 550MHz
Promoting Sigma Quad IIIe - b4(625MHz) and b2(500MHz) but customers may be
reluctant to go sole sourced
 ISSI
 No 18M QDR compatible offering
 72M sampling but no ODT
 No performance advantage over Renesas in any density
11
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR Competitive Landscape contd.
 Renesas
 Strength:
– 55nm die should help grow 18M and 36M QDRII business
– Two 72M solutions (55nm and 45nm) will give us more
flexibility in capturing 72M QDRII/QDRII+ design-wins
 Weakness:
– No 18M QDRII+ offering
– Late in 36M QDRII+ and 144M
12
© 2010 Renesas Electronics America Inc. All rights reserved.
QDR II vs. QDR II+ Feature differences
QDRII+
QDRII
Max.Freq.
I/O,Data Rate,
Interface
K,/K
C,/C
(6P,6R)
Burst Length
B2
Write Latency
0
Q driver strength
B4
1
2
1.5
2.5
ZQ-pin calibration 35ohm to 70 ohms
Q valid indicator
QVLD-pin (6P)
Input Termination
ODT Control
Package
13
In case of single clock mode,
K,/K is used for output
CQ,/CQ
Echo Clock
Read Latency
533Mhz
Separate, DDR,HSTL
Input Clocks
Output Clocks
400Mhz
250Mhz 300Mhz
© 2010 Renesas Electronics America Inc. All rights reserved.
165BGA
(6R)
QDR SRAM Co-Development Team
URL http://www. qdrconsortium.com/
Renesas is a member of QDR Co-Development team
1. Multiple sources
2. Compatible with LA-1 (Look-Aside) interface from NPF
3. Highest bandwidth solution (>2 Gbps @ 533 MHz)
4. Data Valid Window – 65% of clock cycle
5. Package Migration defined through 288 Mb
14
© 2010 Renesas Electronics America Inc. All rights reserved.
2A
QDR/DDR SRAM Validation with NPU/FPGA
Company
NPU / FPGA
Device
NEC Part Number
Result
AMCC
nP3710
36Mb QDR B4 x36 250MHz
UPD44325184
Pass
Broadcom
BCM56624 & 56634
36Mb DDR B2 x36 250MHz
UPD44324362B
In progress
Marvell
Prestera
18Mb DDR B2 x18 300MHz
UPD44164182A
Pass
Bay Microsystems
Chesapeake
72Mb QDR II+ B4 x36 400MHz
UPD44647366A
Pass
72Mb DDR II+ B2 x36 400MHz
UPD44646363A
Pass
18Mb DDR B2 x36 250MHz
UPD44164362A
Pass
36Mb DDR B2 x36 250MHz
UPD44324362
Pass
Xelerated
PMC Sierra
PM5420 and 5426
72Mb QDR II+ B4 x36 400MHz
UPD44647366A
Pass
Ezchip
NP2
18Mb QDR B2 x9 250MHz
UPD44165092A
Pass
36Mb QDR B2 x18 250MHz
UPD44325182
Pass
72Mb QDR II+ B4 x36 400MHz
UPD44647366A
In progress
72Mb QDR II+ B4 x18 400MHz
UPD44647186A
In progress
18Mb QDR B4x36 300MHz
UPD44165184A
Pass
36Mb QDR B4 x36 250MHz
UPD44325184
Pass
Stratix III
18Mb QDR B4 x36 300MHz
UPD44165184A
Pass
Stratix IV
72Mb QDR II+ B4 x18 400MHz
UPD44647186A
Pass
Xilinx
Altera
15
X11
Virtex 6
Stratix II
© 2010 Renesas Electronics America Inc. All rights reserved.
Well that’s really interesting. Is there anything else I
should know?
 Glad you asked
 SER and SEL are two common and growing concerns with
system designers
 SER is Soft Error Rate, where a sub atomic particle impacts
with the memory cell and changes its charge
 The error can be fixed with ECC or on the next write cycle
 SEL is Soft Error Latchup, but it’s a bit more nasty.
Essentially, one of the transistors gets turned into an SCR,
once again by a sub atomic particle impact.
 Memory bit stays in the disturbed state until the board is
powered completely off.
16
© 2010 Renesas Electronics America Inc. All rights reserved.
In the old days, SER was caused by alpha particles released from the moulding
compound, which was contaminated with residual atmospheric radioactivity.
17
© 2010 Renesas Electronics America Inc. All rights reserved.
Now, the dominant cause is cosmic radiation.
18
© 2010 Renesas Electronics America Inc. All rights reserved.
Actually, solar radiation from the sun. It can be very damaging.
19
© 2010 Renesas Electronics America Inc. All rights reserved.
But Renesas devices are designed to be resistant to these effects
Technical note:
For 55nm 72M QDR
SEL results are: 0 FIT/Mbit ( Ta = 25'C)
0 FIT / Mbit (Tc = 125 'C)
20
© 2010 Renesas Electronics America Inc. All rights reserved.
Low Latency DRAM
LLDRAM has a DRAM core and a SRAM like interface
tRC Performance
QDR II
18Mb~144Mb
tRC=4.8~7.5ns
LLDRAM
288~576Mb
tRC=~20ns
DDR2/3
DRAM
256Mb~1Gb
tRC= ~40ns
Cost
• QDR is better for applications that require fast random access
• LLDRAM is better suited where density is a higher priority
21
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Advantages
 Better tRC than Commodity DRAM (Cycle Time or Random
Access Time)
 SRAM >> LLDRAM >> Commodity DRAM
 Lower cost per bit compared to SRAM
 Systems keep requiring larger density for higher performance
 Standard DRAM >> LLDRAM >> SRAM
 ECC (parity) Bit for Higher System Security
 Some system need parity bit for ECC correction.
– Standard DRAM : No parity bit (x8, x16 and x32)
– LLDRAM & SRAM: Support parity bit (x9, x18 and x36)
22
© 2010 Renesas Electronics America Inc. All rights reserved.
Renesas LLDRAM Status
 288M LLDRAM in mass production
 Cisco and Juniper are the main customers
 Trying to expand customer base
– Alcatel, Extreme Networks, ACME packets, Ciena
 576M LLDRAM expected in Q410
 Cisco, Juniper, Alcatel, Brocade and others anxious to have a
second source
 1.1G LLDRAM III
 Developed based on spec from Cisco
 First ES will be delivered to Cisco within June
– General availability TBD
– No restriction on selling to other customers
 Cisco had chosen GSI to second source but GSI apparently had
some issues and their status is now unclear
23
© 2010 Renesas Electronics America Inc. All rights reserved.
288M LLDRAM Validation
Network Processors
Vendor
Processor
Validation status
EZChip
NP2
Complete
Xelerated
X11
Complete
AAP650
Complete
Chesapeake
Complete
Chipset
Validation status
DDP 3020 & 3021
Complete
LSI
Bay Micro
Visual Media
Vendor
Texas
Instruments
24
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Roadmap
CY10/1H
CY10/2H
CY11/1H
CY11/2H
CY12/1H
CY12/2H
Not RLDRAM-II Compatible
40nm
Low Latency
DRAM III
x18/x36
1.1G 800MHz
RLDRAM-II Compatible
T.B.D
70nm
Low Latency
DRAM
x9/x18/x36
1.1G 533MHz
Low Latency
DRAM
x9/x18/x36
576M 533MHz
70nm
90nm
Low Latency
DRAM
x9/x18/x36
288M 533MHz
Vddq=1.5V
Low Latency
DRAM
x9/x18/x36
288M 400MHz
90nm
Vddq=1.8V
Low Latency
DRAM
x9/x18/x36
288M 400MHz
: MP
25
© 2010 Renesas Electronics America Inc. All rights reserved.
: under Development
: Planning
1.1G LLDRAM III
 Frequency : 800MHz@BL4 , 600MHz@BL2
 Organization
 x36 or x18
 Common I/O
 8 Banks
 Burst Length : 2 or 4
 Latency
 tRC=13.75ns@BL4 , 13.3ns@BL2
 tRL=tRC+3 @BL4 , tRC+2 @BL2
 tWL=tRL+1
 Training Sequence for per-bit deskew
 External Refresh : 2ms data retention time
 Supply Voltage
 Vdd (Core)=1.5V , Vddq (I/O)=1.0V HSIO, Vext=2.5V
 Vref : 0.7*VDDQ
 PKG : 180 pin BGA (14x18.5, 1.0mm x 1.0mm ball pitch)
26
© 2010 Renesas Electronics America Inc. All rights reserved.
LLDRAM Competitive Landscape
 Micron is the only competitor at the present time
 Micron 288M and 576M RLDRAM II in mass production
 Micron RLDRAM III spec not open to the public
 GSI was developing 576M RLDRAM II compatible product
and was chosen by Cisco to second source 1.1G LLDRAM III
but has apparently had some issues and their status is
unclear
 ISSI is proposing a 576M Network DRAM solution to Cisco
but Cisco is not interested
 Renesas is well positioned for growth in the LLDRAM area
27
© 2010 Renesas Electronics America Inc. All rights reserved.
Target customers for QDR and LLDRAM
ACME packets
Alcatel-Lucent
Allied Telesis
Avici Systems
Breakingpoint
Brocade
Ciena
Cisco
Cloudshield
Emulex
Enterasys
Ericsson
Extreme Networks
Force10
Fujitsu
F5 Networks
Hitachi
HP
Huawei
IBM
Ixia
Juniper Networks
Matrox
Motorola BCS
Nokia/Siemens
Nortel Networks/Avaya
Palo Alto Networks
Spirent
Tellabs
28
© 2010 Renesas Electronics America Inc. All rights reserved.
Collateral
Former NEC QDR and LLDRAM
 Datasheets are on the web
 For any datasheets not posted on the web
 Contact Waqar Haidari
 Simulation Models
Contact Waqar Haidari at Waqar.Haidari@renesas.com or
(408) 588-6354
 Low Latency DRAM Design Guide
http://america2.renesas.com/memory/products/ld/ll-info.html
Former RT QDR
 Contact Rob.Raghavan@renesas.com or (408) 382-7306
29
© 2010 Renesas Electronics America Inc. All rights reserved.
Contacts in the C & C BU for QDR/LLDRAM
Contacts for former NEC QDR and LLDRAM products:
 Marketing contact – Waqar Haidari
 Technical contact for Cisco – Yasuhiro Saruwatari
 Technical contact for other accounts – Sungjin Han
Contact for former RT QDR products:
 Rob Raghavan
30
© 2010 Renesas Electronics America Inc. All rights reserved.
TCAM Roadmap
~ CY09
CY10/1H
ASSP
20M
576 FCBGA
360Msps
CY10/2H
ASSP
18M
ASSP
CY11/1H
360 FCBGA
125Msps
360 PBGA
125Msps
CY11/2H
ASSP
80M
ASSP
40M
4.5M
ASSP CAM
ASSP
5M
Interlaken
600Msps
Interlaken
600Msps
Interlaken
600Msps
Custom
Custom
Custom
Custom
Custom TCAM
Gen 2 –18M
Custom TCAM
Gen 3 –18M
Custom TCAM
Gen 4 –20M
Custom TCAM
Gen 5 –80M
Custom
Custom
Custom
Custom
Custom TCAM
Gen 2 – 4.5M
Custom TCAM
Gen 3 – 4.5M
Custom TCAM
Gen 4 – 10M
Custom TCAM
Gen 5 – 40M
Custom
Custom
Custom
Custom
Custom TCAM
Gen 2– 2.5M
Custom TCAM
Gen 3 – 2.5M
Custom TCAM
Gen 4 – 5M
Custom TCAM
Gen 5– 5M
Custom CAM
31
CY12/1H
© 2010 Renesas Electronics America Inc. All rights reserved.
CY12/2H
Renesas TCAM Portfolio
Quad Search TCAM
Dual Search TCAM
Dual Search TCAM
R8A20410BG
TBD
TBD
20M
4.5M
18M
Parallel Search Engines
4 banks
2 banks
2 banks
Clock Frequency
360MHz
250MHz
250MHz
40b/80/160/320/480/640
72/ 144/ 288
72/ 144/ 288
Search Rate
360Msps @ Single
720Msps @ Quad
125Msps @ Single
250Msps @ Dual
125Msps @ single
250Msps @ dual
Core Voltage
1.0V+/- 5%
1.0V+/- 5%
1.0V+/- 5%
I/O Voltage
1.5V +/- 5% (HSTL)
2.5V +/- 5% (SSTL2)
2.5V +/- 5% (SSTL2)
Data Bus
80bit (DDR)
72bit (SDR)
72bit (SDR)
Package
576pins FCBGA
360pins PBGA
360pins FCBGA
Datasheet
Now
July
July
Models
Now
August
August
Sample
Now
October
November
August
Q1 2011
Q1 2011
Part number
Density
Search Mode (bit width)
Production
32
© 2010 Renesas Electronics America Inc. All rights reserved.
Quad Search Features Overview
33
© 2010 Renesas Electronics America Inc. All rights reserved.
Quad Search TCAM Block Diagram
WDS[0]/WDS#[0]
P_THRU
F_SEL
PLL
CAM_CLK
TMS
JTAG
Search Key Configuration
PARITY
CONTROLLER
Block31
Block30
OP/TERS[3:0]
Context Register
(80bits X 4)
WDS[2:0]/
WDS#[2:0]
D[79:0]
DP[1:0]
Priority
Encoder
For table A
Block2
Block1
Block0
PARITY_ERR
RDS/RDS#
IND[19:0]
MAT
Search Mask
Priority
Encoder
For table B
CAM Array
Priority
Encoder
For table C
Search Key
Device
Register
TCK
TDI
TDO
TRST
O_VD
Priority
Encoder
For table D
C_SEL
OP_ENA
Write Mask
Write Data
Cascade
RSTL
34
© 2010 Renesas Electronics America Inc. All rights reserved.
CI_RDS/RDS#
CI_IND[19:0]
CI_MAT
CI_O_VD
Cascaded System
Input Side
WDS/WDS#, OP_ENA, OP, D, DP, CR_SEL, KS, KS_ENA, LAST_KS
CI_RDS/
CI_RDS#
RDS/
RDS#
IND
CI_IND
ASIC/NPU
or
FPGA
CI_RDS/
CI_RDS#
RDS/
RDS#
IND
CI_IND
CI_O_VD
O_VD
CI_O_VD
O_VD
CI_MAT
MAT
CI_MAT
MAT
0
ID
1
ID
1
OALIGN
0
OALIGN
CAM-0
Higher priority CAM
CAM-1
Lower priority CAM
Output Side
35
© 2010 Renesas Electronics America Inc. All rights reserved.
Questions for Customers
 What is their application?
 What density is required? (e.g. 20Mbit table size)
 What performance is required? (MSPS – million searches per
second)
 What is the search key width?
 What is the I/O frequency / Type (e.g. 360MHz, 1.5V HSTL)
 What is the design power budget?
 Are they willing to cascade devices for increased density?
 Are they currently using a TCAM. If so what are its
characteristics (performance, density, pinout, power,
interface)
 What type of Network Processor (NPU) is used (ASIC, FPGA,
or commercial NPU from Cavium, Broadcom, Xelerated, etc)
36
© 2010 Renesas Electronics America Inc. All rights reserved.
Renesas TCAM Value Proposition
 Let them know that Renesas has deep experience in TCAM
design & production
 We are a leading supplier of proprietary TCAMs to the world’s
largest network equipment vendor
 We have patented technology that significantly reduces cost and
power
 Explain that Renesas has leveraged this experience to
introduce the 20M Quad Search TCAM to the general market
 Explain that Renesas has a rich roadmap that will cover
multiple densities and performance levels
 Explain that Renesas is partnering with leading NPU vendors
Cavium and Xelerated for interoperability
 Explain that only Renesas offers both TCAM and other high
speed memory like QDR SRAM and LLDRAM
37
© 2010 Renesas Electronics America Inc. All rights reserved.
Call to action
 Focus on networking equipment vendors (similar to Alcatel,
Juniper, Brocade, Extreme, etc)
 Target high end Enterprise, Metro, Core Switches & Routers
 All TCAM datasheet / model / pricing requests should be sent
to rob.raghavan@renesas.com , 408-382-7306
 Make sure to get an NDA signed
 Find out if they use QDR/DDR SRAM or LLDRAM for packet
buffering and packet lookup
38
© 2010 Renesas Electronics America Inc. All rights reserved.
The Real Summary
 We are the only vendor who has QDR and RLDRAM (but legally
LLDRAM) in production (really, who is GSI?)
 There are only two vendors in the world with TCAM, if you include
us
 We are the only one stop shop for networking memory solutions
 QDR/DDR: 18M, 36M 72M; QDRII and QDRII+
 RLDRAM: 288M now, 576M and 1.1G end of year
 TCAM: 20M now, 18M and 4.5M end of year
 RLDRAM is a great entry point with customers
 It’s been a one vendor show longer than customers wanted
 72M QDR is another
 Open with “Hey, I saw the Cypress guy down at the bar buying drinks.
How’s he doing?”
 Once you’re talking QDR or LLDRAM, ask them if they use any
TCAM.
 From Dan Mahoney’s June 13 report to Japan:
“REA’s business development momentum in the network
memory area is increasing, making this one of the best near
term growth opportunities we have.”
39
© 2010 Renesas Electronics America Inc. All rights reserved.
Renesas Electronics America Inc.
© 2010 Renesas Electronics America Inc. All rights reserved.