ECE 425
Peripheral Functions
1
Microcontroller Peripherals
• ARM is unlike previous microcontrollers in that all
peripheral functions are not built in.
• It’s up to the manufacturer to add everything outside
of the CPU functions
– ARM CPU is just a core. Different concept from HC12, etc.
– All peripheral functions go through internal bus system
• Any microcontroller will have a lot of other functional
units.
• ARM systems have them too, but they are memorymapped peripherals, not part of core.
2
Memory Mapping
• ARM has 32 bit address bus.
• Could be all devoted to memory, but that’s
not a practical microcontroller
implementation.
• Instead, some addresses are for peripheral
functions.
– Control registers
– Data I/O
3
Peripheral Units
•
•
•
•
•
•
•
•
GPIO: General Purpose Input/Output
USB: Universal Serial Bus
UART, SPI, I2C: Universal Asynchronous Rcv/Tr
Timer
Watchdog
D/A, A/D
PWM: Pulse Width Modulator
RTC: Real Time Clock
4
Low pin-count 32-bit microcontrollers for vector
control: TMPM372, TMPM373 and TMPM374
5
GPIO
• Default to input
– Set control registers to change to output
• Addressable as words, half words and bytes
• Controllable (set, clear, direction) on bit level
– One port can have some bits input, some bits
output
• Pins are multi-purpose: not all are available
for GPIO if other peripherals are in use.
6
7
GPIO
• Two ports: P0 and P1
– P0 is 32 bits but P1 only has upper 16 bits
available for GPIO
• Some pins may also be used for analog
functions.
– When analog is used, pins are disconnected from
digital functions. Can not be read/written.
8
New & Legacy Registers
• Some I/O functions have duplicate control
registers.
• Faster operation & better controls with new.
– Old are maintained to keep code compatibility
with old processors
– No advantage for new development
• Only new (fast) system will be covered in class.
9
Set Direction
• By default, all GPIO will be in input mode after
reset.
• You can change pin(s) to output mode by
setting bits in the FIODIR registers.
• Two registers, one for Port 0, one for Port 1.
• Set to 1 for output, leave at 0 for input.
• Addresses:
– FIO0DIR = 0x3FFF C000, FIO1DIR = 0x3FFF C020
10
Bits 24, 26, 27 and 31
• NXP LPC214x processor used in lab apparently
does not allow access to port 0 bits 24, 26 and
27.
• Port 0 bit 31 can only be output.
• Port 1 has only bits 16 – 25 available on the
expansion slot for easy access.
– Limitation of lab board, not ARM system
11
Byte and Halfword Access
• Direction registers may also be accessed on a
byte or halfword basis.
• Same addresses as before, just use
byte/halfword writes to the desired bits.
• Example: want to change only bits 31:24 of
port 1: write a byte to address 0x3FFF C023.
• Example: want to change bits 31:16 of port 0:
write a halfword to address 0x3FFF C002
12
IO Mask Registers
• Bits that are set (logic 1) in the mask registers
prevent corresponding port bits from being
written, read, set or cleared.
• Default is all zeros
– Generally should be left that way
• Addresses: FIO0MASK = 0x3FFF_C010,
FIO1MASK = 0x3FFF_C030
13
IO Value Register
• FIOPIN registers are used to read the values of
IO pins.
• Will return valid readings ONLY if the
corresponding mask register bits are NOT SET.
• Will return values even if the pin is set to
some other digital function, not GPIO.
– But not if it’s a D/A output
• Addresses: FIO0PIN = 0x3FFF_C014, FIO1PIN =
0x3FFF_C034.
14
Set Output Bits High
• FIOSET registers are used to set output pins to
Logic 1.
– Only works if corresponding MASK bits are not set
– Ignored if they are set
– Ignored if pin is set to input mode
• Writing zeros to FIOSET registers does not set
pins low.
– Use FIOCLR registers for that.
• Addresses: FIO0SET = 0x3FFF C018, FIO1SET =
0x3FFF C038
15
Set Output Bits Low
• FIOCLR registers are used for that.
• Same masking as before: changes are ignored
if bits are masked out or set to input mode.
• Write a 1 to set a bit to 0. Writing 0s has no
effect.
• Addresses: FIO0CLR = 0x3FFF C01C, FIO1CLR =
0x3FFF C03C
16
Toggle Bits
• Last action wins
• No need to cancel a set before clearing.
– Vice versa, too.
17
Driving LEDs
• Lab boards are set up so you can just turn
them on and off.
• That won’t work when you’re the system
engineer.
• Need to match source/sink characteristics of
chip I/O with electrical characteristics of
external devices.
18
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns
slew rate control.
[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns
slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It
requires external pull-up to provide an output
functionality.
[4] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate
control) and analog input function. If configured
for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3
ns. When configured as an ADC input, digital
section of the pad is disabled.
[5] 5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate
control) and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL
levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value typically ranges from 60 kΩ to 300 kΩ.
[7] Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision
2.0 (Full-speed and Low-speed mode only).
[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
19
TTL Levels
• TTL logic is obsolete but logic levels carry on.
• Use only for interfaces
– Way too slow & power hungry for internals of
integrated circuits.
•
•
•
•
VOL = 0.4 V
VOH = 2.4 V
IOL = 16 mA
IOH = 400 µA
•
•
•
•
VIL = 0.8 V
VIH = 2.0 V
IIL = 1.6 mA
IIH = 40 µA
20
LED Electrical Characteristics
Type
Color
IF
max.
VF
typ.
VF
max.
VR
max.
Luminous
intensity
Viewing
angle
Wavelength
Standard
Red
30mA
1.7V
2.1V
5V
5mcd @
10mA
60°
660nm
Standard
Bright red
30mA
2.0V
2.5V
5V
80mcd @
10mA
60°
625nm
Standard
Yellow
30mA
2.1V
2.5V
5V
32mcd @
10mA
60°
590nm
Standard
Green
25mA
2.2V
2.5V
5V
32mcd @
10mA
60°
565nm
High
intensity
Blue
30mA
4.5V
5.5V
5V
60mcd @
20mA
50°
430nm
Super
bright
Red
30mA
1.85V
2.5V
5V
500mcd @
20mA
60°
660nm
Low current
Red
30mA
1.7V
2.0V
5V
5mcd @
2mA
60°
625nm
21
Mismatch
• TTL outputs can not source enough current to
drive most LEDs.
22
’05 Open-Collector Output
© Texas Instruments
23
TTL Open Collector IOL (Sink Current)
•
•
•
•
IOL Low-level output current is 40 mA
That’s plenty.
Source is zero, but that’s OK, too.
Procedure
– Drive OC TTL gate from processor pin.
– With logic 1 input, output transistor is ON.
• Being on, it can SINK current coming through LED.
– With logic 0 input, output transistor is off.
• Current flow is blocked, LED is off.
24
Totem Pole Inverter
25
Ones and Zeros
• Digital electronics engineering is mostly about
ones and zeros.
• Under that abstraction, it’s still an analog
world.
• Currents and voltages must match up. Ohm’s
Law, KCL, KVL still apply.
• Most malfunctioning designs are a result of
ignoring Ohm’s Law.
26
Clock System
•
•
•
•
Oscillator
PLL
Power Control/Wakeup
The details of all these systems are specific to
the LPC2148. Other implementations may
differ, though all will be similar.
• None of this resides in the ARM core.
27
Time Base
• All processors have a time base.
• Usually the fundamental frequency is
provided by an external crystal.
• Modern processors like ARM systems
internally multiply the external frequency.
• ARM used in lab has internal oscillator
components and can be used with a simple
crystal rather than an active transistor
oscillator.
28
Clock Inputs
A common clock can be distributed to several processors to run them in sync or a
crystal can be added to the processor circuit. Capacitor values depend on oscillator
frequency (see manufacturers’ data sheets for value/frequency table). External
clock design (left) has a bigger range of allowed values than local oscillator design
(right).
29
Frequency Range
• LPC214x processors can use external clocks from
1 to 50 MHz.
– Further restrictions if internal PLL is to be used. Then
range is only 10 to 25 MHz.
• If internal oscillator components are to be used,
range is 1 to 30 MHz.
• Lab board uses 12 MHz crystal, internally
multiplied to up to 60 MHz.
– 60 MHz is max. internal operating frequency.
– 12 MHz is a good choice because USB needs 48 MHz.
30
Frequency Range Algorithm
31
ARM PLL
Frequency Synthesizer
156 to 320 MHz
fOSC
X
LPF
CCO
Divide by
2*P
M*fOSC
=CCLK
From
CPU
Divide by M
From CPU
32
PLL
• Processor has two internal PLLs.
• One provides time base for almost all the
system.
– Has an interrupt for signaling stability to the
processor logic.
• The other is exclusively for use by the USB.
– Must always be 48 MHz
33
ARM Clock/PLL System
PLL0 output can be 10 to 60 MHz. PLL1 output is
always 48 MHz. Input frequency must be 10 to 25
MHz.
34
Enabling PLL
• PLLs take some time to lock and stabilize.
– Operation is unreliable at power on.
• Need a multi-step procedure to enable PLL.
– 1. Choose PLL frequency
• Algorithm to be shown shortly
– 2. Enable PLL
– 3. Wait for PLL to signal it is stable
– 4. Switch internal clocking to PLL output
35
PLL Control Registers
• Four for each PLL.
• Must be programmed to stay within several
operating parameters, including internal
current-controlled oscillator limits.
– 156 MHz ≤ FCCO ≤ 320 MHz
• Final PLL output has at least one
programmable divide by 2 stage to ensure
50% duty cycle.
36
PLL Control Registers
Register Description
Name
PLL0 Name & PLL1 Name &
Address
Address
PLLCON
PLL Control Register. Holding register for
updating PLL control bits
0xE01F C080
PLL0CON
0xE01F C0A0
PLL1CON
PLLCFG
PLL Configuration Register. Holding register
for updating PLL configuration values
0xE01F C084
PLL0CFG
0xE01F C0A4
PLL1CFG
PLLSTAT
PLL Status Register. Read-back register for
PLL control and configuration information
0xE01F C088
PLL0STAT
0xE01F C0A8
PLL1STAT
PLLFEED PLL Feed Register. This register enables
0xE01F C08C
loading of the PLL control and configuration PLL0FEED
information from the PLLCON and PLLCFG
registers into the shadow registers that
actually affect PLL operation.
0xE01F C0AC
PLL1FEED
37
PLL Programming Steps - Overview
1. Select the desired operating frequency for your system ( Processor
operating frequency) CCLK.
2. Check the oscillator connected to the controller on board. (FOSC)
3. Calculate the value of PLL multiplier “M”.
CCLK = M × FOSC
4. Find the value of PLL Divider “P” in such a way that is in the range of 156
MHz to 320 MHz.
156 < FCCO < 320 = CCLK x 2 x P
5. Write the values PLLCON and PLLCFG.
6. Write the PLLFEED Values 0xAA and 0x55. Interrupts MUST be disabled!!!
7. Wait for PLL to lock.
8. Connect the PLL.
38
PLL Control Register
• Only two bits used: one to enable the PLL, the
other to connect it.
• Other bits are reserved and should be left at zero
(default).
• Bit 0: PLLE (PLL Enable). When set to 1, allows PLL
to lock on to specified frequency.
• Bit 1: PLLC (PLL Connect). When set to 1, switches
PLL output in place of time base after other
procedures are correctly done.
– Will have no effect if feed not completed
39
PLL Control Register
• First enable PLL by setting PLLE bit.
• Once PLL Lock has been established (read PLL
status register to determine this), set PLLC bit.
• Addresses: PLL0CON - address 0xE01F C080,
PLL1CON – address 0xE01F C0A0
40
PLL Switching Notes
The PLL must be set up, enabled, and lock established before it
may be used as a clock source. When switching from the
oscillator clock to the PLL output or vice versa, internal circuitry
synchronizes the operation in order to ensure that glitches are
not generated.
Hardware does not insure that the PLL is locked before it is
connected or automatically disconnect the PLL if lock is lost
during operation. In the event of loss of PLL lock, it is likely that
the oscillator clock has become unstable and disconnecting the
PLL will not remedy the situation.
41
PLL Operating Modes
PLLC PLLE
0
0
0
1
1
0
1
1
PLL Function
PLL is turned off and disconnected. CCLK is
input clock.
PLL is active but not connected.
Same as 00. Prevents PLL from being
connected without being enabled.
PLL is active and connected.
These bits are in the PLL Control Register. Each PLL has its own
Control Register.
42
PLL Configuration Register
• Holds five bit multiplier field and two bit
divider field.
– Multiplier: Bits 4:0
– Divider: Bits 6:5
•
•
•
•
MSB is reserved. Should not be set.
Only eight bits defined for this register.
Addresses: PLL0CFG - 0xE01F C084, PLL1CFG 0xE01F C0A4
43
PLL Multiplier
• Five bits, binary values 0 – 31.
• Multiply factor is binary value + 1
– Range 1 - 32
44
PLL Divider
• Two bits, binary values 0, 1, 2, 3
• Divider values:
Bits 6:5
Divider Factor
00
1
01
2
10
4
11
8
45
PLL Frequency Variables
46
PLL Status Register
• Read-only register showing actual values
being used by the PLL.
– Not necessarily what you have set them to be.
– Changes do not take effect until a proper PLL feed
has occurred.
• Addresses: PLL0STAT - 0xE01F C088, PLL1STAT
- 0xE01F C0A8
47
PLL Status Register Bits
Bit(s)
Name
Description
4:0
MSEL
Read back of PLL Multiplier value. Actual value being used by PLL
6:5
PSEL
Read back of PLL Divider value. Actual value being used by PLL
7
-
Reserved
8
PLLE
Read back of PLL Enable bit. When set, PLL is active but not necessarily
clock source.
9
PLLC
Read back of PLL Connect bit. When this and PLLE are both set, PLL is
clock source. When either is zero, oscillator clock is used.
10
PLOCK
When set, indicates PLL has established lock on desired frequency.
15:11
-
Reserved
48
PLL Feed Operation
A correct feed sequence must be written to the PLLFEED register
in order for changes to the PLLCON and PLLCFG registers to take
effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be
consecutive APB bus cycles. The latter requirement implies that
interrupts must be disabled for the duration of the PLL feed
operation. If either of the feed values is incorrect, or one of the
previously mentioned conditions is not met, any changes to the
PLLCON or PLLCFG register will not become effective.
49
PLL Feed Register
• One for each PLL
• PLL0FEED - address 0xE01F_C08C, PLL1FEED –
address 0xE01F_C0AC
• Only bits 7:0 are defined
• Sequence is first write AA, then write 55.
• Odd write-only register. Can not ever be read
back.
50
PLL Feed and Status
• Status register shows what the PLL is actually
doing.
• If Feed has not been operated per spec, this
may not be what you wanted it to do, as
reflected in values written to control and
configuration registers.
51
PLL Interrupt
• PLL Lock bit is connected to the interrupt
controller
– Bit 12 of VICIntEnable
• Procedure:
– Set PLL values, including Feed procedure
– Enable interrupt
– Go about other initialization tasks
– When interrupt triggers, switch clocks to PLL
outputs. This is done in ISR.
52
PLL Frequency Calculation
The PLL output frequency (when the PLL is both active
and connected) is given by:
CCLK = M × FOSC or CCLK = FCCO / (2 × P)
The CCO frequency can be computed as:
FCCO = CCLK × 2 × P or FCCO = FOSC × M × 2 × P
53
Frequency Calculation Procedure
• Choose the internal operating frequency
– No more than 60 MHz. For PLL1, it’s always 48.
– Keep any UART frequencies in mind: must be able to
precisely divide down to them from internal
frequency.
• Choose the oscillator frequency. Internal
frequency must be an integer multiple of
oscillator frequency.
FO = I * FCLK
1 ≤ I ≤ 32
54
Frequency Calculation Procedure
• M is I – 1.
– M will be written to bits 4:0 of Configuration Reg.
• Find a value for J such that
J = FCC0/(CCLK * 2)
156 ≤ FCCO ≤ 320
J = 1, 2, 4 or 8: only possible values
• P is log2 J.
– P will be written to bits 6:5 of Configuration Reg.
55
Frequency Configuration Example
System design asks for FOSC= 10 MHz and requires CCLK = 60
MHz.
Based on these specifications, M = CCLK / Fosc = 60 MHz / 10
MHz = 6. Consequently, M - 1 = 5 will be written as
PLLCFG[4:0].
Value for P can be derived from P = FCCO / (CCLK x 2), using
condition that FCCO must be in range of 156 MHz to 320
MHz. Assuming the lowest allowed frequency for FCCO = 156
MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest FCCO
frequency criteria produces P = 2.67. The only solution for P
that satisfies both of these requirements is P = 2. Therefore,
PLLCFG[6:5] = 1 will be used.
56
Another Example
System design asks for FOSC= 12 MHz and requires the USB clock
of 48 MHz.
M = 48 MHz / Fosc = 48 MHz / 12 MHz = 4. Consequently, M - 1 =
3 will be written as PLLCFG[4:0].
Value for P can be derived from P = FCCO / (48 MHz x 2), using
condition that FCCO must be in range of 156 MHz to 320 MHz.
Assuming the lowest allowed frequency for FCCO = 156 MHz, P =
156 MHz / (2 x 48 MHz) = 1.625. The highest FCCO frequency
criteria produces P = 3.33. Solution for P that satisfy both of
these requirements are P = 2 and P = 3. Therefore, either of
these two values can be used to program PLLCFG[6:5] in the
PLL1.
57
PLL & USB
• If USB is to be used, the only possible external
frequencies are 12, 16 and 24 MHz.
• USB must be 48 MHz.
• 48 MHz must be an integer multiple of the
external clock.
• If the PLL is to be used (and that’s the only
way to get the 48 MHz PLL clock), the external
clock must satisfy 10 ≤ F ≤ 25. Only 12, 16 and
24 meet those requirements.
58
VPB Divider
• VPB Divider provides peripherals with PCLK at
desired frequency.
• Can be same as CCLK, ½ or ¼ CCLK.
• Objective is power savings. Peripherals don’t
necessarily need to run as fast as the core.
59
VPB Divider
External Time Base
PLL0
Processor Clock
VPB
Divider
VPB Clock (PCLK)
60
VPB Divider Operation
• Write to VPBDIV register, address
0xE01F_C100
• Only 2 LSBs have meaning. Other bits are all
reserved and should be left alone.
Bits 1:0
VPB Output
Frequency
Notes
00
¼ CCLK
Default
01
CCLK
10
½ CCLK
11
Reserved
Previous frequency
will be maintained
61
Power Control
• LPC214x processors support two reduced
power modes
– Idle mode
• No instructions are run, but peripherals continue
operation.
• Peripheral-generated interrupts can wake up processor
– Power down mode
• Oscillator is shut down.
• Power consumption goes to near zero.
62
Idle Mode
• The CPU stops.
– Power used by CPU, memory, memory controller,
internal buses is saved.
• Execution is suspended until a reset or
interrupt from peripheral occurs.
• Peripherals run in idle mode and may
generate interrupts to resume the CPU
execution.
63
Entering Idle Mode
• Idle mode is started by writing a 1 to bit 0 of
the PCON register.
• PCON register has several other functions too,
to be discussed shortly.
• If power down mode is also selected, that will
win.
• PCON register is at address 0xE01F_C0C0.
64
Power Down Mode
• The oscillator is shutdown and the chip
receives no internal clocks.
• All the information of current execution state
is preserved in this mode.
• A Reset signal or External Interrupt can
terminate the power-down mode.
• PLL will not automatically reconnect after
power down. ISR must re-initialize PLL.
65
External Interrupt/Reset
• It takes an external interrupt or reset to get
out of power down mode.
– Internal peripherals are mostly also powered
down, so they can not restart the processor. They
will never generate an interrupt when powered
down.
– Mostly? Some can run off other clock sources
(some comm. interfaces), so they can generate an
interrupt that will restart the processor.
66
Entering Power Down Mode
• Similar to entering Idle: it’s the next bit in the
same register.
– Set bit 1 to 1.
• Will not work (will be ignored) if USB is turned
on and set to require clock to work.
– USB can work from external clock source.
67
Exiting Power Down
• Clock is stopped during PD.
• Complete restart is needed.
• Oscillator needs to stabilize.
– Takes 4k cycles.
– During this time, external bus actions will be ignored.
• Use Idle if that won’t work for you.
• Once it’s running again, restart routine must clear
PD bit or it will reassert in an endless loop.
68
PCON Register
Bit(s)
Name
Function
0
IDL
Puts processor into idle mode.
1
PD
Puts processor into power down mode.
2
BODPDM
Disables Brownout detector when in power down
mode.
3
BOGD
Brown out Global Disable. Brown out circuit is fully
disabled, consuming no power.
4
BORD
Brown out Reset Disable. Second stage of low voltage
detection will not cause chip reset.
5-7
Reserved
All PCON functions are enabled by writing a 1 to the indicated bit.
Only bits 0 – 4 should ever be written to. All are 0 by default.
69
Peripheral Power Control
• Most peripheral units can selectively and
individually turned off for power savings.
– Done by gating the clock. Implication is that nonclocked analog blocks won’t totally shut down.
• Some peripherals like GPIO, Watchdog timer, Pin
connect block and System Control block cannot
be turned off.
• Default is to enable everything. Reset
automatically turns all peripherals on.
• 1 to Enable. 0 to Disable
70
PCONP Register, Address 0xE01F_C0C4
Bit(s)
Function
Bit(s)
Function
0
Reserved
9
RTC
1
Timer 0
10
SPI 1
2
Timer 1
11
Reserved
3
UART 0
12
A/D 0
4
UART 1
18:13 Reserved
5
PWM
19
I2C 1
6
Reserved
20
A/D 1
7
I2C 0
30:21 Reserved
8
SPI 0
31
USB
71