8085 MPU and its architecture with the Block diagram
The above figure shows the internal architecture of 8085 microprocessor. It includes the following components
–
1)
2)
3)
4)
5)
6)
Arithmetic and Logic Unit (ALU)
Register Array
Instruction Register and Decoder
Timing & Control unit
Interrupt Control
Serial I/O Control
3) Arithmetic and Logical Unit (ALU):
It performs arithmetic and logical operations. Addition, subtraction, multiplication, division, AND, OR, XOR,
NOT, shift and rotate operations are done by ALU. It includes the accumulator, the temporary register, the
arithmetic and logic circuits, and five flags. The result is stored in the accumulator, and the flags are set or reset
according to the result of the operation. The descriptions and conditions of the flags are –
a) S-Sign flag: After the execution of an arithmetic and logic operation, if the bit D7 of the result is 1, the
sign flag is set; otherwise, it is reset. If D7 is 1, the number is a negative number and if D7 is 0, the
number is a positive number.
b) Z-Zero flag: After the execution of an arithmetic and logic operation, if the result is 0 i.e. all the bits of
the result are 0, then the zero flag is set, otherwise, it is reset.
c) AC-Auxiliary Carry flag: After the execution of an arithmetic and logic operation, if a carry is
generated by the bit D3 and passed to the bit D4, then the AC flag is set, otherwise, it is reset. It is used
only internally for BCD (Binary Coded Decimal) operations and is not available for the programmer.
d) P-Parity flag: After the execution of an arithmetic and logic operation, if the result has an even number
of 1s, then the P- flag is set, otherwise, it is reset.
e) CY-Carry flag: After the execution of an arithmetic and logic operation, if the operations results in a
carry, then the CY- flag is set, otherwise, it is reset.
The bit positions reserved for these above mentioned flags in the flag resister are as follows –
D7
S
D6
Z
D5
D4
AC
D3
D2
P
D1
D0
CY
Eg. ADI 01 H where A=FF H
1 1 1 1
0 0 0 0
1 (CY) 0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
Where S=0, Z=1, CY=1, AC=1, P=0
Eg. ADD B where A=47H and B=51H
Where S=1, Z=0, CY=0, AC=0, P=0
Carry
47H=0100 0111
51H=0101 0001
98H=1001 1000
2) Register Array:
It consists of number of registers for storing data and addresses. It can be of two types:
a) General purpose registers
b) Special purpose registers
General purpose registers are used for temporary storage of data or address during execution. They are B, C,
D, E, H and L. They are all 8 bit registers. So, to store 16 bit data we have to form a register pair like: BC, DE
or HL.
Special purpose registers:
The following registers come under this category and each performing a special function.
Accumulator (A) – It is an 8 bit register which is used for storing the operands/data during execution.
Program counter (PC) – It is a 16 bit register used to store the memory address of the next instruction to be
executed.
Status register – It stores the present status of the microprocessor after any arithmetic and logical operation. It
records any occurrence of carry, auxiliary carry, sign, zero and odd/even parity.
Stack pointer – It is a 16 bit register used to initialize the stack. It holds the address of the top of the stack.
Two additional registers called temporary registers W and Z are included in the register array. These registers
are used to hold 8-bit of data during the execution of some instructions. They are used internally and they are
not available to the programmer.
3) Instruction register and Decoder –When an instruction is fetched from memory, it is loaded into the
instruction register. On the other hand, Instruction Decoder decodes the instruction and establishes the sequence
of events to follow.
Both are the part of the ALU.
4) Timing & Control unit:
It generates the clock signals and control signals for communication between processor and peripheral devices.
5) Interrupt Control:
Interrupt is a signal send by an external device to the processor to perform a particular task or work.
Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral and
the microprocessor.
When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate
signal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor suspends
its current activity and executes an interrupt service routine to complete the data transfer
between the peripheral and processor. After executing the interrupt service routine the processor
resumes its current activity. This type of data transfer scheme is called interrupt driven data
transfer scheme.
The 8085 has five hardware interrupt and 8 software interrupt signals that can be used to interrupt a program
execution.
6) Serial I/O Control:
The 8085 has two signals to implement the serial transmission – SID (Serial Input Data) and
SOD (Serial Output Data). In serial transmission, data bits are sent over a single line, one bit at a
time, such as the transmission over the telephone lines.
Block and Pin Diagram of 8085MP
The block diagram of 8085MP shows the signals flow of the 8085 MP architecture. It is a way to know where
the specific memory, I/O etc. are available.
All the signals can be classified into 6 – groups –
1) Address bus
2) Data bus
3) Control and status signals
4) Power supply and frequency signals
5) Externally initiated signals and
6) Serial I/O ports
1) Address bus
2) Data bus
The 8085 has 16-signal lines (pins) that are used as the address bus. These lines are split into 2 –segments: A15A8 and AD7-AD0. The first half i.e. eight signal lines, A15-A8 are unidirectional and are used for the most
significant bits called high order address of 16-bit address. The signal lines AD7-AD0 are used for dual purpose.
They are used as low order address bus as well as the data bus. During the early part of the cycle in an
execution, they are used as low-order address bus and during the later part of the cycle; these lines are used as
the data bus.
The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A 16 bit binary number allows 216
different numbers, or 32000 different numbers, i.e. 0000000000000000 up to 1111111111111111. Because
memory consists of boxes, each with a unique address, the size of the address bus determines the size of
memory, which can be used. To communicate with memory the microprocessor sends an address on the
address bus, e.g. 0000000000000011 (3 in decimal), to the memory. The memory selects box number 3 for
reading or writing data. Address bus is unidirectional, i.e. numbers only sent from microprocessor to memory,
not other way.
On the other hand, Data bus carries ‘data’, in binary form, between μP and other external units, such as
memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory and μP size helps determine
performance of μP. The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits.
Data bus used to transmit "data", i.e. Information, results of arithmetic, etc, between memory and the
microprocessor. Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8
bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number has to be broken down
into chunks of 255. This slows microprocessor. Data Bus also carries instructions from memory to the
microprocessor. Size of the bus therefore limits the number of possible instructions to 256, each specified by a
separate number.
Difference between data bus and address bus
Data bus
Address bus
1. Bidirectional
1. Unidirectional
2. Low order data bus to transfer data between
2. High order address bus to send out the
MP and memory.
memory address on the address bus from
MP to the Memory.
3. 8 lines
3. 16 lines
3. Control and status signals
This group has two control signals (RD and WR), three status signals (IO/M, S1, S0) to identify the nature of
operation and one special signal (ALE) to indicate the beginning of the operation.
i) ALE (Address Latch Enable): used to latch the low order address from the multiplexed bus and generate
a separate set of eight address lines A7-A0.
ii) 𝑅𝐷 (Read): used to indicate that the selected I/O or memory device is set to be read and data are
available on the data bus.
iii) 𝑊𝑅 (Write): used to indicate that the data on the data bus are to be written in a selected memory or I/O
location.
iv) IO/𝑀 (Input/Output Memory): used to differentiate between I/O and memory operations. When high it is
I/O operation and when low, it is memory operation.
v) S1 and S0: similar to IO/M and can identify various operations, but they are rarely used in small systems.
S1
S0
Operation
0
0
Halt
0
1
Read
1
0
Write
1
1
Fetch
4) Power supply
The power supply and frequency signals are as follows –
i)
VCC: +5 volt power supply
ii)
VSS: Ground reference
iii)
X1 and X2: A crystal (RC and LC network) is connected at these 2 –pins. The frequency is internally
divided into two to operate the system at 3 MHz; the crystal must have a frequency of 6 MHz
iv)
CLK (out): used as the system clock for devices.
5) Externally initiated signals
The 8085 has five interrupt signals and six external signals. The signals are as
Interrupt signals
i)
INTR (Interrupt request): It is used as a general purpose interrupt. If it is active, the PC will be
inhibited from incrementing and an INTA will be issued. During this cycle, a RESTART/CALL
instruction can be inserted to jump to the ISR. The INTR is enabled or disabled by software. It is
disabled by reset and immediately after an interrupt is accepted.
ii)
RST 7.5, 6.5, 5.5: These are the vector interrupts. They can be used to transfer the program
control to specific memory locations.
iii)
TRAP: It is a non-maskable interrupt and has the highest priority. It is unaffected by any mask or
interrupt enable.
External signals
i)
INTA: It is used instead of RD signal during the instruction cycle after an INTR is accepted.
ii)
HOLD: It indicates that another master is requesting the use of address and data buses. The CPU
upon receiving the HOLD request will relinquish the use of buses as soon as the completion of
the current machine cycle. The CPU can regain the buses only after the HOLD request is
removed. When HOLD request is acknowledged, the address, data, Read (RD), Write (WR), and
IO/M lines are tri-stated.
iii)
HLDA: It indicates that when CPU has received the HOLD request, it will relinquish the buses
in the next clock cycle. HLDA goes low after the HOLD request is removed. The CPU takes the
buses one half clock cycles after HLDA goes low.
iv)
READY: Used to delay the MP read or write cycles until a slow responding peripheral device is
ready to send or accept data. When ready is high during a read or write cycle, it indicates that the
memory or the peripheral device is ready to send or accept data. If ready is low, CPU will wait
for the ready signal to go high before completing the read or write cycle.
v)
RESET IN: When the signal on this pin goes low, the PC is set to zero, the buses are tri-stated
and the MP is held in reset condition as long as reset is applied.
vi)
RESET OUT: This signal can be used to reset other devices.
6) Serial I/O ports:
The 8085 has two signals to implement the serial transmission – SID (Serial Input Data) and
SOD (Serial Output Data). In serial transmission, data bits are sent over a single line, one bit at a
time, such as the transmission over the tele phone lines.
Fig. 8085 MP Functional Block Diagram
Fig. 8085 MP Signals
5) Externally initiated signals
The 8085 has five interrupt signals and six external signals. The signals are as
Interrupt signals
vii)
INTR (Interrupt request): It is used as a general purpose interrupt. If it is active, the PC will be
inhibited from incrementing and an INTA will be issued. During this cycle, a RESTART/CALL
instruction can be inserted to jump to the ISR. The INTR is enabled or disabled by software. It is
disabled by reset and immediately after an interrupt is accepted.
viii)
RST 7.5, 6.5, 5.5: These are the vector interrupts. They can be used to transfer the program
control to specific memory locations.
ix)
TRAP: It is a non-maskable interrupt and has the highest priority. It is unaffected by any mask or
interrupt enable.
External signals
x)
𝐼𝑁𝑇𝐴: It is used instead of 𝑅𝐷 signal during the instruction cycle after an INTR is accepted.
xi)
HOLD: It indicates that another master is requesting the use of address and data buses. The CPU
upon receiving the HOLD request will relinquish the use of buses as soon as the completion of
the current machine cycle. The CPU can regain the buses only after the HOLD request is
removed. When HOLD request is acknowledged, the address, data, Read (𝑅𝐷), Write (𝑊𝑅), and
IO/𝑀 lines are tri-stated.
xii)
HLDA: It indicates that when CPU has received the HOLD request, it will relinquish the buses
in the next clock cycle. HLDA goes low after the HOLD request is removed. The CPU takes the
buses one half clock cycles after HLDA goes low.
xiii)
READY: To delay the MP read or write cycles until a slow responding peripheral device is ready
to send or accept data. When ready is high during a read or write cycle, it indicates that the
memory or the peripheral device is ready to send or accept data. If ready is low, CPU will wait
for the ready signal to go high before completing the read or write cycle.
xiv)
𝑅𝐸𝑆𝐸𝑇 𝐼𝑁: When the signal on this pin goes low, the PC is set to zero, the buses are tri-stated
the MP is reset.
xv)
RESET OUT: This signal can be used to reset other devices.
The 8085A is a 8-bit MP general purpose MP capable of addressing 64k of memory. The device has 40 dual
inline pins, requires a +5V single power supply and can operate with a 3-MHz single phase clock. The 8085A-2
version can operate at the maximum frequency of 5 MHz. The 8085 is an enhanced version of its predecessor,
the 8080A; its instruction set is upward compatible with that of 8080A, meaning that the 8085 instruction set
includes all the 8080A instructions plus some additional ones.
All the signals can be classified into six groups –
1) Address Bus
2) Data Bus
3) Control and Status Signals
4) Power Supply and Frequency Signals
5) Externally Initiated signals
6) Serial I/O ports