Xilinx Template (light) rev

advertisement
What are FPGA Power Management
HDL Coding Techniques
Xilinx Training
Objectives
After completing this module, you will be able to:
Explain how power is dependent on the HDL coding style you
use
Describe how your design’s power consumption is dependent
on your use of control signals
Explain how some common design techniques can improve
your design’s power consumption
Show how some common design techniques can improve your
design’s power consumption
Look at Enable Rates on BRAM
Enable rate is the dominant factor in BRAM
power consumption, toggle activity is secondary
– Only enable BRAM during an active read or write cycle
Use smart architecting for “multiple BRAM”
blocks
Consider LUTRAM (Distributed memory) for small
memory blocks
BRAM Power Optimization
Conceptual
2k x 36 Array
Minimum Area
Xilinx Block Memory Generator Tool
2k x 36 Array
Low power
One BRAM enabled at a time
 Allows selection between high performance and low
power
LUTRAM vs. BRAM
XPE: Example of 16 sets of 2k
bits
BRAM
85 % power
savings
with LUTRAM
LUTRAM
XPE: Example of 16 sets of 18k bits
LUTRAM
28 %
power
savings
BRAMwith BRAM
 Use LUTRAM for small storage for lowest power
– This is a sample output from the Xilinx Power Estimator
Spreadsheet
Resets
Two kinds of resets
– Global…usually used to reset after configuration
• This is done by default after configuration of the FPGA
and does not need to be coded into the design
• Access to this net is done with the GSR port from
the Startup component (only necessary if you
wish to perform a global reset s second time)
• Note…if you are coding in a global reset into your
HDL you are actually coding in a second reset
• Some ASIC technologies require at most an
initialization when they power up. But FPGAs do not
require a reset.
– Local…used as a standard part of some components
behavior
– FSM, counters, etc
Global Reset Net (GSR)
The GSR input is an active-high global set/reset
net that is active at the end of configuration
– It uses a dedicated routing resource for signal
distribution
• Saves general interconnect
– It can also be used to restore the initial state of the
FFs in the FPGA at any time
• The intial state is communicated with an INIT attribute
• It drives the output FFs for each block RAM, but does not
affect the contents of each memory or SRL
– It is connected to all synchronous elements through a
wired OR gate
• This allows a local reset to also drive the FF’s set/reset
port
Inferring an Initialization (XST only)
If you have a reset, you can initialize all registers in VHDL /
Verilog code
SR will cause the flip-flop to be set to the state inferred here
– Inference is supported only for data types std_logic, bit_vector, bit, but
NOT integer
VHDL:
signal my_regsiter : std_logic_vector (7 downto 0) := (others <= ‘0’);
Verilog:
reg [7:0] my_register = 8’h00;
This is helpful for RTL simulation of the design
– If it functions during simulation, it should function on the FPGA
– Note…if you design without a reset in your design, you still get a free
global reset
No Reset is Best
Synthesis can infer SRL-based shift registers
– But only if no reset is inferred on the component (otherwise flip-flops are
wasted)
– Or, the synthesis tool can emulate the reset
• However, this will uses extra resources and take extra clock cycles to set up
(not what you want)
Use a Synchronous Reset
Each DSP slice effectively has more than 250 registers
– None have an asynchronous reset
Many designs that run out of slices are not fully utilizing their
DSP slice resources
– Synthesis tools will infer the DSP slice resources for multipliers, but
they are not smart enough to infer other functions
• Can control synthesis use with attributes, but NOT if an asynchronous reset
is used
Block RAMs obtain minimum clock-to-output time by using
their output register
– Output registers only have synchronous resets
Many designs that run out of slices are not fully utilizing the
block RAM resources
– Synthesis tools are not yet smart enough to infer less obvious functions
Clock Enable
Control the use of clock enables from the code
– Code them only when needed
– If a low-fanout CE is necessary, use synthesis attributes to control the
use of control signals at the signal or module level
• Do not use global switches to turn off the use of CEs
 Results in an average of 25-percent LUT increase
– Consider using alternative coding methods for low-fanout clock enables
This will
map the CE
to the
control port
VHDL:
if (CE=‘1’) then
Q <= A;
Verilog:
if (CE=‘1’)
Q <= A;
VHDL:
Q <= ((not CE) AND A) OR (CE AND Q);
Verilog:
Q <= (~CE & A) | (CE & Q);
This will
map the
CE to a
LUT input
Summary
Code properly to minimize power
– Only enable BRAM during active read or write cycles
– Use low power architecting for multiple Block RAM arrays (use CORE
generator)
– Build small memory blocks with LUTs(<4k bits)
– Minimize local resets, if possible
– No reset is best since the FPGA gets a global reset automatically
• Allows inference of SRL
– Design with Synchronous Resets
• Enables inference of DSP slice and Block RAM output register
– Don’t build a reset into your design for simulation purposes
• Instead code for the INIT behavior
– Control the use of Clock Enables
Where Can I Learn More?
Xilinx online documents
– support.xilinx.com
• Spartan-6 FPGA Power Management User Guide, UG394
 Introduces the Suspend and Hibernate modes
 Describes the necessary voltage supplies
 Introduces the low-power (-1L) devices
 Describes the Power-On and Power-Down behavior
 Power Estimation options are discussed
• Power Consumption in 65 nm FPGAs, WP246
 Very useful resource to clarify this presentation
Where Can I Learn More?
Xilinx Education Services courses www.xilinx.com/training
– Designing with Spartan-6 and Virtex-6 Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
Free Video-based Training
– How Do I Plan to Power My FPGA?
– Power Estimation
– What are the Spartan-6 Power Management Features?
– What are the Virtex-6 Power Management Features?
– What are FPGA Power Management Design Techniques?
Trademark Information
Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on,
or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded,
displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or
otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of
privacy and publicity, and communications regulations and statutes.
Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents,
copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design.
Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no
obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH
YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE,
WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS,
IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES,
INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH
YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF
FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT
THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU
WITHOUT THESE LIMITATIONS OF LIABILITY.
The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe
controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons
systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You
represent that use of the Design in such High-Risk Applications is fully at your risk.
© 2012 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.
Download