How Do I Resolve
Routing Congestion?
Objectives
After completing this module, you will be able to:
 Use various methods to resolve your design’s routing congestion
 Use the PlanAhead software to optimize your design’s routing
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If you have Area Constraints…
 Consider removing Area Constraints, unless you are certain they will be
helpful
– Helpful Area Constraints only place logic near dedicated hardware or reserved I/O
pins, only
– If your design has a top-level floorplan, unnecessary Area Constraints, or
constrains a large percentage of the device, they may need to be removed
• In general the fewer the Area Constraints, the better
• A top-level floorplan usually constraints the top-most hierarchical blocks in your design,
which means that over 80% of the design is constrained
– Note that if you eventually get the design to complete PAR, you might consider readding some Area Constraints and try implementing the design again
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SmartXplorer
 Consider running SmartXplorer with the –cr (congestion reduction strategy)
option from the command line
– Note that this may have a negative impact on meeting your timing constraints
• If any of these strategies do complete routing, it could indicate that the timing
constraints are too tight
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Run Additional Cost Tables
 Run 10+ cost tables to determine how consistent the routing congestion is
– If a cost table is found where the congestion is greatly reduced or does not exist,
compare the Congestion Metric Map output (in the PlanAhead Tool) with a failing
result
• Evaluate the placement of the dedicated hardware (block RAM, DSP slice, and
distributed RAM). If certain dedicated hardware is near routing congestion, place that
dedicated hardware in the better placement.
• Refer to the Re-use Flow section of the Floorplanning Methodology Guide, UG633
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Evaluating Routing Congestion
 Import the design into the PlanAhead tool
to analyze the vertical and horizontal
routing
– Review the Analyzing Implementation
Results and Displaying Design Metrics
sections of the PlanAhead User Guide,
UG632 for more details
– After loading the design into PlanAhead,
right-click on the die view and select Metric
 Horizontal/Vertical routing
congestion per CLB
– Look for “Hot-Spots”
• These are locations on the die where most of
the vertical or horizontal routing is used up
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What to do with a “Hot Spot”
 Determine if the logic in each hot spot is
part of the same hierarchy of your design
– If it isn’t use Area Constraints to separate
the hierarchies
• Don’t allow overlapping Area Constraints
• Try not to place timing critical logic poorly
 Evaluate the primitives associated with the
hot-spots
– For example, if the logic is distributed RAM
driving DSP slice or block RAM, evaluate
the placement of these resources
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What to do with a “Hot Spot”
 Evaluate the routing associated with hotspots
– If they are high fanout nets…
• Evaluate the placement of the loads. If they
are far apart, consider grouping the logic with
an Area Constraint.
• Also consider replicating the source to reduce
the fanout
 Determine if routing congestion is near the
configuration and system monitor resources
– If so, use the environment variable
• UAP_DENSMAP_CFG_NEIGHBORHOOD_SLOPE=1
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What to do with a “Hot Spot”
 Evaluate the pinout and GT placement in
the PlanAhead tool to see if it is causing
logic to spread out
– If they are consider removing the offending
pin assignments to see if this is the cause
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Evaluate Your Use of Control Signals
 High fanout control signals
– Determine if the signals that have a fanout > 1000 are resets or clock
enables
• Review the Spartan-6 and Virtex-6 HDL Coding Techniques RELs to determine
if your design needs these signals
 Never code a reset for simulation purposes
• Also review the Retargeting Guidelines for Virtex-5 FPGAs, WP248 to
determine if your design needs these signals
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Evaluate RAM Distribution
 Evaluate your use of Block RAM and Distributed RAM utilization
– From the MAP report determine if distributed RAM is > 40% or if your use of
Block RAM is < 60%
• Don’t waste block RAM
– If your Block RAM usage is high evaluate the connectivity to these resources
and consider floorplanning your memories
• Find all block RAMs with a common connectivity and group them into a single clock
region
 Do the same with distributed RAMs
 Re-implement and re-evaluate your critical timing paths
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Evaluate Your Clock Topology
 Use your synthesis schematic viewer or the PlanAhead Tool to evaluate
your design’s usage of the clocking resources
– Look if any clocking components can be reduced
• By reducing the number of BUFGs/BUFRs in a design, more flexibility is provided to
the implementation tools
– Look for gated clocks in the design and/or clocks that might be routed on local
routing resources
• Gated clocks can be re-targeted to the CE functionality of the BUFHCE to save
routing resources
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Evaluate Your Clock Topology with
PlanAhead
 Use the Find command (from
PlanAhead) to trace your
clocking resources or look for
the primitive names
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Manage Your Device Utilization
 There is less flexibility in how the design gets implemented when the
device utilization is high (usually over 80%)
– Avoid asynchronous resets
• They prevent logic from being merged into the block RAM and DSP slice resources
• SRLs cannot be inferred with any reset behavior
– Disable KEEP HIERARCHY options and/or attributes during synthesis to
ensure all possible optimizations can be done by your synthesis tool
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Summary
 Use a minimal amount of Area Constraints until you are certain they are not
creating routing congestion
– Don’t let logic from different hierarchical blocks be placed in regions where routing
congestion is present (separate the logic)
 Consider running SmartXplorer with the –cr
– Also consider running the tools for multiple cost tables
 Evaluate your routing congestion with the PlanAhead software
– Find your “Hot-Spots”
 Evaluate your use of control signals, memory resources, and clocking
resources
 Manage your device utilization
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© Copyright 2010 Xilinx
Where Can I Learn More?
 Xilinx online documents
–
www.support.xilinx.com
• Virtex-6 FPGA Routing Optimization Design Techniques, WP381
 Synthesis tool options, Implementation tool options, etc.
• PlanAhead User Guide, UG632
 Display design metrics
• Floorplanning Methodology Guide, UG633
 How to re-use placement information (Re-use Flow)
• Retargeting Guidelines for Virtex-5 FPGAs, WP248
 Helpful resource to clarify HDL coding techniques
• Command Line Tool User Guide, UG628
 How to run SmartXplorer with congestion reduction strategies
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© Copyright 2010 Xilinx
Where Can I Learn More?
 Xilinx Education Services courses www.xilinx.com/training
– Designing with Spartan-6 and Virtex-6 Device Families course
• How to get the most out of both device families
• How to build the best HDL code for your FPGA design
• How to optimize your design for Spartan-6 and/or Virtex-6
• How to take advantage of the newest device features
 Free Video Based Training
– How To Create Area Constraints with PlanAhead
– What are the Benefits of PlanAhead?
– What Design Techniques Help Avoid Routing Congestion?
How Do I Resolve Routing Congestion? - 17
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