2010 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 2010, Montreal
100+ GHz Transistor Electronics:
Present and Projected Capabilities
Mark Rodwell
University of California, Santa Barbara
rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax
THz Transistors
Why Build THz Transistors ?
500 GHz digital logic
→ fiber optics
THz amplifiers→ THz radios
→ imaging, sensing,
communications
precision analog design
at microwave frequencies
→ high-performance receivers
Higher-Resolution
Microwave ADCs, DACs,
DDSs
Transistor figures of Merit / Cutoff Frequencies
gains, dB
H21=short-circuit current gain
MAG = maximum available
power gain:
impedance-matched
fmax
power-gain
cutoff frequency
ft
current-gain
cutoff frequency
U= unilateral power gain:
feedback nulled,
impedance-matched
What Determines Digital Gate Delay ?
Tgate  t f  ( VL / I C )( C je  6Ccbx  6Ccbi  Cwire )
CV/I terms
 ( kT / qI C )( 0.5C je  Ccbx  Ccbi  0.5t f I C / VL ) dominate
→
 Rex ( 0.5Ccbx  0.5Ccbi  0.5t f I C / VL )
 Rbb( 0.5C je  Ccbi  0.5t f I C / VL ).
analog ICs have somewhat similar bandwidth considerations...
How to Make
THz Transistors
High-Speed Transistor Design
Depletion Layers
C 
t
Fringing Capacitances
A
T
C finging / L ~ 
T
2v
I max 4vsat (Vappl   )

A
T2
C finging / L ~ 
Thermal Resistance
Bulk and Contact Resistances
Rth 
R   contact / A
contact te rms dominate
1
1
L
ln   
Kth L  W  Kth L
Frequency Limits
and Scaling Laws
of (most)
Electron Devices
t  thickness
C  area / thickness
Rtop   contact / area
Rbottom 
 contact
area

PIN photodiode
Rtop
Rbottom
 sheet width
4

length
I max, space-charge-limit  area / thickness
2
power
 length 
T 
 log 

length
 width 
To double bandwidth,
reduce thicknesses 2:1
Improve contacts 4:1
reduce width 4:1, keep constant length
increase current density 4:1
Changes required to double transistor bandwidth
We
emitter
length LE 
HBT parameter
emitter & collector junction widths
current density (mA/mm2)
current density (mA/mm)
collector depletion thickness
base thickness
emitter & base contact resistivities
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
nearly constant junction temperature → linewidths vary as (1 / bandwidth)2
LG
gate width WG 
constant voltage, constant velocity scaling
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
change
decrease 2:1
increase 2:1
increase 2:1
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
Electron Plasma Resonance: Not a Dominant Limit
T 1
Lkinetic 
A q 2nm*
T
1
Rbulk 
A q 2nm*t m
dielectric relaxation frequency scattering frequency
1 Rbulk
1 / 2
f scattering 
f dielectric 
2 Lkinetic
Cdisplacement Rbulk
1
1 


2tm
2 
n - InGaAs
3.5  10 / cm
19
p - InGaAs
7  10 / cm
19
3
Cdisplacement 
A
T
plasma frequency
1 / 2
f plasma 
LkineticCdisplacement
800 THz
7 THz
74 THz
80 THz
12 THz
31 THz
3
Thermal Resistance Scaling : Transistor, Substrate, Package
spherical flow
for r  Le
cylindrica l heat flow
near junction
Tsubstrate 
planar flow
for r  DHBT / 2
L 
P  1 1
P  Tsub  D / 2 

ln  e  
  


K InP LE  We  K InP  LE D  K InP 
D2

P
increases
logarithmi cally
insignific ant
variation
increases quadratica lly
if Tsub is constant
 1 1  Pchip
Tpackage    
 4   KCuWchip
junction temperature rise, Kelvin
140 Tsub  40 mm  (150 GHz / f clock )
120
Wiring lenghts
total
2000 - HBT CML IC
scale as
100
80
1/bandwidt h.
Power density,
substrate: cylindrical+spherical regions
60
package
40
0
100
scales as
substrate: planar region
20
(bandwidth ) 2 .
200
300
400
500
600
master-slave D-Flip-Flop clock frequency, GHz
700
Thermal Resistance Scaling : Transistor, Substrate, Package
spherical flow
for r  Le
cylindrica l heat flow
near junction
Tsubstrate 
planar flow
for r  DHBT / 2
L 
P  1 1
P  Tsub  D / 2 

ln  e  
  


K InP LE  We  K InP  LE D  K InP 
D2

P
increases
logarithmi cally
insignific ant
variation
increases quadratica lly
if Tsub is constant
 1 1  Pchip
Tpackage    
 4   KCuWchip
junction temperature rise, Kelvin
140 Tsub  40 mm  (150 GHz / f clock )
120
Wiring lenghts
2000 - HBT CML IC
Probable
best solution:
scale as
1/bandwidt h.
Thermal Vias ~500 nm below InP subcollector
Power density,
...over full active IC area.
scales as
total
100
80
substrate: cylindrical+spherical regions
60
package
40
substrate: planar region
20
0
100
(bandwidth ) 2 .
200
300
400
500
600
master-slave D-Flip-Flop clock frequency, GHz
700
Bipolar
Transistors
150 nm thick collector
256 nm InP HBT
40
340 GHz
dynamic
frequency
divider
Z. Griffith
dB
H
U
21
20
fmax = 780 GHz
10
M. Seo, UCSB/TSC
mA/mm2
10
30
10
VBB
H
dB
f
10
324 GHz
amplifier
max
2
3
4
5
12
20
21
U
E. Lind
2
20
Vout
1
V
mA/mm
VEE
0
12
10
ce
10
30
10
9
10
Hz
70 nm thick collector
M. Seo, UCSB/TSC
IMS 2010
11
10
10
10
4
0
11
Vtune
t
10
340 GHz VCO
6
2
f = 424 GHz
0
9
10
8
= 560 GHz
15
10
5
f = 560 GHz
t
0
0
9
10
J. Hacker, TSC
IMS 2010
10
10
11
10
0
12
10
1
2
V
Hz
3
4
ce
40
30
H
Z. Griffith, TSC
CSIC 2010:
to be presented
Z. Griffith
2
U
mA/mm
30
dB
204 GHz
static
frequency
divider
21
20
10 fmax = 218 GHz
20
10
f = 660 GHz
t
0
9
10
much better results in press ...
10
10
11
10
Hz
10
12
0
0
1
2
V
ce
3
InP Bipolar Transistor Scaling Roadmap
emitter 512
16
256
8
128
4
64
2
32 nm width
1 mm2 access 
base
300
20
175
10
120
5
60
2.5
30 nm contact width,
1.25 mm2 contact 
collector 150
4.5
4.9
106
9
4
75
18
3.3
53
36
2.75
37.5 nm thick,
72 mA/mm2 current density
2-2.5 V, breakdown
520
850
430
240
730
1300
660
330
1000
2000
1000
480
1400 GHz
2800 GHz
1400 GHz
660 GHz
ft
fmax
power amplifiers
digital 2:1 divider
370
490
245
150
We
Tb
Wbc
Tc
Fabrication Process for 128 nm & 64 nm InP HBTs
Chart 17
Initial Results: Refractory-Contact HBT Process
30
110 nm emitter width
30
U
H21
20
f
H21
max
= 700 GHz
Gain (dB)
Gain (dB)
270 nm emitter width
25
25
15
A = 0.11 mm x 3.5 mm
10
U
je
20
f
15
max
= 800 GHz
A = 0.27mm x 3.5mm
je
10
f = 370 GHz
t
5
5
f = 430 GHz
t
0
9
10
10
10
11
10
Freq (Hz)
12
10
0 9
10
10
10
11
10
freq (Hz)
Need to add E-beam defined base, best base contact technology
12
10
InP DHBTs: August 2010
400 500
GHz GHz
1000
600
GHz
700
GHz
800
GHz
900
GHz

popular metrics :
ft or f max alone
ft f max
Teledyne DHBT ( ft  f max ) / 2
200 nm
UIUC DHBT
800
f
max
(GHz)
NTT DBHT
250 nm
ETHZ DHBT
110 nm
600
UIUC SHBT
250 nm
UCSB DHBT
400
NGST DHBT
600nm
HRL DHBT
200
IBM SiGe
350 nm
Vitesse DHBT
200
(1 ft  1 f max ) 1
much better metrics :
power amplifiers :
PAE, associated gain,
mW/ mm
low noise amplifiers :
Fmin , associated gain,
digital :
f clock , hence
(Ccb V / I c ),
Updated Aug 2010
0
0
ft f max
400
600
ft (GHz)
800
1000
( Rex I c / V ),
( Rbb I c / V ),
(τb  τc )
670 GHz Transceiver Simulations in 128 nm InP HBT
transmitter exciter
Simulations @ 670 GHz (128 nm HBT)
LNA: 9.5 dB Fmin at 670 GHz
30
PA: 9.1 dBm Pout at 670 GHz
35
35
20
30
20
30
620
receiver
640
660
680
SP.freq, GHz
freq, GHz
(a)
700
10
0
0
720
800
820
64nm
-10
840 -10
-8860 -6
-4880 -2
(b)
VCO:
-50 dBc (1 Hz)
@ 100 Hz offset
at 620 GHz (phase 1)
128nm
4 0.986
(c)
free-running
VCO
0
Total PLL
phase noise
-50
closed-loop
VCO noise
-100
multiplied
reference noise
-150
1
10
2
3
4
10
6
10
7
950 GHz Input
-0.9
-0.95
-0.95
Vout, Vout_bar
Vout , Vout_bar
5
10
10
10
offset from carrier, Hz
-1
-1.05
-1.1
-1.15
-1
-1.05
-1.1
-1.15
197.5 10
-12
200 10
-1.2
-12
195 10
-12
Noise Figure, Conversion Gain (dB)
197.5 10
-12
time, seconds
time, seconds
Mixer:
10.4 dB noise figure
11.9 dB gain
-8
50
-0.9
-1.2
-12
195 10
1.04
-10
SP.freq, THz
freq, THz
690 GHz Input
Dynamic divider:
novel design,
simulates to 950 GHz
3
-10
1.02 -12
8 1.0010
(a)
10
3-layer thin-film THz interconnects
thick-substrate--> high-Q TMIC
thin -> high-density digital
0
-5
Pin
SP.freq, GHz
freq, GHz
5
10
0
0900 2
10
20
Gain
Pout
5
-5
128nm
0
nf(2)
dB(S(2,1))
10
15
10
20
PLL single-sideband
phase noise spectral density, dBc (1 Hz)
20
Gain
Pout
nf(2)
dB(S(2,1))
nf(2)
dB(S(2,1))
15
30
25
20
15
10
5
0
-5
-15.00
-10.00
-5.000
0.0000 5.000
LO Power
10.00
200 10
-12
1.-
THz
Field-Effect Transistors
(THz HEMTs)
FET Scaling Laws
LG
Changes required to double device / circuit bandwidth.
laws in constant-voltage limit:
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
electron mass in transport direction
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
gate width WG 
change
decrease 2:1
increase 2:1
increase 2:1
constant
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
HEMT/MOSFET Scaling: Four Major Challenges
contact regions:
need reduced
access resistivity
channel:
need higher charge density
yet keep high carrier velocity
gate dielectric:
need thinner barriers
→ tunneling leakage
channel:
need thinner layers
THz FET Scaling Roadmap
Gate length
Gate barrier EOT
well thickness
S/D resistance
effective mass
# band minima
ft
fmax
fdivider source-coupled logic
Id /Wg@ 200 mV overdrive
nm
nm
nm
1
25
0.58
4.0
100
0.05
1
18
0.41
2.8
74
0.08
2
GHz
700
770
GHz
GHz
810
150
mA/mm 0.54
mm
*m0
high-K gate dielectrics
35
0.83
5.7
150
0.05
?
13
2.0
53
9
0.21
1.4
37
0.08
3
0.08
3
1100
1600
2300
930
220
1400
300
2000
430
2900
580
0.69
0.95
1.4
1.8
0.29
source / drain regrowth
G-L transport
III-V MOSFETs with Source/Drain Regrowth
27 nm InGaAs MOSFET
Regarding
Mixed-Signal ICs
&
Waveform Generation
Clock Timing Jitter in ADCs and DACs
Timing jitter is quantitatively specified
by the single-sideband phase noise spectral density L(f).
IC oscillator phase noise varies as ~1/f2 or ~1/f3 near carrier
Impact on ADCs and DACs:
imposition of 1/fn sidebands on signal of relative amplitude L(f)
...not creation of a broadband noise floor.
Dynamic range of electronic DACs & ADCs is limited by factors
other than the phase noise of the sampling clock
Why ADC Resolution Decreases With Sample Rate
Dynamic Range Determined by Circuit Settling Time vs. Clock Period
dynamic hysteresis
metastability
# bits 
1
fsamplet latch
IC time constants→ Resolution decreases at high sample rates
Fast IC Waveform Generation: General Prospects
Waveform generator → fast digital memory & DAC
Parallel digital memory and 200 Gb/s MUX is feasible
cost limits: power & system complexity vs. # bits, GS/s
Performance limit: speed vs. resolution of DAC
faster technologies → increased sample rates
Feasible ADC resolution:
12 SNR bits @ 4 GS/s feasible using 500 nm (400GHz) InP HBT.
Feasible sample rate will scale with technology speed..
THz Transistors
&
Mixed-Signal ICs
Few-THz Transistors
Few-THz InP Bipolar Transistors: can it be done ?
Scaling limits: contact resistivities, device and IC thermal resistances.
62 nm (1 THz ft , 1.5 THz fmax ) scaling generation is feasible.
700 GHz amplifiers, 450 GHz digital logic
Is the 32 nm (1 THz amplifiers) generation feasible ?
Few-THz InP Field-Effect Transistors: can it be done?
challenges are gate barrier, vertical scaling,
source/drain access resistance, channel density of states.
2DEG carrier concentrations must increase.
S/D regrowth offers a path to lower access resistance.
Solutions needed for gate barrier: possibly high-k (MOSFET)
Implications: 1 THz radio ICs, ~200-400 GHz digital ICs, 20 GHz ADCs/DACs