CPE 201
Digital Design
Lecture 20:
Sequential Logic (5)
Lecture Outline
• Excitation Tables
• Controller Design Examples
• State Reduction
2
Understanding the Controller’s
Behavior
x=0
00
Off
b
x=0
00
Off
b’
b
x=1
x=1
x=1
01 On1
10 On2
11 On3
b
0
0
0
0
x
0
x=0
00
Off
b’
x=1
x=1
x=1
01 On1
10 On2
11 On3
b
1
0
0
0
n1
0
clk
0
0
state=00
x=1
01 On1
10 On2
11 On3
b
1
0
1
1
s1
0
0
s0
0
1
state=00
1
0
0
n0
0
0
clk
x
n1
1
n0
1
0
s0
0
x=1
0
1
n0
0
s1
0
0
x
x=1
n1
0
0
0
clk
b
b’
0
clk
s1
s0
0
1
1
0
state=01
Inputs:
b
Outputs:
x
3
Controller Example:
Button Press Synchronizer
bi
Button press
synchronizer
controller
bo
• Want simple sequential circuit that converts
button press to single cycle duration, regardless
of length of time that button actually pressed
– We assumed such an ideal button press signal in
earlier example, like the button in the laser timer
controller
4
Controller Example:
bi’
A
bi
bo=0
B
bi
C bi’
bi’
bi
bo=1
bo=0
bi
bo
Combinational
logic
FSM
outputs
FSM inputs: bi; FSM outputs: bo
FSM
inputs
Button Press Synchronizer (cont.)
Step 2: Create architecture
n1
n0
s1
clk
n1 = s1’s0bi + s1s0’bi
n0 = s1’s0’bi
bo = s1’s0bi’ + s1’s0bi = s1’s0
s0
State register
Combinational logic
Step 1: FSM
bo
bi
n1
FSM inputs: bi; FSM outputs: bo
bi’
bi’
00
bo=0
bi
01
bo=1
bi
10
n0
bi
bi’
s1
bo=0
clk
s0
State register
Step 3: Encode states
Step 4: State table
Step 5: Create
combinational circuit
5
Sequence Decoder Example
• Design a circuit to detect three or more consecutive 1’s
in a string of bits coming through an input line
Present State
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Input
x
0
1
0
1
0
1
0
1
Next State
A
B
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
Output
y
0
0
0
0
0
0
1
1
A(t+1)= Σ(3,5,7)
B(t+1)= Σ(1,5,7)
Y(A,B,x)= Σ(6,7)
6
Synthesis Using D Flip-Flops
• Need 2 D flip-flops to represent the four states
A(t+1)=DA(A,B,x)= Σ(3,5,7)
B(t+1)=DB(A,B,x)= Σ(1,5,7)
Y(A,B,x)= Σ(6,7)
DA = Ax + Bx
DB = Ax + B’x
y = AB
7
Sequence Detector Logic Diagram
DA = Ax + Bx
DB= Ax + B’x
y=AB
8
Excitation Tables
– Input equations for the circuit
must be derived indirectly from
x
b
Combinational n1
logic
n0
s1
s0
clk
State register
the state table
• Excitation tables can help
FSM
outputs
• Why?
FSM
inputs
• Using flip-flops other than D can be complicated
DA DB
JA KA JB KB
– They give us the flip-flop input that would cause a
state transition
9
Excitation Tables – JK Flip-Flop
• During design we know the
transition Q(t)  Q(t+1) and want
to know inputs JK that lead to the
transition
Q(t+1) = JQ’(t) + K’Q(t)
Excitation table
Q(t)
Q(t+1)
J
K
Input situation
0
0
0
X
Reset, No change
0
1
1
X
Set, Complement
1
0
X
1
Reset, Complement
1
1
X
0
Set, No change
10
Excitation Tables – T Flip-Flop
Q(t+1) = TQ’(t) + T’Q(t) = T XOR Q
Excitation table
Q(t)
Q(t+1)
T
Input situation
0
0
0
No change
0
1
1
Complement
1
0
1
Complement
1
1
0
No change
11
Synthesis Using JK Flip-Flops
Present State
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Input
x
0
1
0
1
0
1
0
1
Next State
A
B
0
0
0
1
1
0
0
1
1
0
1
1
1
1
0
0
JA
0
0
1
0
x
x
x
x
Flip-Flop Inputs
KA
JB
KB
x
0
x
x
1
x
x
x
1
x
x
0
0
0
x
0
1
x
0
x
0
1
x
1
Available from the FSM diagram
• We have to include J, K input conditions,
derived from the excitation table
12
Synthesis Using JK Flip-Flops
13
Synthesis Using JK Flip-Flops
14
Synthesis Using T Flip-Flops
• E.g.: 3-bit Binary Counter
– The counter counts with the clock
State diagram
15
Synthesis Using T Flip-Flops
Present State
A2 A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Next State
A2
A1
A0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
Flip-Flop Inputs
TA2
TA1
TA0
0
0
1
0
1
1
0
0
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
State diagram
16
Synthesis Using T Flip-Flops
17
Controller Example: Sequence
Generator
•
Want to generate sequence 0001, 0011, 1100, 1000, (repeat)
– Each value for one clock cycle
w
x
y
z
Inputs: none; Outputs: w,x,y,z
wxyz=0001
wxyz=1000
A
D
Combinational
logic
s1
B
C
wxyz=0011
wxyz=1100
Step 1: Create FSM
Inputs: none; Outputs: w,x,y,z
n1
n0
wxyz=1000
A
D
s0
00
01
State register
clk
wxyz=0001
Step 2: Create architecture
11
10
B
C
wxyz=0011
wxyz=1100
Step 3: Encode states
w
w = s1
x = s1s0’
y = s1’s0
z = s1’
n1 = s1 xor s0
n0 = s0’
x
y
z
s1
clk
Step 4: Create state table
s0
State register
n0
n1
Step 5: Create combinational circuit18
Controller Example: Secure Car Key
•
Inputs: a; Outputs: r
(from earlier example)
Wait
Step 1
r=0 a
a’
K1
K2
K3
K4
r=1
r=1
r=0
r=1
a
r
Step 2
Combinational
logic
n2
n1
n0
s2 s1 s0
clk
State register
Inputs: a; Outputs: r
000
Step 3
r=0
a
a’
001
010
011
100
r=1
r=1
r=0
r=1
We’ll omit Step 5
Step 4
19
FSM Example: Code Detector
•
Unlock door (u=1) only when
buttons pressed in sequence:
u
r
g
b
a
Red
Green
Blue
– start, then red, blue, green, red
•
s
Start
Input from each button: s, r, g, b
– Also, input a indicates that some
colored button pressed
•
FSM
–
–
–
–
–
–
Wait for start (s=1) in “Wait”
Once started (“Start”)
If see red, go to “Red1”
Then, if see blue, go to “Blue”
Then, if see green, go to “Green”
Then, if see red, go to “Red2”
Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0 s
Start
u=0
Door
lock
Code
detector
s’
ar’
ab’
ag’
ar’
a’
ar
Red1
u=0
ab
a’
Blue
u=0
ag
a’
Green
u=0
ar
a’
Red2
u=1
• In that state, open the door (u=1)
Q: Can you trick this FSM to open the door,
– Wrong button at any step, return to without knowing the code?
A: Yes, hold all buttons simultaneously
“Wait”, without opening door
20
Improve FSM for Code Detector
Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0
s’
s
ar’ ab’
ag’
ar’
Start
u=0
a’
ar
Red1
u=0
•
ab
a’
ag
Blue
u=0
Green
a’
u=0
ar
a’
Red2
u=1
New transition conditions detect if wrong button pressed, returns to
“Wait”
21
Common Pitfalls Regarding Transition
Properties
a
• At most one condition
must be true
– For all transitions
leaving a state
• At least one condition
must be true
– For all transitions
leaving a state
b
If ab=11
next state=?
a
a
a’b
What if
ab=00?
a’b
a’b’
a
a’b
22
Verifying Correct Transition Properties
• Can verify using Boolean algebra
• At most one condition true
– AND of each condition pair (for transitions
leaving a state) should equal 0  proves
pair can never simultaneously be true
• At least one condition true
– OR of all conditions of transitions leaving a
state should equal 1  proves at least one
condition must be true
a
– Example
Answer:
a * a’b
= (a * a’) * b
=0*b
=0
OK!
a + a’b
= a*(1+b) + a’b
= a + ab + a’b
= a + (a+a’)b
=a+b
Fails! Might not
be 1 (i.e., a=0,
b=0)
a’b
Q: For shown transitions, prove whether:
* At most one condition true (AND of each pair is always 0)
* At least one condition true (OR of all transitions is always 1)
23
Evidence that Pitfall is Common
• Recall code detector FSM
Wait
– We “fixed” a problem with the
u=0 s
transition conditions
– Do the transitions obey the
Start
two required transition
u=0ar
properties?
• Consider transitions of state
Start, and the “at most one
property ar * a(r’+b+g)
a’ *true”
a(r’+b+g)
ar * a’
= (a*a’)r = 0*(r’+b+g)
=0
=0
Red1
u=0
s’
a’
ab
a’
Blue
u=0
ag
a’
Green
u=0
ar
a’
Red2
u=1
Intuitively: press red and blue
buttons at same time:
conditions ar, and a(r’+b+g) will
both be true. Which one should
be taken?
= (a*a)*r*(r’+b+g) = a*r*(r’+b+g)
= arr’+arb+arg
= 0 + arb+arg
= arb + arg
Q: How to solve?
= ar(b+g)
A: ar should be arb’g’
Fails! Means that two of Start’s
(likewise for ab, ag, ar)
transitions could be true
a
24
Simplifying Notations
• FSMs
– Assume that unassigned
output is implicitly 0
clk
a=0
b=1
c=0
a=0
b=0
c=1
b=1
c=1
a
• Sequential circuits
– Assume that unconnected
clock inputs are implicitly
connected to same
external clock
a
25
State Reduction and Assignment
• Goal: Reduce the number of states while
keeping the external input-output requirements
• 2m states need m flip-flops, so reducing the
states may reduce flip-flops
• If two states are equivalent, one can be
removed
• What are equivalent states?
26
State Reduction Example
• For state reduction only inputoutput sequences are important
– States are only used to provide the
output sequence
010101110100 applied and start from state a
State
input
output
a a b c d e f f g f g
0 1 0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 1 0 1 0 0
a
27
State Reduction Example
Present State
a
b
c
d
e
f
g
Next State
x=0
x=1
Output
x=0
x=1
a
c
a
e
a
g
a
0
0
0
0
0
0
0
b
d
d
f
f
f
f
0
0
0
1
1
1
1
States e and g are equal since for each member of the
set of inputs, they give the same output and send the
circuit either to the same state or an equivalent state
28
State Reduction Example
Present State
a
b
c
d
e
f
Next State
x=0
x=1
Output
x=0
x=1
a
c
a
e
a
e
0
0
0
0
0
0
b
d
d
f
f
f
0
0
0
1
1
1
Table and state diagram after the first reduction: g is removed and replaced by state e.
NEW equal states: d and f
29
State Reduction Example
Present State
a
b
c
d
e
Next State
x=0
x=1
Output
x=0
x=1
a
c
a
e
a
0
0
0
0
0
b
d
d
d
d
0
0
0
1
1
If we apply the same input sequence:
State
input
output
a a b c d e d d e d e
0 1 0 1 0 1 1 0 1 0 0
0 0 0 0 0 1 1 0 1 0 0
a
Reduced state diagram
Table and state diagram after the second reduction: f is
removed and replaced by state d.
30
Design Procedure
1.
2.
3.
4.
5.
6.
7.
From word description, derive state diagram
Reduce the number of states
Assign binary values to states
Obtain the binary coded state table
Choose the type of flip-flop used
Derive the simplified flip-flop input and output equations
Draw the logic diagram
31
Chapter Summary
• Sequential circuits
– Have state
• Created robust bit-storage device: D flip-flop
– Put several together to build register, which we used to hold state
• Defined FSM formal model to describe sequential
behavior
– Using mathematical models – Boolean equations for combinational
circuit, and FSMs for sequential circuits
• Defined step process to convert FSM to sequential circuit
– Controller
• So now we know how to build sequential circuits (known
as controllers)
32
Readings
• Chapter 5
– Sections 5.8
33