Lecture 20 OUTLINE The MOSFET (cont’d) • Qualitative theory • Field-effect mobility • Long-channel I-V characteristics Reading: Pierret 17.2, 18.3.4; Hu 6.3-6.6 Qualitative Theory of the NMOSFET VGS < VT : depletion layer The potential barrier to electron flow from the source into the channel region is lowered by applying VGS> VT Inversion-layer “channel” is formed VGS > VT : Electrons flow from the source to the drain by drift, when VDS>0. (IDS > 0) VDS 0 The channel potential varies from VS at the source end to VD at the drain end. VDS > 0 EE130/230M Spring 2013 Lecture 20, Slide 2 MOSFET Linear Region of Operation For small values of VDS (i.e. for VDS << VGVT), I DS WQinvv WQ inv m eff VDS WQ inv meff L where meff is the effective carrier mobility Hence the NMOSFET can be modeled as a resistor: RDS VDS L I DS Wmeff Coxe (VG VT ) EE130/230M Spring 2013 Lecture 20, Slide 3 Field-Effect Mobility, meff Scattering mechanisms: • Coulombic scattering • phonon scattering • surface roughness scattering EE130/230M Spring 2013 Lecture 20, Slide 4 MOSFET Saturation Region of Operation VDS = VGS-VT VDS > VGS-VT ID • When VD is increased to be equal to VG-VT, the inversion-layer charge density at the drain end of the channel equals 0, i.e. the channel becomes “pinched off” • As VD is increased above VG-VT, the length DL of the “pinch-off” region increases. The voltage applied across the inversion layer is always VDsat=VGS-VT, and so the current saturates. I Dsat I DS V EE130/230M Spring 2013 DS VDsa t • If DL is significant compared to L, then IDS will increase slightly with VDS increasing VDS>VDsat, due to “channel-length modulation” Lecture 20, Slide 5 Ideal MOSFET I-V Characteristics Enhancement-Mode N-channel MOSFET Linear region EE130/230M Spring 2013 Lecture 20, Slide 6 Impact of Inversion-Layer Bias • When a MOS device is biased into inversion, a pn junction exists between the surface and the bulk. • If the inversion layer contacts a heavily doped region of the same type, it is possible to apply a bias to this pn junction. N+ poly-Si + + + + + + + + SiO2 N+ - - - - - - - - - p-type Si EE130/230M Spring 2013 • VG is biased so that surface is inverted • n-type inversion layer is contacted by N+ region • If a bias VC is applied to the channel, a reverse bias (VB-VC) is applied between the channel and body Lecture 20, Slide 7 Effect of VCB on fS, W and VT • Application of a reverse body bias non-equilibrium 2 Fermi levels (one in n-type region, one in p-type region) are separated by qVBC fS is increased by VCB • Reverse body bias widens W, increases Qdep and hence VT 2qN A Si (2fF VCB ( y)) VT ( y) VFB VCB ( y) 2fF Cox EE130/230M Spring 2013 Lecture 20, Slide 8 Derivation of NMOSFET I-V • VD > VS • Current in the channel flows by drift • Channel voltage VC(y) varies continuously between the source and the drain 2qN A Si (2fF VCB ( y)) VT ( y) VFB VCB ( y) 2fF Cox • Channel inversion charge density Qdep ( y) Qinv ( y) Coxe VG VFB VCB ( y) 2fS C oxe W EE130/230M Spring 2013 Lecture 20, Slide 9 1st-Order Approximation • If we neglect the variation of Qdep with y, then Qdep 2qN A Si (2fF VSB ) 2qN A Si (2fF VSB ) VT ( y) VFB VCB ( y) 2fF VSB VSB Cox VT ( y) VT VSB VCB ( y ) where VT is defined to be the threshold voltage at the source end: 2qN A Si (2fF VSB ) VT VFB VSB 2fF Cox The inversion charge density is then Qinv Coxe VG VT VSB VCB ( y) Coxe VG VT VS VC ( y) EE130/230M Spring 2013 Lecture 20, Slide 10 NMOSFET Current (1st-order approx.) • Consider an incremental length dy of the channel. The voltage drop across this region is dVC I DS dR I DS L 0 dy WTinv I DS I DS dy dy qm eff nWTinv Qinv m eff W VD I DS dy m eff WQinv (VC )dVC I DS I DS VS VD W m eff Qinv (VC )dVC VS L VD W m eff Coxe VG VT VS VC dVC VS L VDS W m eff Coxe VG VT VDS in the linear region L 2 EE130/230M Spring 2013 Lecture 20, Slide 11 Saturation Current, IDsat (1st-order approximation) IDS saturates when VD reaches VG-VT Set VD = VG-VT in the equation for ID I Dsat W Coxe m eff (VG VT ) 2 2L for VD VDsat VG VT 2qN A Si (2fF VSB ) VT VFB VSB 2fF Cox EE130/230M Spring 2013 Lecture 20, Slide 12 Problem with “Square Law Theory” • Ignores variation in depletion width with distance y: Qinv Coxe VG VT VS VC 2qN A Si (2fF VSB ) where VT VFB VSB 2fF Cox EE130/230M Spring 2013 Lecture 20, Slide 13 Modified (Bulk-Charge) I-V Model VG VT In linear region: VD VDsat m W m I Dlin Coxe m eff (VG VT VDS )VDS L 2 In saturation region: VD VDsat I Dsat where m 1 EE130/230M Spring 2013 Cdep,min Coxe 1 VG VT m W Coxe m eff (VG VT ) 2 2mL 3Toxe WT Lecture 20, Slide 14 since Si 3 SiO2 MOSFET Threshold Voltage, VT The expression that was previously derived for VT is the gate voltage referenced to the body voltage that is required reach the threshold condition: 2qN A Si (2fF VSB ) VT VFB VSB 2fF Cox Usually, the terminal voltages for a MOSFET are all referenced to the source voltage. In this case, 2qN A Si (2fF VSB ) VT VFB 2fF Cox and the equations for IDS are W m Coxe meff (VGS VT VDS )VDS L 2 VDS VDsat VGS VT / m I Dlin EE130/230M Spring 2013 Lecture 20, Slide 15 W Coxe m eff (VGS VT ) 2 2mL VDsat VGS VT / m I Dsat VDS The Body Effect Note that VT is a function of VSB: 2qN A Si (2fF VSB ) VT VFB 2fF Cox 2qN A Si (2fF ) 2qN A Si (2fF ) 2qN A Si (2fF VSB ) VFB 2fF Cox Cox Cox 2qN A Si VT 0 2fF VSB 2fF VT 0 g 2fF VSB 2fF Cox where g is the body effect parameter When the source-body pn junction is reverse-biased, |VT| is increased. Usually, we want to minimize g so that IDsat will be the same for all transistors in a circuit. EE130/230M Spring 2013 Lecture 20, Slide 16 MOSFET VT Measurement • VT can be determined by plotting IDS vs. VGS, using a low value of VDS IDS VGS EE130/230M Spring 2013 Lecture 20, Slide 17 Channel Length Modulation • Recall that as VDS is increased above VDsat, the width DL of the depletion region between the pinch-off point and the drain increases, i.e. the inversion layer length decreases. 1 1 DL I Dsat 1 L DL L L DL VDS VDsat DL VDS VDsat L IDS I Dsat W Coxe m eff (VGS VT ) 2 1 VDS VDsat 2mL VDS EE130/230M Spring 2013 Lecture 20, Slide 18 Long-Channel MOSFET I-V Summary • In the ON state (VGS>VT for NMOS; VGS<VT for PMOS), the inversion layer at the semiconductor surface forms a “channel” for current to flow by carrier drift from source to drain In the linear region of operation (VDS < (VGSVT)/m): VDS I DS I Dlin WQinvv WQ inv m eff WQ inv m eff L mVDS Qinv Coxe VGS VT 2 m 1 Cdep,min Coxe m eff f VGS In the saturation region of operation (VDS > (VGSVT)/m): W I DS I Dsat Coxe m eff (VGS VT ) 2 1 VDS VDSsat 2mL EE130/230M Spring 2013 Lecture 20, Slide 19