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  1. Engineering & Technology
  2. Computer Science
  3. Assembly Language
A Unified View of Non-monotonic Core Selection and Application
A Unified View of Non-monotonic Core Selection and Application
A two-word instruction is stored at location 350 with its
A two-word instruction is stored at location 350 with its
a TigerSHARC Embedded Processor ABOUT ADSP-TS201S SILICON ANOMALIES
a TigerSHARC Embedded Processor ABOUT ADSP-TS201S SILICON ANOMALIES
a TigerSHARC Embedded Processor
a TigerSHARC Embedded Processor
A Syntactic Approach to Foundational Proof-Carrying Code Zhaozhong Ni
A Syntactic Approach to Foundational Proof-Carrying Code Zhaozhong Ni
A Syntactic Approach to Foundational Proof-Carrying Code 191
A Syntactic Approach to Foundational Proof-Carrying Code 191
A Simplified MIPS Processor in Verilog
A Simplified MIPS Processor in Verilog
A Simple Processor Prof. Sirer CS 316 Cornell University
A Simple Processor Prof. Sirer CS 316 Cornell University
a SHARC Embedded Processor
a SHARC Embedded Processor
a SHARC Embedded Processor
a SHARC Embedded Processor
A secure processor architecture for encrypted computation on untrusted programs Please share
A secure processor architecture for encrypted computation on untrusted programs Please share
A Processor Hakim Weatherspoon CS 3410, Spring 2012 Computer Science
A Processor Hakim Weatherspoon CS 3410, Spring 2012 Computer Science
A Performance Analysis Framework for Identifying
A Performance Analysis Framework for Identifying
A novel 12-bit _ISA_ for introducing novice students to instruction set
A novel 12-bit _ISA_ for introducing novice students to instruction set
A Modern Multi-Core Processor
A Modern Multi-Core Processor
A miniPascal compiler for the E-machine by Frances Wren Goosey
A miniPascal compiler for the E-machine by Frances Wren Goosey
A Lean FPGA Soft Processor Built Using a DSP Block
A Lean FPGA Soft Processor Built Using a DSP Block
A Laboratory Manual for the SPARC
A Laboratory Manual for the SPARC
A framework to accelerate sequential programs on homogeneous multicores Please share
A framework to accelerate sequential programs on homogeneous multicores Please share
A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps
A Framework for Accelerating Bottlenecks in GPU Execution with Assist Warps
A FPGA Implementation of a MIPS - Klipsch School of Electrical and
A FPGA Implementation of a MIPS - Klipsch School of Electrical and
A Floating Point Divider for Complex Numbers in the NIOS II
A Floating Point Divider for Complex Numbers in the NIOS II
A Dynamically Recompiling ARM Emulator
A Dynamically Recompiling ARM Emulator
A Dynamic Multithreading Processor
A Dynamic Multithreading Processor