Voltus IC Power Integrity Solution
Break-through in Power Signoff
Jerry Zhao
Product Marketing Director
Power Sign-off Products, SSV
Nov 21st, 2013
Agenda
1. Introduction – Challenges and Cadence Solution
2. Voltus - Performance, Capacity and Accuracy
3. Voltus and Design Closure
4. Summary
2
© 2013 Cadence Design Systems, Inc. All rights reserved.
Design Challenges in Mobile Computing Era
 Mobile Devices Require Low Power
‒
‒
Extending battery life
Increasing device reliability
 Design Complexity Increases in Low
Power ICs
‒ Advanced design techniques
‒ Increasing IP content and functionality
‒ Tighter design margins
 Power Integrity is Critical for Successful
Design Signoff
‒ Occurs late in the design cycle
‒ Impacts timing and physical design closure
Complexity in Power Signoff Grows as Design Complexity Increases
3
© 2013 Cadence Design Systems, Inc. All rights reserved.
Power Solutions Have not Kept Pace with
Designer’s Requirements
Trend of Dynamic Analysis Performance
 Time Required for Power Analysis is
Increasing due to
‒ Growing design complexity and size
‒ More complex analysis requirements
Runtime (days)
20
15
10
5
0
90
 Current Solutions don’t Consider the
Impact of Power on Timing Closure
65
40
28
16
Technology Node (nm)
Trend of Power Ramp-up Performance
140
‒ Thermal breakdown
‒ Complete power integrity analysis from
chip to package to system
Runtime (hrs)
 New Challenges in 3DIC Technology
120
100
80
60
40
20
0
1
2
4
10
# of Power Domain
15
Designers Require New Technologies for Power Signoff
4
© 2013 Cadence Design Systems, Inc. All rights reserved.
What Did Cadence Announce in Nov. 12th?
 Voltus™ IC Power Integrity Solution
‒
‒
‒
‒
‒
Break-through technology in power integrity
analysis and signoff
Up to 10X faster performance over existing
solutions
Most accurate electrical design signoff and
closure solution
Industry’s 1st power integrity tool integrated
with static timing analysis
Integration with Cadence digital & analog,
package & board, and system level solutions
for fast design closure
 TSMC 16nm FinFET Certification
 Customer Endorsements
‒
‒
‒
Freescale Semiconductor
Integrated Device Technology
Tilera
Fastest Path to Design Signoff
5
© 2013 Cadence Design Systems, Inc. All rights reserved.
The Voltus IC Power Integrity Solution
• Massively parallel execution
• Scalability across computer network
• Hierarchical analysis
• SPICE-like accuracy
• Integrated power and timing signoff
• Foundry certification on advanced nodes
6
© 2013 Cadence Design Systems, Inc. All rights reserved.
• Early grid analysis in implementation
• Physically-aware grid optimization
• Chip and system co-design analysis
A Glance at Voltus
Key Functionalities
IR-Drop & EM
Performance
De-Cap
Power Switch
Power Calculation
Capacity
Integration
IR-Aware STA
(Tempus)
Accuracy
Chip-PKG-PCB
(Sigrity)
7
© 2013 Cadence Design Systems, Inc. All rights reserved.
Early Rail Analysis
(EDI)
Voltus Technology Advantages
Performance, Capacity and Accuracy
8
© 2013 Cadence Design Systems, Inc. All rights reserved.
Voltus - Exceptional Performance
Innovation Through Parallelization
 Massively Parallel Execution
‒
‒
Multi-threaded
Distributed Processing
Voltus
 Extra High Capacity
‒
‒
Innovative hierarchical analysis
Capacity up to 1B instances
 No Loss of Accuracy
‒
‒
‒
…
SPICE-accurate rail matrix solver
Accurate power grid RC extraction
Accurate instance power distribution
Massively Parallel Architecture Offers up to 10X Better Performance
9
© 2013 Cadence Design Systems, Inc. All rights reserved.
Voltus Capacity Enablement
Hierarchical Analysis
Hierarchical Analysis Flow
Blk1 Power
Grid Analysis
Blk N Power
Grid Analysis
………
H-PGV
H-PGV
H-PGV
Top-level
(Hierarchical Data)
ECO
Full Chip
Power Signoff Analysis
Accuracy Comparison
Flat
 Hierarchical methodology
– Block level power grid network captured by
Power-Grid-View modeling (H-PGV)
– Top level circuitry combined with these H-PGVs
to form a complete grid network
– “Top-down” or “Bottom-up” flows
 Targeting designs with 100+ million
instances
– Silicon successes on 400+ M instances designs
– Capacity up to 1 Billion instances
Hierarchical
 Productivity gains without loss of accuracy
– Performance improvement up to 4X vs. “flat” on
large designs
– ECO flow at block level to fix EMIR issues
through decap optimization, etc
28mV (VDD)
9mV (VSS)
10
27mV (VDD)
9mV (VSS)
© 2013 Cadence Design Systems, Inc. All rights reserved.
Voltus Accuracy Foundations
Advanced Algorithm
 Full scale SPICE-level PG matrix
‒ Grid simulation from SPICE engine
 Advanced parallel execution
‒ No loss of accuracy with multi-CPU
 Accurate power calculation
‒ Liberty, activity, signal propagation
Accurate IP Modeling
 Power-Grid-View (PGV)
‒ Cell intrinsic coupling cap
‒ PG extraction shown visibility inside
‒ Current char for multi-mode macro
 ECSM-Power
‒ SPICE-level current vs. NLPM
11
© 2013 Cadence Design Systems, Inc. All rights reserved.
Embedded Cadence Sign-off Tools
 QRC: RC Extraction
‒ field solver accuracy on PG nets
 Tempus: Static Timing
‒ Signal propagation, timing window
 Spectre APS: Transistor Simulation
‒ PGV modeling, LDO Co-Sim
Strong Eco-System Support
 TSMC Certification
‒ N16 FinFET & Design Reference Flow
 IP Suppliers on PGV library
‒ TSMC, Samsung, ARM
 EM Rules Support
‒ “qrcTechFile” format
TSMC 16nm FinFET Certification
 Recently certified by TSMC on
16nm FinFET (v0.5)
‒ TSMC OIP: San Jose, 10/1/2013
‒ Both gate level (Voltus) and transistor
level (VPS)
 FinFET stresses ElectroMigration
‒ Increased power density
‒ Reduced wire width
‒ Vertical current directions
 What does certification cover ?
‒ Power EM and Signal EM
‒ EM rules and accuracy
‒ IR-Drop accuracy
 What do EM rules include?
‒
‒
‒
‒
12
Current direction
Width/length dependencies
Temperature rating factors
:
© 2013 Cadence Design Systems, Inc. All rights reserved.
Power EM (AVG current)
DC Current
charge
discharge
AC Current
Cload
Voltus – Accurate Electrical Signoff
Next-generation, Unified Solution in Voltus + Tempus
 Power Integrity Directly Affects Timing
‒
‒
‒
Timing is most sensitive to power supply (VDD)
Current segmented, point tool based solutions from
multiple vendors are less accurate and cumbersome
Leads to guard banding which increases pessimism in
Static Timing
 Voltus + Tempus: New, Unified Signoff Solution
‒
‒
Simultaneous power and timing analysis and closure
Increases accuracy in STA by up to 3%
•
•
Reduces timing pessimism
More realistic voltage drop across the chip and its affect on
timing
Industry 1st Integrated Solution for Power and Timing Signoff
13
© 2013 Cadence Design Systems, Inc. All rights reserved.
Voltus and Design Closure
Power Grid Analysis, Optimization, ECO Flow, ….
14
© 2013 Cadence Design Systems, Inc. All rights reserved.
Voltus – Fast Design Closure
Complete Design Flow from Chip to System
Encounter
 Tight Integration with IC Physical Implementation
‒
‒
‒
Early rail analysis & ECO: during power planning stages
De-cap & ECO: IR-drop and leakage reduction
Power gate switching& ECO: rush current, turn-on time
Tempus
APS
Virtuoso
Signoff
Ecosystem
Palladium
 Chip-package-PCB Co-Simulation and Analysis
Sigrity
‒
‒
‒
Accurate power grid networks for chip and board
Electrical-Thermal analysis
3DIC support, including CoWoS (2.5D)
Productivity Improvements in IC Design Closure and System Design
15
© 2013 Cadence Design Systems, Inc. All rights reserved.
Early Rail Analysis
Bringing Power Grid Analysis and Design to Floorplanning Stage
ERA at Various Stage
EDI
0.4A
(PWL)
Floorplanning
1Amp
(avg)
2 Amp
3 Amp
(PWL)
(avg)
Std. Cell Placement
CTS/Optimization
Fully Places Instances
(Power Calc and Distribution)
Signal Routing
Voltus Engine
 Flexible power-constraints specifications
‒
‒
Interactive current region specification on not placed blocks
Power calculation on place and/or routed blocks
 Early feedback for more efficient power grid network optimization
‒
‒
‒
16
Power grid width, straps, vias, epeats, spacing and IO/bump locations
Power switch analysis to refine size and placement
High Quality Power Grid Implementation for Faster Singoff Convergence
© 2013 Cadence Design Systems, Inc. All rights reserved.
Power Gate Switching Analysis & Optimization
Switches, Rush Current and EDI ECO
Ron
Power
Ramp-up
ON
 Up to 100’s of power domains
‒
‒
Coarse-grain or fine-grain switches
Comprehensive ramp-up sequence
 Steadystate analysis (static, dynamic)
OFF
ON
Ron
Always-on VDD rail
Coarse-grain
Switched VDD rail
Logic/power rail
within block
VSS rail
17
© 2013 Cadence Design Systems, Inc. All rights reserved.
‒
‒
ON: switches impacts on power/EMIR
OFF: power/leakage savings
 Power ramp-up analysis
‒
‒
Rush current and turn-on time
Impacting IR-Drop to surrounding blocks
 Power switch optimization
‒
‒
Switches: sizes, numbers, locations
ECO in EDI: upsizing, downsizing, or more
switches inserted
De-coupling Cap Optimization
Size and location of de-caps
 De-coupling caps and power grid
‒
‒
Reducing localized dynamic IR-drop
Adding leakage, slowing down recovery
 Calculating de-cap value
‒
‒
Optimization
User-defined voltage thresholds
The required Q to compensate IR-drop
 Placement-aware de-cap optimization
‒
‒
A universal voltage threshold
Swapping filler cell with de-cap cell
 Timing-aware de-cap optimization
‒
‒
A tighter voltage threshold for critical paths
De-cap cells for no timing violation
 De-cap removal and ECO flows in EDI
18
© 2013 Cadence Design Systems, Inc. All rights reserved.
Voltus Advantage - Palladium Dynamic Power Analysis
Real-world, Application-specific Stimulus
Power
Power
Budget
VCD/TCF/FSDB
Deep Cycle ‘What if’
time
Palladium®
Dynamic Power Analysis
Voltus Vector-based EMIR
 Palladium® Dynamic Power Analysis (DPA)
‒
‒
‒
Real test environment for realistic stimulus generation
Deep cycle dynamic power analysis to identify peak power windows for the chip
Output chip activities in zero-delay (VCD/TCF/FSDB) format
 Vector-based Voltus IR-drop and EM analysis
‒
‒
Annotating TWF into DPA output to generate vectors with delays for Voltus
Power vector profiling and peak power window power signoff
Well above 90% Accuracy Correlation with Silicon Measurement
19
© 2013 Cadence Design Systems, Inc. All rights reserved.
Complete Cadence Power Integrity Solutions
Full-chip Power Integrity Analysis for all Designs
Virtuoso
Voltus
“Voltus”
Spectre APS/XPS
Full-chip
Power Grid Views
PGV
“Voltus”
Virtuoso Power System
Block & IP
(Transistor)
Digital (SoC)
IR drop and EM
Mixed Signal
Custom/Analog
IR Drop & EM
Accurate Transistor EMIR Analysis, High Quality Analog IP Grid Modeling
20
© 2013 Cadence Design Systems, Inc. All rights reserved.
Chip-Package-Board Co-Simulation
Integrated Voltus and Sigrity Design Flows
 Sigrity package model generation
Chip-Package-Board Varieties
‒
‒
XtractIM: broadband SPICE format
PowerSI: S-parameter format
 Voltus die model generation
2D
Voltus
2.5D (Si Interposer)
Package Model
3D (TSV)
Sigrity
‒
‒
‒
Broadband SPICE format
Frequency and time domains
Single-port and N-port (up to 100’s)
 Sigrity MCP interface
Die-Model
‒
‒
Model Connection Protocol
Name- based or location-based
 Complete power integrity solutions
‒
‒
21
© 2013 Cadence Design Systems, Inc. All rights reserved.
Chip: Voltus + package model
System: PowerDC + die model
Electrical-Thermal Co-Simulation
Temperature
Map
PKG
Leakage
Power
Chip 1
Chip 2
Chip 3
Chip-PKG-PCB
Temperature
PCB
Power
Map
Temperature
Voltus
Thermal Co-Simulation
PowerDC
 Thermal Runaway
‒
‒
Positive feedback among chip’s Temperature, leakage, and power dissipation
Temperature dependent IR-drop and EM
 Thermal Simulation in “Voltus + PowerDC”
‒
‒
‒
‒
22
Voltus output: temperature and location dependent “Power Map” file
PowerDC computes detailed temperature distribution for Chip-PKG-PCB (T vs. time)
Voltus reads back “Temperature Map” file for EMIR convergence
Thermal view available in 2D/3D
© 2013 Cadence Design Systems, Inc. All rights reserved.
In Summary
 Voltus Accelerates Design Closure and Signoff
‒
‒
‒
‒
Up to 10X faster than competing solutions
Up to 1 billion instances in capacity
Voltus and Tempus are integrated for more accurate
electrical design closure
Integration with other Cadence tools for fast and
complete design closure
 Cadence Solves the Design Complexity
Challenges in Power Signoff
‒ Enabling designers to meet their targets
‒ Enhanced performance, accuracy and design closure
Voltus – The New Standard in Power Signoff
23
© 2013 Cadence Design Systems, Inc. All rights reserved.