Cadence Tempus™ Timing Signoff
Solution
SSV Summit
November 2013
Industry needs for next generation signoff
• Signoff closure up to 40% of the
design flow
Design Flow Components
Signoff
P&R
Front End
• Capacity for +100M cell designs
with 100s of timing views
Design Cycle Distribution %
• Need faster runtimes
• Better accuracy to reduce
pessimism, power, area
65nm
40nm
28nm
Technology Node
2
© 2013 Cadence Design Systems, Inc. All rights reserved
20nm
The Tempus™ Timing Signoff Solution
• Massively parallelized computation
• Scalable to 100s of CPUs
• Optimized data structures
• Up to 10X reduction in closure time
• Placement and routing aware
• Unlimited MMMC capacity
• Up to 10X faster path-based analysis (PBA)
• Advanced process modeling
• TSMC-certified accuracy
Tempus – It’s about TIME
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© 2013 Cadence Design Systems, Inc. All rights reserved
Performance background
Stacked performance enablement
• Optimized multi-threading
• Distributed processing
• Incremental & hierarchical
analysis
• Concurrent multi-mode multicorner analysis
• Parallelized path based analysis
MMMC
Concurrency
Incremental Analysis
Distributed Processing
Flat Single View (Multi-Threading)
Technology
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© 2013 Cadence Design Systems, Inc. All rights reserved
Performance metrics
Parallelized processing
• Combines multi-threading with
distribution
• Simple setup
MMMC
Concurrency
– User specifies desired resources
• Parallelization transparent to user
• Up to 50M cells analyzed in one
hour
Incremental Analysis
Distributed Processing
Flat Single View (Multi-Threading)
• Low memory footprint
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© 2013 Cadence Design Systems, Inc. All rights reserved
Concurrent MMMC view analysis
• Analyzes all modes and
corners in one timing session
• Runs on one compute server
• More than 2X faster with same
hardware
– Less than 20% memory overhead
per additional timing view
• Reduces hardware resource
requirement
6
© 2013 Cadence Design Systems, Inc. All rights reserved
MMMC
Concurrency
Incremental Analysis
Distributed Processing
Flat Single View (Multi-Threading)
Path-based analysis (PBA)
Reduced pessimism and runtime
• Graph based analysis is fast
but inherently pessimistic
PBA reduces pessimism
0
• Path based analysis is slow
but reduces pessimism
• Tempus solves PBA
reporting runtimes
– Parallelized computation
-0.01
© 2013 Cadence Design Systems, Inc. All rights reserved
100
200
300
400
500
600
Pessimism
reduction
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
AOCV PBA Slack
-0.09
AOCV Graph Based
-0.1
7
0
-0.02
Path Slack
– Accurate transitions and
derates
Path Number
Tempus timing closure
• Full timing/optimization
solution
• Delay and SI
• Distributed MMMC
• Physically aware
• Setup/hold/DRV/leakage
optimization
Place and route
Physical
view
(LEF/
DEF)
2-3
Iteration
Physically
aware
ECO
Tempus
Distributed
MMMC
delay
calculation
and STA
Physicallyaware
optimization
Hold, DRV,
setup,
leakage
– Path or graph based
Timing closed
8
© 2013 Cadence Design Systems, Inc. All rights reserved
Tempus resonates with users
What we said…
Community feedback
(courtesy of DeepChip)…
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© 2013 Cadence Design Systems, Inc. All rights reserved.
Global Foundries tapeout success
• Presented at ARM®
TechCon 2013
• Cortex®-A12 testchip
– 28nm SLP Technology
• Close collaboration
– ARM, Global Foundries,
Cadence
• Full Cadence flow
– Final signoff with Tempus!
• Key Tempus technologies
– MMMC analysis
– Physically aware optimization
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© 2013 Cadence Design Systems, Inc. All rights reserved
In summary
• Cadence is solving the design complexity challenge
– Eliminating the signoff bottleneck
– Enables power, performance and time-to-market goals
• Tempus™ accelerates timing analysis and closure by
weeks
– As much as 10x faster
– Handles 100’s of millions of cells
– Optimizes timing across hundreds of views
• Strong customer demand
– Multiple evaluations and customers
• Early tapeout success
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© 2013 Cadence Design Systems, Inc. All rights reserved.
More to come!
"Cadence, Encounter, Tempus, Virtuoso and the Cadence logo are trademarks of Cadence Design Systems, Inc. All
other trademarks and logos are the property of their respective holders."
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© 2013 Cadence Design Systems, Inc. All rights reserved