Voltus IC Power Integrity Solution—
The Answer to Power Signoff Challenges
Ben Gu, Engineering Director, Silicon Signoff and Verification, DGS
CDNLive Shanghai
5 August 2014
Agenda
1. Introduction—Challenges and Cadence Solutions
2. Voltus Performance, Capacity, and Accuracy
3. Voltus Solution and Design Closure
4. Summary
2
© 2014 Cadence Design Systems, Inc. All rights reserved.
Introduction—Challenges and Solutions
3
© 2014 Cadence Design Systems, Inc. All rights reserved.
Design challenges in mobile computing era
 Mobile devices require low power
‒
‒
Extending battery life
Increasing device reliability
 Design complexity increases in lowpower ICs
‒ Advanced design techniques
‒ Increasing IP content and functionality
‒ Tighter design margins
increasing due to
‒ Growing design complexity and size
‒ More complex analysis requirements
20
Runtime (days)
 Time required for power analysis is
Trend of Dynamic Analysis Performance
15
10
5
0
90
65
40
28
Technology Node (nm)
Complexity in power signoff grows as design complexity increases
4
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16
Voltus IC Power Integrity Solution
Next-generation SoC power signoff platform
 Launched in November 2013
– Customer endorsements: Freescale/IDT/Tilera
 Breakthrough massively parallel execution
technology in SoC power signoff
 Up to 10X faster performance gain over
existing solutions
 Capacity up to 1 billion instances with
hierarchical analysis capability
 Integrated with key Cadence® technology for
fast design signoff and closure
 Certified for TSMC 16nm FinFET process
Performance, accuracy, and design closure
5
© 2014 Cadence Design Systems, Inc. All rights reserved.
Virtuoso Power Systems
Transistor-level power signoff solution
 Unified transistor-level power signoff
in Virtuoso® platform
Virtuoso
DSPF
 SPICE-level accuracy
Spectre APS,
XPS
 Up to 10X performance gains
through parallel execution
 Power-grid-view (PGV) modeling for
Voltus™ SoC full-chip-level power
signoff
VPS
IR-Drop
Power/Signal EM
EMIR on
Layout
 Certified for TSMC 16nm FinFET
Accuracy, usability, and seamless flow with Voltus solution
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© 2014 Cadence Design Systems, Inc. All rights reserved.
PGV
Complete Cadence power integrity solutions
Full-chip power integrity analysis for all designs
Virtuoso
Voltus
Voltus
Spectre APS, XPS
Full-Chip
PGV
Power Grid Views
Voltus
Virtuoso Power System
Block and IP
(Transistor)
Digital (SoC)
IR Drop and EM
Mixed Signal
Custom/Analog
IR Drop and EM
Accurate transistor EMIR analysis, high-quality analog IP grid modeling
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© 2014 Cadence Design Systems, Inc. All rights reserved.
TSMC 16nm FinFET certification
 TSMC N16nm FinFET certification
– TSMC Symposium, San Jose, 4/22/2014
o Both gate and transistor level
 What does certification cover?
– Power net and signal net EM
o DC and AC
– IR-Drop accuracy
o Static and dynamic IR-Drop
 Complex design rules in EM checks
– (LiL)M0: different EM rules per current
direction
– Length and width dependency
– Current direction dependency
– Temperature dependency
– VIA shape rules for fracturing
 QRC’s EM-aware extraction for Virtuoso
Power System accuracy
– Understand metal’s topology/geometry
– Accurate Ls for R and EM limit calculation
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LA
LB
Mx +1
Mx
LC
Mx +1
Mx
Voltus and Sigrity chip-PKG-PCB co-simulation
Accurate power signoff for highly coupled power delivery network
PKG Model
Temperature Map
Sigrity
Voltus
MCP
Die Model
Power Map
 Die-model and PKG/PCB-model in Broadband SPICE® format for
―Voltus™ + Sigrity™‖ co-simulation
 Power map/temperature map for electro-thermal co-analysis
 Comprehensive power and signal integrity analysis
3D-IC technology
9
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Voltus Technology Advantages
Performance, Capacity, and Accuracy
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Voltus solution—Exceptional performance
Innovation through parallelization

Massively parallel execution
‒
‒

Voltus
Extra-high capacity
‒
‒

Multi-threaded
Distributed processing
Innovative hierarchical analysis
Capacity up to 1B instances
…
No loss of accuracy
‒
‒
‒
SPICE-accurate rail matrix solver
Accurate power grid RC extraction
Accurate instance power distribution
Massively parallel architecture offers up to 10X better performance
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Stackable performance enablement
Scalable across multi-CPUs, multi-machines
– Multi-threaded on single machine
– Distributed processing on multiple machines
100
hr
 Massively parallel execution
Dynamic Vector-Based IR-Drop
~80M Instances
Runtime
N28nm
(From MT to DP)
~6X
 Parallel execution for all phases of a Voltus™
run
– Instance power calculation
– Power grid RC extraction
– Rail matrix solver
 Near-linear, scalable rail solver best for timeconsuming analysis types
– Power ramp-up sequences
– Long VCD simulation window
 Customer success on a large processor chip
– ~80M instances on N28nm
– Scalable parallel execution for performance gain
and memory footprint reduction
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50
~9.7X
~15.6X
~22.3X
0
1CPU
1CPU
2.5
8CPU 16CPU 32CPU 64CPU
8CPU
16CPU
32CPU
2X1664CPU4X16
Distributed Processing Scalability
(From 1M to 4M)
~2.3X
2
1.5
1
~35 %
0.5
0
1 Machine
16CPU/250G Per
Machine
2 Machines
4 Machines
Performance Gain
Memory Reduction
Customer Success Stories
Scalable across multi-CPUs, multi-machines
 ~180M Instances with >400M Nodes
 TSMC28nm
 7 VDD Nets and 1 VSS Net
Competitor
Results
Design Spec
IC #1: Large Mobile Processor
 Dynamic Power Signoff
~5 days
Voltus on 32CPU/1Machine
31 hr
Voltus on 64CPU/3Machine
20 hr
 150M Instances with >2B Resistors
 TSMC28nm
 20 VDD Nets and 3 VSS Net
Results
Design Spec
IC #2: Large 3DIC Processor
 All Macros/SRAMs in Detailed PGV
Competitor
N/A
Voltus on 32CPU/1Machine
-
Voltus on 64CPU/3Machine
12 hr
13
 ~120M Instances with over 1B resistors
 TSMC28nm
 1 VDD Net and 1 VSS Net
 1200 RTL-VCD Dynamic Power Signoff
© 2014 Cadence Design Systems, Inc. All rights reserved.
Results
Design Spec
IC #3: Large Network Processor
Competitor
No
Voltus on 32CPU/2Machine
6h/300G
Voltus on 64CPU/4Machine
4h/170G
Voltus solution—Capacity enablement
Hierarchical analysis for extra large designs without loss of
accuracy
 Targeting designs with 150+ million instances
– Silicon successes on 400+M instances designs
– Capacity up to 1 billion instances
Hierarchical Analysis Flow
Blk1 Power
Grid Analysis
 NVIDIA presented Voltus™ results on their
large GPUs at Signoff Summit (Nov. 2013)
H-PGV
H-PGV
H-PGV
 Hierarchical methodology
– Block-level power grid network captured by powergrid-view modeling (H-PGV)
– Top-level circuitry combined with these H-PGVs to
form a complete grid network
– ―Top-down‖ or ―bottom-up‖ flows
Blk N Power
Grid Analysis
………
Top-level
(Hierarchical Data)
Fix
Full Chip
Power Signoff Analysis
Accuracy Comparison
Flat
Hierarchical
– “A disruptive runtime improvement‖ with Voltus
solution
– Design and run results:
o ~400M instances on TSMC 28nm
o 21hrs and ~725GB on a 1TB server with 32 CPUs
28mV (VDD)
9mV (VSS)
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27mV (VDD)
9mV (VSS)
Voltus solution—Accuracy foundations
Advanced Algorithm
 Full-scale SPICE-level PG matrix
‒ Grid simulation from SPICE engine
 Advanced parallel execution
‒ No loss of accuracy with multi-CPU
 Accurate power calculation
‒ Liberty, activity, signal propagation
Accurate IP Modeling
 Power-grid-view (PGV)
‒ Cell intrinsic coupling cap
‒ PG extraction shown visibility inside
‒ Current char for multi-mode macro
 ECSM-Power
‒ SPICE-level current vs. NLPM
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Embedded Cadence Signoff Tools
 QRC: RC extraction
‒ Field solver accuracy on PG nets
 Tempus™ Timing Signoff Solution:
Static timing
‒ Signal propagation, timing window
 Spectre® APS: Transistor Simulation
‒ PGV modeling, LDO Co-Sim
Strong Ecosystem Support
 TSMC certification
‒ N16 FinFET and Design Reference Flow
 IP suppliers on PGV library
‒ TSMC, Samsung, ARM
 EM rules support
‒ “qrcTechFile” format
Voltus Solution—Fastest Path to Design Closure
Integration in Cadence Design Flows
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Voltus solution—Fast design closure
Complete design flow from chip to system
Encounter
 Tight integration with IC physical implementation
‒
‒
‒
Early rail analysis and ECO: During power planning stages
De-cap and ECO: IR-Drop and leakage reduction
Power gate switching and ECO: Rush current, turn-on time
Tempus
Spectre
APS
Virtuoso
Signoff
Ecosystem
Palladium
 Chip-package-PCB co-simulation and analysis
Sigrity
‒
‒
‒
Accurate power grid networks for chip and board
Electrical-thermal analysis
3D-IC support, including CoWoS (2.5D)
Productivity improvements in IC design closure and system design
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Early rail analysis
Bringing power grid analysis and design to floorplanning stage
ERA at Various Stage
EDI
0.4A
(PWL)
Floorplanning
1Amp
(avg)
2 Amp
3 Amp
(PWL)
(avg)
Std. Cell Placement
CTS/Optimization
Fully Places Instances
(Power Calc and Distribution)
Signal Routing
Voltus Engine
 Flexible power-constraints specifications
‒
‒
Interactive current region specification on not placed blocks
Power calculation on place and/or routed blocks
 Early feedback for more efficient power grid network optimization
‒
‒
‒
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Power grid width, straps, vias, repeats, spacing, and I/O/bump locations
Power switch analysis to refine size and placement
High-quality power grid implementation for faster signoff convergence
© 2014 Cadence Design Systems, Inc. All rights reserved.
Unified solution in Voltus and Tempus tools
 Iterative timing/IR-drop analysis
 Delay calculation based on instance-specific
voltage
– Voltage scaling in Tempus™ solution requires multiple
libraries
o 3 libraries for best scaling, 2 required at a minimum
– Min/max voltages applied based on launch/capture
path and setup/hold checks
– Internal instance rail voltage file format for fast
iterations
– Critical net pruning for next-iteration IR-Drop analysis
• Increases accuracy in STA vs. OCV derate
methodologies
– Reduces timing pessimism
– More realistic modeling of voltage drop across the chip
and its affect on timing
Tempus/Voltus
Timing based on modeling voltage
variation and vice-versa
Tempus
Voltus
At least one iteration or more required
to reduce pessimism vs. OCV derates
Industry 1st integrated solution for power and timing signoff
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Voltus Summary
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In summary
 Voltus™ IC Power Integrity Solution
accelerates design closure and signoff
‒
‒
‒
‒
Up to 10X faster than competing solutions
Up to 1 billion instances in capacity
Voltus and Tempus™ solutions are integrated for
more accurate electrical design closure
Integration with other Cadence® tools for fast
and complete design closure
 Cadence solves the design complexity
challenges in power signoff
‒
‒
Enabling designers to meet their targets
Enhanced performance, accuracy, and design
closure
Voltus solution—The new standard in power signoff
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© 2014 Cadence Design Systems, Inc. All rights reserved.
© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Broadband SPICE, Palladium,
Spectre, and Virtuoso are registered trademarks and Sigrity, Tempus, and Voltus are trademarks of Cadence Design Systems, Inc. in
the United States and other countries. ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.
All rights reserved. All other trademarks are the property of their respective owners.