FPGA Calculator Core
Final Presentation
Chen Zukerman
Liran Moskovitch
Advisor : Moshe Porian
Duration: semesterial
December 2012
Contents
•
•
•
•
•
•
•
•
•
Project Overview
Top Architecture
Micro Architecture
Testability
Synthesis Results
Hardware Debugging
Project Educational Value
Project Movie
Lab Demo
Project Overview
Hardware implementation of calculator core :
• Positive integers
• Operands: ‘+’ , ’-’ , ’x’, ‘^’ , ‘ { ‘ , ‘ } ‘
• Precedence rules compatible
• Manually acquisition Input via Matlab GUI
• Result display + debugging feedback on GUI screen
Result
FPGA
Calculator Core
Top Architecture
Altera Cyclone II FPGA
WBS3
WBS1
Wishbone Intercon
GUI MATLAB
Uart In
115200 bits/sec
WBM1
RX PATH
Uart Out
115200 bits/sec
WNB2
TX PATH
WBS2
FPGA Clock, 50[MHZ]
FPGA Reset
Sys_clk,
100[MHZ]
Clock &
Reset
Sys_reset
CALC_CORE
WBM3
integrated
Implemented
Data Flow
Altera Cyclone II FPGA
Type
Address
WBS3
WBM1
Postfix Data
.
RX PATH
.
Data Length
CALC_CORE
Result
Result
FF
Wishbone Intercon
GUI MATLAB
Infix - DataWBS1
.
.
FF
Uart In
115200 bits/sec
Uart Out
115200 bits/sec SOF
Type
Type
TXAddress
PATH
Data Length
Address
Result
Data Length
CRC
Postfix Data
.
.
FF
EOF
FPGA Clock, 50[MHZ]
Infix - Data
.
.
FPGA
FFReset
CRC
EOF
WNB2
SOF
WBS2
Sys_clk,
100[MHZ]
Clock &
Reset
Sys_reset
WBM3
integrated
Implemented
Micro Architecture
02
00
Calculator Core in action
07
09
0A
1
5A
detailed view
00
00
00
5A
09
0A
1
1
1
07
09
0A
0A
09
82
FF
0A
82
09
FF
00
5A
0A
09
09
FF
82
0A
5A
00
5A
1
03
5A
09
0A
03
Testability
• Multi-Level
Top Level Testing
testingand
environments
simulating environment
were implemented
:
Goals :
1. functionality verification (in system boundaries)
2. verification that hardware and software calculation results are equal
PLL Vs. PLL Bypass
• The top level contains PLL unit that produces system clock
• Simulating The top level with PLL unit is slow
• PLL BYPASS
 Disables PLL unit and produce system clock manually
 Implemented one hierarchy above the PLL unit
in order to get faster simulation time (if … generate)
 Choosing between PLL and PLL BYPASS is done by generic
sim_clk_gen_g (if true – PLL is disabled, otherwise enabled)
GUI
Exhibit the data to transmit
Exercise display
Method select
Hardware result
Software result
Enter the exercise
Gui messages
GUI - Capabilities
Operational features:
• Receive data from the user
• Data abstraction – easy and simple operation
• Generates only correct packets with legal values
• Method choosing.
Debug features:
• Transferred data display
• Messages display
• Generates text files available for simulation
Operation Table
Operation
Binary code
Hex code
Select value
(
10010101
85
-
)
10010110
86
-
^
10000011
83
011
x
10000010
82
010
+
10000000
80
000
-
10000001
81
001
End of Postfix\infix
11111111
FF
-
Text Files
Calculation string txt file format :
• Data
General
linecomment
- full packet
–comment:
desired
calculation
test
literally,
string
explanation,
Different
notations
infix
, postfix
, postfix in Clarifications
hex + operatoretc.
conversion
Result
stringsignals
txtPostfix
file data
formatInfix
: data
Wishbone
ADR – Client inner addressEnd of postfix
End
of infix
CRCEOFClarifications etc.
• Comment
DataTGA
General
line
: full
infix
– desired
expected
+ result
test result
literally,
[hex]string
explanation,
SOFcomment
––Client
TGDpacket
Type
–notation
data
length
Wishbone
signals
Expected result CRCEOF
SOF
Text File
• Calculation string txt file example (4 strings):
String generator + checker
• Allows simple & fast testing and simulation
• Working with multiple strings one after the other
• Automatic feedback – message in the transcript window
String generator + checker example
Full packet calculation string
Full packet result string
String Generator opens the input txt file
String
Generator
and Checker
simulation
reports
– Transcript Window
String
Generator
closes
the input
txt file
End of successful top level test
Test Plan
• For simulation and hardware as well
• Blocks Basic Tests (inputs/outputs limits and special cases):
• General Tests (inputs/outputs limits and special cases):
Subtractor
Adder
Power
basic
basic
basic
tests:
tests:
tests:
Multiplier
basic
tests:
 Simple string using each operator once
 Strings using same operator all along
 Strings using different operator in the beginning of the string
 Each operator used twice in a single string
 Short string
 Long string
 Brackets testing (in different location along the string)
 Bigger\Smaller Right\Left Operand
Synthesis Results
Max Frequency
• Required frequency : 100 [MHz]
• Actual Max frequency : 133.87 [MHz]
Hardware Debugging
• Problem : first programming on FPGA … nothing happens
(GUI does not receive the returned full packet result string) .
• Source : The reset button on the DE2 board is active low while the PLL reset
polarity (predefined by the MegaWizard) is active high .
• Solution : adding the pll_reset signal which insures, that when the FPGA reset
button is active ('0'), the PLL reset would be active as well with the
appropriate polarity ('1') .
• Conclusion :
 Fundamental principle - system synthesis MUST come only AFTER
successful simulation - Early detection of the problem .
 MegaWizard PLL RESET (areset) is always active high ('1'). Special
attention should be paid to the reset polarity issue .
 Programming indication led could be useful .
Project Educational Value
• Planning and Specifying a Project
• Writing reusable generic code
• Profound acquaintance with communication protocols : UART, Wishbone
• Integration of many components
• Verifying logic correctness using smart simulators, waveforms, text files
and scripts (do files)
• Using the GUI for hardware Testing and also as a producer of text files
which are used later by the smart simulators
• Documentation of the work done
• SVN is a very useful tool
• Seriousness, Persistence, spending time and a will to learn and
understand are a Guarantee of success 
Project Movie
http://www.youtube.com/watch?v=0POkQuCi9Tk
Lab Demo