Power and Ground Routing
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Power Planning
• New technologies:
 Great power budget
 Dense power grids
• Reasons:
 Power supply scales more slowly than Moore’s law
−  Current supplied to chip increase
 Market demands for functionality
Up to 20%-40% of metal resources for P&G nets!
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• Intel’s 45 nm process
Routing Layers
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Metal Layers
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Power Planning
• Power planning:
1. Power routing
2. Placement of power supply IO pads (or bumps)
− Preferably near highly active regions
−  minimize IR drop

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P&G Distribution
• P&G distribution for a custim chip floorplan
G V G V
Power and ground rings per block or abutted blocks
G V G V G V
Trunks connect rings to each other or to top-level power ring
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Supply Nets
• Supply nets characteristics:
 Large
 Span across the entire chip
 Routed before any signal
 Use top two metal layers
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Supply Net Widths
• Wire widths:
 Must be adjusted to accommodate their respective estimated branch currents
• Logic gates:
 Net segment width: IR drop < 5% VDD
− Wider segments: lower voltage drop
− Sometimes: < 10% VDD (5% for VDD, 5% for Gnd)
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Types of Power Planning

− Only two supply nets are present
− A cell needs a connection to both supply nets

− In most modern chips
− Compensates for IR drops
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Planar Routing
Step 1: Planarize net topology
 As both power and ground nets must be routed on one layer
− Split the design using Hamiltonian path
Step 2: Layer assignment
 Assign net segments to appropriate layers
Step 3: Determine widths of net segments
 A segment ’s width ∝ ∑currents from all the cells to which it connects
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Planar Routing
1.
Planarize net topology:
 Hamiltonian path:
− allows both supply nets to be routed across the with no conflicts
 Gnd enters from left, VDD from right
GND VDD
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Planar Routing
1.
Planarize net topology:
 Both nets grow in a tree-like fashion
 Separated by Hamiltonian path
 Exact routes depend on the pin locations.
− Cells are connected wherever a pin is encountered.
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Planar Routing
2.
Layer assignment to nets based on:
 Routability
 Resistance and capacitance of each available layer
 Design rule information
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GND
Planar Routing
• Determine widths of net segments
 Based on maximum current flow: KCL
VDD
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Planar Routing
• For large currents
 Designers extend the “width” of the “planar” route in the vertical dimension with superposed segments on multiple layers that are stapled together with vias.
• Width determination: iterative process current Timing & noise IR drop
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Mesh Routing
Step 1: Creating a ring
 Surround the entire core area of the chip, and possibly individual blocks
 Connects supply I/O cells
 Electrostatic discharge protection structures
 May use all layers (except metal1)  low resistance
Power rail
Ring
Pad
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Mesh Routing
Step 2: Connecting I/O pads to the ring
 Each I/O pad: a number of
“fingers”
 Should be maximally connected to the power ring
− On each of several metal layers  low resistance
Power rail
Connector
Ring
Pad
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Step 3: Creating a mesh
Mesh Routing
 A set of stripes at defined pitches on two or more layers
Power rail  Width and pitch:
− From power consumption
− And design rules
 In pairs:
− Alternating VDD-Gnd, Gnd-VDD
 Layers:
Connector
− Upper most (thickets)
− Sparser at lower layers (to avoid signal routing congestion)
Ring
Pad
Mesh
 Vias:
− Stripes on adjacent layers: connected with as many vias as possible
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VDD
VDD GND
GND
Mesh Routing
Step 4: Creating Metal1 rails
 where P&G network meets cells.
 Width and pitch:
− Determined by std-cell library
 Std-cells laid out backto-back
−  share rails
Power rail
VDD
GND
VDD
GND
Ring
Pad
Connector
Mesh
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Mesh Routing
Step 5: Connecting the Metal1 rails to the mesh
Power rail
Connector
Ring
Pad
Mesh
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Mesh Routing
Power rail
Connector
M1
Ring
Pad
Mesh
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M1 to M3: for signal routing
M4 to M8: for power routing
(2-layers in practice)
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
Metal4 mesh
M1
Mesh Routing
2

Metal6 mesh
1

Metal5 mesh
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
16
 4

Metal7 mesh
4

Metal8 mesh
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
Metal1 rail
VDD
Metal4 mesh
GND
Metal4 mesh
Metal4
Via3
Metal3
Via2
Metal2
Via1
Metal1
GND rail
VDD rail
M1-to-M4 connection
Metal6
Via5
Metal5
Via4
Metal4
M4-to-M6 connection
Metal8
Via7
Metal7
Via6
Metal6
M6-to-M8 connection
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