LPC Speech Coder
on the TI C6x DSP
Mark Anderson, Jeff Burke
EE213A / EE298-2
Prof. Ingrid Verbauwhede
Summary
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Implementation platform
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Architecture clock frequency
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Texas Instruments TMS320C6000
Low-quantity cost US $35 (‘C6211)
150 MHz (‘C6211)
Throughput
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75-80 channels @ 8000 samples/sec
Summary
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Total energy per sample
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1.8 uJ/sample
‘Area’
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1.2% of cycle budget per chan. per frame
8.5% of unified memory per channel
25% of unified memory for algorithm
Summary
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Flexibility of implementation
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SegSNR_A:
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High; programmable processor with C
compiler, GUI debugger & simulator
?
SegSNR_Q:
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26 dB (voiced segments)
Architecture overview
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256-bit VLIW
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Two “clustered” data paths
Four functional units in each data path
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16x16 multiply
Two ALUs
Data addressing unit
32-bit instruction for each functional unit
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(256 bit “instruction” for 8 func. Units)
Data path diagram
Architecture overview
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Split register file
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Only two cross-paths exists
Cluster is limited to one source read from
opposite register file per cycle.
Data types
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8, 16, 32-bit with 40-bit accumulate
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40-bit = register pair
Memory architecture
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‘C6211 (US$35) has a cache!
4kB L1 Instruction cache (L1P)
4kB L1 Data cache (L1D)
64kB L2 Unified memory and/or cache
Extra DMA channels
Memory architecture
Design Tools
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Command-line
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Compiler, debugger, simulator
Code Composer Studio
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Same tools
Windows NT GUI
30-day “evaluation” license
Draconian copy protection, pulls out the
rug from under you
Design Flow
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Consolidate Matlab reference into a
single function
Matlab rewritten C-style
Verified C-style Matlab
C prototype created
Imported into Code Composer,
optimized & simulated
Fixed-point quantization
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Input samples
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16-bit, normalized to [-1,1)
<1.15> format used
Coefficient quantization
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Hamming window, pre-emphasis, FIR
<1.15> format used
No noticeable change in characteristics
Fixed-point quantization
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Most values 16 bit
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Take advantage of 16x16 fast multipliers
Remain close to other class
implementations
Add metric for overpowered LPC engine
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Use # of channels as performance metric
Fixed-point quantization
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Energy stored in <5.27>
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Temporary values stored in <10.30>
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Prevent overflow, provide precision for low
energy segments
Take advantage of extended precision
Modified autocorrelation used <16.0>
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All whole numbers
Fixed-Point SNR
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Matlab simulation of magnitude
truncation
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Tools again.
SegSNR_A = ?
SegSNR_Q = 26 dB
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Voiced segments only
Sent_female test data
Performance results
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Initial version: 80,000 CPU cycles/frame
Optimization
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Take advantage of VLIW, pipelining
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Use TI’s DSP Library
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observe assembly, modify C loops
Assembly advantage without assembly
Optimized version: 30,182 cycles/frame
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Had to stop early, still at least 5K cycles wasted
Performance
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Then, the tool license expired.
The tool would not install on other
machines.
TI responded, but wasn’t too helpful.
Moral #1: Avoid the evaluation
version.
Moral #2: Give tools away to sell
hardware
Cycle count details
Routine
% Cycles/frame
Windowing, pre-emphasis
4.3
1285
Energy calc
0.8
254
Autocorrelation in Levinson-Durbin 8.0
2421
Autocorrelation in pitch detection
51
15334
Algorithm total
95
28561
Total w/ housekeeping
30182
Additional optimizations
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Use more DSPLIB routines
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Autocorrelation
Assembly-level optimization
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Code size reduction?
Reduce number of buffers to reduce L1D
usage per frame
Energy per sample
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‘C6211 consumes 1.24W
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75% high activity / 25% low activity
1.24W / 80 channels
= 15.5mW/channel
15.5 mJ/sec/channel * 1/8000
= 1.8 uJ / sample
Number of channels
150 x 106 cycles/sec x 0.02 sec/frame
= 3.0 x 106 cycles/frame
3.0 x 106 cycles/frame / 30,182 cycles
= 99 channels
Memory
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‘C6211 Cache complicates estimates
Performance is 85-99% of optimal for
typical applications
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30,182 cycles becomes
35,508 cycles/frame for 85% efficiency
=> now support only 86 channels
Memory
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Try to account for off-chip memory
transfers
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~220,000 cycles for 150ns fetches
for 80 channels
=> support 75-80 channels
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Unable to verify/simulate because of
unexpected tool expiration
Memory
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L2 usage
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~16kB Code size thanks to VLIW
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Remaining used by data for channels
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512 32-byte instruction clusters
More suited for ‘C6201 & larger processors
480 bytes each (8.5% of remaining memory)
L1 usage
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L1P: Can’t tell because of cache
L1D: 2.2kB (~56%)
Tool comments
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Powerful, easy to use IDE…
When it worked.
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Licensing problems for eval version
Debugging support a bit odd
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puts/printf
C6x Conclusions
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Easily support 75-80 channels of coding
26 dB fixed-point SNR, 16-bit types
VLIW = Large code size
Cache on a low-end DSP!
Good tools,
but draconian copy protection